CN105940381A - Data reorder during memory access - Google Patents
Data reorder during memory access Download PDFInfo
- Publication number
- CN105940381A CN105940381A CN201380081205.0A CN201380081205A CN105940381A CN 105940381 A CN105940381 A CN 105940381A CN 201380081205 A CN201380081205 A CN 201380081205A CN 105940381 A CN105940381 A CN 105940381A
- Authority
- CN
- China
- Prior art keywords
- memory controller
- data
- register file
- vector register
- instruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0613—Improving I/O performance in relation to throughput
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
Abstract
Embodiments including systems, methods, and apparatuses associated with reordering data retrieved from a dynamic random access memory (DRAM). A memory controller may be configured to receive an instruction from a central processing unit (CPU) and, based on the instruction, retrieve a sequential data from a DRAM. The memory controller may then be configured to reorder the sequential data and place the reordered data in one or more locations of a vector register file.
Description
Technical field
Embodiments of the invention relate generally to the technical field of memory access.
Background technology
Background technology provided in this article describes the purpose for the context usually presenting disclosure.Current nomination
The work for being been described by this background section of inventor and originally may not obtain existing when submitting to
The aspect having the description of technical qualification is recognized as pin prior art of this disclosure the most implicitly.Unless this
Otherwise indicating in literary composition, the method described in this section is not the prior art of the claim in the disclosure, and not
It is recognized as prior art because being included in this section.
May require many application of intensive calculating and particularly high-performance calculation application (such as figure) may be right
Vector works.Such as, data can be loaded in vector register file and then multiple by with parallel work
Vector processing unit processes.Specifically, data can be divided between multiple vector registors of vector register file, and
And then, vector processing unit can process the data in given vector registor.
In an embodiment, from multiple storage address retrieval data and write data into the process vector registor can
To be referred to as " gathering " operation.On the contrary, can from the process that vector registor is written to multiple memory address locations by data
To be referred to as " dispersion " operation.
Accompanying drawing explanation
By combining the described in detail below of accompanying drawing, will readily appreciate that embodiment.For the ease of this description, similar accompanying drawing
Labelling refers to similar structural detail.By way of example rather than reality is illustrated by the way of restriction in each figure of accompanying drawing
Execute example.
Fig. 1 illustrates the example system including Memory Controller according to various embodiments.
Fig. 2 illustrates the sample table of operation of reordering according to the memorizer of various embodiments.
Fig. 3 illustrates the replaceable sample table of operation of reordering according to the memorizer of various embodiments.
Fig. 4 illustrates the instantiation procedure for the data read from memorizer that reorder according to various embodiments.
Fig. 5 illustrates the example system being configured to implement procedures described herein according to various embodiments.
Detailed description of the invention
In the following detailed description, with reference to the accompanying drawing of its part of formation, the most similar reference refers to from start to finish
Similar part, and wherein show, by the way of diagram, the embodiment that can put into practice.It being understood that without departing from this
In the case of scope of disclosure, it is possible to use other embodiments and structure or logical changes can be made.Therefore, in detailed below
Description is not taken in a limiting sense, and the scope of embodiment is limited by appended claims and equivalent thereof.
This document describes device, method and storage medium that the process with alphabetic data is associated.Specifically, leaving over it is
In system, vector register file can include multiple vector registor, and multiple vector processing unit unit can configure
One-tenth processes the data of each corresponding vector registor.Such as, alphabetic data can be divided into volume of data " chunk ", and
And each chunk can be processed by different vector processing units.
In certain embodiments, for concrete vector processing unit, process concrete data chunks rather than another data
It is desired that chunk is probably conjunction.In existing Legacy System, alphabetic data can read from memorizer, and alphabetic data is every
One chunk can be placed in the vector registor of vector register file.Then, various vector registor can be confused
In the order of data so that desired data chunks is in the desired vector registor of vector register file.
Finally, data can be processed by various vector processing units.
But, embodiment herein provides a kind of process, and it can improve and loads data into vector processing unit
In and process the efficiency of these data.Specifically, in embodiment described herein, CPU (CPU) can to
Wherein store the Memory Controller transmission order that the memorizer (such as dynamic random access memory (DRAM)) of data couples.
Based on this order, Memory Controller can be retrieved data from DRAM and be loaded into one of vector register file in data
Or the data that reordered before in multiple vector registor.Then, Memory Controller can be according to reordering rearranged sequence
Data are loaded in one or more vector registors of vector register file.Can by during retrieving rather than
The data that reorder after data are loaded in vector register file are to realize various benefit.Such as, it is required to pass from CPU
The number of defeated signal can reduce.Additionally, load and the process time and thus waiting time of system can reduce.Also may be used
To realize additionally or alternatively benefit.
Various operations can be to be described as multiple points most helpful in the way of understanding theme required for protection successively
Vertical action or operation.But, the order of description should not be construed as to imply that these operations and necessarily depends on order.Special
Not, these operations can not be implemented with the order presented.Described operation can be with different from described embodiment
Order is implemented.Various additional operations can be implemented, and/or described operation can be omitted in an additional embodiment.
For the purpose of this disclosure, phrase " A and/or B " and " A or B " mean (A), (B) or (A and B).For the disclosure
Purpose, phrase " A, B and/or C " means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).
Description can use phrase " in one embodiment " or " in an embodiment ", and it is identical or not that it may each be finger
One or more with in embodiment.It addition, as about embodiment of the disclosure used term " comprise ", " including ", " tool
Have " etc. be synonym.
As it is used herein, term " circuit " may refer to following every, be following every part or under including
State every: perform the special IC (ASIC) of one or more software or firmware program, electronic circuit, processor (share,
Special or group) and/or memorizer (shared, special or group), combinational logic circuit and/or described by providing functional other
Appropriate hardware assembly.As it is used herein, " computer implemented method " may refer to by one or more processors, have
(it can include one or more the mobile device of the computer system of one or more processors, such as smart phone etc
Processor), panel computer, laptop computer, Set Top Box, any method of the execution such as game console.
Fig. 1 depicts the example of system 100, and system 100 can allow more efficient in vector register file of data
Gathering.In an embodiment, CPU 105, and specifically, the element of CPU 105, vector registor the most discussed below literary composition
Part 130, can couple with Memory Controller 110 via one or more buses.In an embodiment, Memory Controller 110
Can couple with DRAM 120 in addition.In embodiment described herein, DRAM 120 can be synchronous dram (SDRAM),
Double data rate (DDR) the DRAM(such as second filial generation (DDR2), the third generation (DDR3) or forth generation (DDR4) DRAM) or certain its
The DRAM of its type.In certain embodiments, Memory Controller 110 can be via DDR communication link 125 and DRAM 120 coupling
Close.
In an embodiment, Memory Controller 110 can couple with the vector register file 130 of CPU 105 in addition, to
Amount register file 130 can include multiple vector registor 135a, 135b and 135c.In certain embodiments, vector register
Device file 130 can be referred to as single-instruction multiple-data (SIMD) register file.Each vector registor can be configured to deposit
The part of the data that storage is retrieved from DRAM 120 by Memory Controller 110.In an embodiment, vector register file 130 can
Couple with multiple vector processing unit 140a, 140b and the 140c with CPU 105.Vector processing unit 140a, 140b and 140c
Can be configured to different from another process vector register file 130 in vector processing unit 140a, 140b or 140c
One or more vector registor 135a, 135b or 135c in another part of data process vector registor literary composition concurrently
The part of the data in one or more in vector registor 135a, 135b or 135c of part 130.Such as, Vector Processing list
Unit 140a can with vector processing unit 140b process vector registor 135b data parallel process vector registor 135a
Data.Although vector register file 130 only is depicted as having three vector registors 135a, 135b and 135c by Fig. 1, but
Being in other embodiments, vector register file 130 can have more or less of vector registor.Additionally, system 100
Can include than three the more or less of vector processing units of vector processing unit 140a, 140b and 140c described in Fig. 1.
Although some element is shown as element each other or with coupled to each other, but in other embodiments, one
Or multiple element can configure with SOC(system on a chip) (SoC) or system in package (SiP) and be in identical chips or encapsulation, or
Can be with separated from one another.Such as, in vector register file 130 and/or vector processing unit 140a, 140b and 140c
Or multiple can separate with CPU 105.Alternatively, one single chip can include CPU 105, Memory Controller 110, vector
One or more in register file 130 and vector processing unit 140a, 140b or 140c.
In certain embodiments, Memory Controller 110 can comprise one or more module or circuit, such as memorizer
Retrieve circuit 145, reorder circuit 150 and storage circuit 155.In an embodiment, memory search circuit 145 can be configured to
One or more parts of data are retrieved from DRAM 120.Reorder circuit 150, as discussed in detail further below, and can
To be configured to the data retrieved by memory search circuit 145 that reorder.Storage circuit 155 can be configured to rearranged sequence
Data are placed in vector register file 130.
In an embodiment, CPU 105 can be configured to Memory Controller 110 transmission instruction.Instruction, it can be
SIMD instruction, can include such as generating, for Memory Controller 110, the instruction that " ACTIVE " orders.In certain embodiments,
Instruction can be or include that " LOAD " or " MOV " from CPU 105 instructs, and it can include that desired data are at DRAM
The instruction of the position in 120.ACTIVE order can make Memory Controller 110 activate (opening) wherein can to store or retrieve number
According to DRAM 120 in memory location or " page ".In certain embodiments, ACTIVE order open position can wrap
Include the data of thousands of byte.If accessing subsequently in the range of the page opened to memorizer, only the subset of address can
The data being supplied in selection page can be needed.In an embodiment, ACTIVE order can also identify and wherein store data
The row address of DRAM 120.
After ACTIVE order, Memory Controller 110 can generate " READ " or " WRITE " order.Real at some
Executing in example, READ or WRITE command can generate in response to the same instructions generating ACTIVE order, and real at other
Executing in example, READ or WRITE command can generate in response to the separation command from CPU 105.In certain embodiments,
One or all in ACTIVE, READ or WRITE command can include the storage address of DRAM 120, such as DRAM 120
In the column address of position or row address.Specifically, the instruction from CPU 105 can include one or more memorizer ground
Location, it can be converted to the particular row in DRAM 120 and column address.This conversion can be completed also by Memory Controller 110
Can be exclusively used in and realize other purpose, such as be evenly distributed the access to DRAM 120.Owing to DRAM 120 can be organized
For 2D array, therefore the row address in ACTIVE, READ or WRITE command can select wherein to store desired data
The row of DRAM 120, and the column address of ACTIVE, READ or WRITE command can select to be accessed for the row of DRAM 120.
In certain embodiments, during row and column address can be latched at some DRAM.
CPU 105 can instruct to Memory Controller 110 transmission at the rear of several clock cycle.Alternatively, CPU
105 can instruct to Memory Controller 110 transmission, and Memory Controller 110 can be real after several clock cycle
Now instruct.Such as, in certain embodiments, Memory Controller 110 may according to the one of Memory Controller 110 or
Multiple parameter presets follow the trail of the number of the clock cycle between some order.In an embodiment, can be at tRCDCycle measures number
Mesh, tRCDCycle can correspond to Memory Controller 110 posted row address strobe (RAS) and issues row to Memory Controller 110
Time between address strobe (CAS).
In certain embodiments, the instruction from CPU can make Memory Controller 110 data be read by read command
Get in vector registor 135a, 135b or 135c one or more in.This reading of data can be by asserting with all
Part such as the order of the column address or the row address that wherein store the memory location of the DRAM 120 of data etc is corresponding
The pin of DRAM 120 completes.One or more pins of DRAM 120 can correspond to the column address of read command.Logical
Cross asserting of these pins, in " burst ", data can be delivered to Memory Controller 110 from DRAM 120, as following more
Add detailed description.
Specifically, DRAM 120 can have multiple pin, and by the plurality of pin, it can transmit or receive from depositing
The concrete signal of memory controller 110.The order received on concrete pin can make DRAM 120 implement concrete function, such as
Read data, as described above, or write data, as described below.
On the contrary, WRITE command can make Memory Controller 110 by data from vector registor 135a, 135b and 135c
It is written to the memory location of the DRAM 120 specified by WRITE command.
In certain embodiments, being stored in the data in DRAM 120 can be alphabetic data.Showing as alphabetic data
Example, data can be 64 byte longs and be organized in eight 8 byte chunks.One 8 byte chunk of 64 bytes can be claimed
Being the 0th chunk, the 2nd 8 byte chunk of 64 bytes can be referred to as the 1st chunk, by that analogy.Generally, alphabetic data is permissible
It is made up of chunk 0,1,2,3,4,5,6 and 7.
In certain embodiments, CPU 105 can include cache 115.As shown in fig. 1, in certain embodiments,
Cache 115 can couple with Memory Controller 110 and/or vector register file 130 and be between it.At some
In embodiment, cache 115 can also couple with one or more in vector processing unit 140a, 140b and 140c.?
In some embodiments, one or more in vector processing unit 140a, 140b and 140c and/or vector register file 130
Can be configured to access from the most slow before the data of DRAM 120 attempting to access by means of Memory Controller 110
Deposit the data of 115.
Specifically, many Modern microprocessor of such as CPU 105 etc can use cache to reduce system
Average latency.Cache 115 can include one or more layer, such as L1 layer, L2 layer, L3 layer etc..In an embodiment,
Can the size of cache line based on Memory Controller 110 to the access of the data in the DRAM 120 of system 100.Example
As, in certain embodiments, cache line size can be 64 bytes.In this embodiment, by 64 byte cache-lines
It is sent to vector register file 130 from DRAM 120 and may require that eight continuous 8 byte data chunks.
Scalar register and the most unshowned of scalar register file is used to leave in embodiment wherein,
As the vector register file 130 with the present embodiment is contrasted, may close it is desirable that, not as first in alphabetic data
Individual chunk (it can be referred to herein as the chunk through priorization) was imported into scalar register before other chunk
File so that the processor (such as CPU 105) being associated with scalar register can be from DRAM(such as DRAM 120) read
Operate in data immediately while taking the remainder of alphabetic data.There is provided the chunk through priorization possible to scalar register
Be close desired because scalar register may be only capable of single treatment individual data chunk, as with can be configured to each other
The such as vector of one or more vector processing unit 140a, 140b and 140c coupling of the chunk of processing sequence data concurrently
The vector register file of register file 130 etc is contrasted.In certain embodiments, read command can be configured to
It is at least partly based on the starting column address of read command and whether read command includes that outburst type is order or interweaves
Instruction access the chunk through priorization from DRAM 120, as explained in further detail below.
In embodiment of the disclosure, similar read command may be used for accessing the alphabetic data from DRAM 120.
But, in embodiment of the disclosure, read command can be also used for determining which data chunks is placed on vector registor
In which vector registor (vector registor 135a, 135b and 135c of such as vector register file 130) of file.May
Close it is desirable that, particular data chunk is placed in specific vector depositor so that given vector processing unit can process
This data chunks.Such as, in some embodiments, it may be possible to close it is desirable that, vector processing unit 140a processing sequence data
Second chunk and the 4th chunk of simultaneously vector processing unit 140b processing sequence data.Given vector processing unit is to data set
The process of block can be based on specific algorithm, the requirement of process or certain other requirement.
Specifically, in certain embodiments, vector operator can be referred to as SIMD order.In an embodiment, tool is utilized
Volume data chunk is filled vector registor 135a, 135b and 135c of vector register file 130 and can be used one or more
SIMD order and complete.Specifically, SIMD instruction may be used for confusing 32 of alphabetic data or 64 bit vector elements, the most all
If the vector register file of vector register file 130 or memory operand etc is as selector.
Fig. 2 depicts the example of the table of the chunk of the alphabetic data in vector register file that may be used for reordering.As
Already pointed out, CPU 105 can transmit read command to Memory Controller 110.Read command can include initial row
Address.Further additionally or alternatively, read command can include will being order from DRAM 120 sorted order data or interweaving
Instruction.In sequential bursts pattern, the chunk of alphabetic data can be accessed to increase address order, the volume when arriving ending
Rap around to the initial of block.On the contrary, interleaved burst pattern can use XOR (XOR) computing to come based on initial address sum counter value
Mark chunk.In certain embodiments, interleaved burst pattern can be simpler or the most more efficient, because XOR operation
More simply can realize in gate than " addition " computing that may be used for sequential bursts pattern.
As shown in Figure 2, based on starting column address and from CPU 105 receive instruction (the most discussed above
" LOAD " or " MOV " instruction in) outburst type instruction, Memory Controller 110 can with access order data, reorder order
Data, and then the data of rearranged sequence are stored in vector registor 135a, 135b and 135c of vector register file 130
In.Specifically, the memory search circuit 145 of Memory Controller 110 can access the ordinal number being stored in DRAM 120
According to.In read command to the columns and/or rows address of the data that the access of data can be based at least partially in DRAM 120
Instruction.
Then, Memory Controller 110, and the circuit 150, Ke Yichong that reorders of specially Memory Controller 110
The alphabetic data that sequence is retrieved from DRAM 120 by memory search circuit 145.Specifically, the chunk of alphabetic data can be root
Reorder according to the instruction of outburst type and the starting column address of read command.As example, it is assumed that alphabetic data is by by group
Be made into 8 each 8 bytes and be marked as chunk 0,1,2,3,4,5,6 and 7 order chunk 64 bytes composition.Show at this
In example, read command can have the starting column address of " 1,0,0 ".As indicated in Fig. 2, this starting column address may indicate that order
Data should be reordered as chunk 4,5,6,7,0,1,2 and 3.In other words, may indicate that should for the starting column address of " 1,0,0 "
One 32 byte of exchange sequence data and the 2nd 32 byte of alphabetic data.In this example, outburst type be order or
Instruction in the read command interweaved can not affect reorders.
Memory Controller 110 storage circuit 155 then can according to indicated by read command reorder will through weight
The data of sequence are stored in vector registor 135a, 135b and 135c of vector register file.Such as, continue above showing
Example, chunk 4 can be stored in vector registor 135a for vector processing unit 140a process, chunk 5 can be stored in
For vector processing unit 140b process in amount depositor 135b, chunk 6 can be stored in vector registor 135c to feed to
Amount processing unit 140c process, by that analogy.
In other embodiments, one or more additional interface and/or logic can be added to include beyond institute in Fig. 2
Other data arrangement of the sequence enumerated.Fig. 3 depicts the example that may indicate that the table using additional interface to reorder data.
Specifically, extra pin can be added to CPU 105 so that the extra bits of data can be transmitted together with read command
To Memory Controller 110.As shown in the embodiment in figure 3, extra pin can allow the alphabetic data of rearranged sequence
Up to eight additional alignment.
Fig. 4 depicts the instantiation procedure can implemented by Memory Controller 110 as described above.Initially, memorizer controls
Device 110 can be from CPU(such as CPU 105 at 400) receive instruction.Instruction can be read command the most discussed above.
Then, Memory Controller 110 can be from DRAM(such as DRAM 120 at 405) sorted order data.Specifically
Ground, the memory search circuit 145 of Memory Controller 110 can be from DRAM 120 sorted order data.
After DRAM sorted order data, Memory Controller 110, and specially Memory Controller 110
Reorder circuit 150, can be according to the instruction reorder alphabetic data from CPU 105 at 410.Such as, memorizer controls
Device 110 can be according to starting column address, the instruction of outburst type or in one or more additional interface or logic element (all Tathagata
Pin from CPU 105) go up the one or more data that reorder in the instruction received, as described above.
After the data that reorder, Memory Controller 110, and the storage circuit of specially Memory Controller 110
155, according to reordering, the Part I of alphabetic data can be placed at 415 the first non-sequential of vector register file
In position.Specifically, data chunks can be placed on the vector registor of vector register file by Memory Controller 110
In (the vector registor 135a of such as vector register file 130).Data chunks can be the first chunk of alphabetic data.Connect
, Memory Controller 110, and the storage circuit 155 of specially Memory Controller 110, can be according to rearrangement at 420
The Part II of alphabetic data is placed in the second non-sequential position of vector register file by sequence.Such as, memorizer controls
Second chunk of alphabetic data can be placed on vector registor (the such as vector registor of vector register file by device 110
The vector registor 135c of file 130) in.Then this process can terminate at 425.
It will be appreciated that chunk described above and vector registor only can be by Memory Controller for reordering
From DRAM(such as DRAM 120) alphabetic data retrieved and the data of rearranged sequence are stored in vector register file to
The example of the process in amount depositor (vector registor 135a, 135b and 135c of such as vector register file 130)." the
Being described in herein for distinguishing two different chunks of alphabetic data one and second ", and be not construed as describing
It is restricted to only the first two chunk of alphabetic data.Similarly, such as " first and second " that used herein in regard to vector registor
Description be intended that illustrative and nonrestrictive.
Although 64 bytes about data provide above example, but data rearrangement program process can be further extended
Bigger scope.Such as, although burst order is described as only including 8 chunks, but can use in other embodiments
The chunk of more or less number.Additionally, each chunk can include the data of more or less byte.In some embodiments
In, the such as DRAM of DRAM 120 etc can be included in the data in the magnitude of thousands of, and the chunk of alphabetic data and/
Or length can be augmented the data volume including increasing.Expansion can the process as described above amount of data that reorders
A kind of mode may is that the additional column address used in read command, or uses additional pin from CPU to Memory Controller
Transmission additional data, as the most as described in Figure 3.In other embodiments, data rearrangement program process can be extended to
" stride " of data, is wherein replaced in alphabetic data and includes that { 0,1,2,3,4,5,6,7}, alphabetic data can include continuous chunk
Discontinuous chunk { 0,2,4,6,8,10,12,14} or certain other the discontinuous increment of order.In certain embodiments, change
The additional logic that the amount of data becoming the column address being sent to Memory Controller or read command may require in DRAM with
Process additional command or data.Although additionally, procedure described above is been described by about vector register file 130, but
In certain embodiments, from DRAM sorted order data, the data that reorder and then supply data to the process of depositor can
For supplying data to scalar register, wherein beyond only through the concrete order of data chunks of data chunks of priorization
It is that conjunction is desired.
Fig. 5 diagram according to the Example Computing Device 500 of various embodiments, wherein can merge and to describe the most in the early time
The system of CPU 105, Memory Controller 110 and/or DRAM 120 etc.Calculating equipment 500 can include several assembly, one
Individual or multiple Attached Processors 504 and at least one communication chip 506.
In various embodiments, one or more processors 504 or CPU 105 each can include one or more place
Reason device core.In various embodiments, this at least one communication chip 506 can physically and electrically be coupled to these one or more process
Device 504 or CPU 105.In other implementation, communication chip 506 can be these one or more processors 504 or CPU
The part of 105.In various embodiments, calculating equipment 500 can include printed circuit board (PCB) (PCB) 502.These are implemented
Example, these one or more processors 504, CPU 105 and communication chip 506 can be disposed thereon.In alternative embodiments,
Various assemblies can couple in the case of not using PCB 502.
Depending on that it is applied, calculating equipment 500 can include physically and electrically being coupled to its of PCB 502
Its assembly.These other assemblies include but not limited to volatile memory (such as DRAM 120), such as ROM's 508 etc is non-
Volatile memory, I/O controller 514, digital signal processor (not shown), cipher processor (not shown), graphics process
Device 516, one or more antenna 518, display (not shown), touch-screen display 520, touch screen controller 522, battery
524, audio codec (not shown), Video Codec (not shown), global positioning system (GPS) equipment 528, compass
530, accelerometer (not shown), gyroscope (not shown), speaker 532, video camera 534 and mass-memory unit are (such as
Hard disk drive, solid-state drive, compact disk (CD), digital versatile disc (DVD)) (not shown) etc..In various embodiments
In, CPU 105 can be integrated in same die to form SOC(system on a chip) (SoC), as shown in fig. 1 with other assembly.In reality
Executing in example, both one or all in DRAM 120 and/or ROM 508 can be maybe to include that cross-point nonvolatile is deposited
Reservoir.
In various embodiments, calculating equipment 500 can include that resident lasting or nonvolatile memory, such as flash are deposited
Reservoir 512.In certain embodiments, one or more processors 504, CPU 105 and/or flash memory 512 can include
Storage programming instruction associated firmware (not shown), described programming instruction be configured in response to one or more processor 504,
CPU 105 or Memory Controller 110 perform programming instruction and calculating equipment 500 can be put into practice and describe above with respect to Fig. 4
The whole or selected aspect of block.In various embodiments, these aspects can additionally or alternatively use and this
Or the hardware that separates of multiple processor 504, CPU 105, Memory Controller 110 or flash memory 512 and realize.
Communication chip 506 can realize for transmitting data to calculating equipment 500 and transmitting data from calculating equipment 500
Wiredly and/or wirelessly communicate.Term " wireless " and derivative thereof may be used for description can be by using to be entered by non-solid medium
The modulated electromagnetic radiation of row transmits the circuit of data, equipment, system, method, technology, communication channel etc..This term does not implies that
Associate device does not comprise any wire, although they may not comprise in certain embodiments.Communication chip 506 can realize number
Any one in individual wireless standard or agreement, include but not limited to IEEE 802.20, General Packet Radio Service (GPRS),
Evolution-Data Optimized (Ev-DO), evolution high-speed packet access (HSPA+), evolution high-speed downlink packet access (HSDPA+),
Evolution High Speed Uplink Packet accesses (HSUPA+), global system for mobile communications (GSM), strengthens data rate GSM evolution
(EDGE), CDMA (CDMA), time division multiple acess (TDMA), Digital Enhanced Cordless telecommunications (DECT), bluetooth, its derivatives, with
And it is indicated as being 3G, 4G, 5G and higher other wireless protocols any.Calculating equipment 500 can include multiple communication chip
506.Such as, the first communication chip 506 can be exclusively used in the relatively short distance radio communication of such as Wi-Fi and bluetooth etc, and
Second communication chip 506 can be exclusively used in such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and other etc relatively
Distance radio communication.
In various implementations, calculating equipment 500 can be kneetop computer, net book, notebook computer, super
Basis, smart phone, calculating flat board, PDA(Personal Digital Assistant), super mobile PC, mobile phone, desk computer, server, beat
Print machine, scanner, monitor, Set Top Box, amusement control unit (such as game console), digital camera, portable music
Player or digital video recorder.In other implementation, calculating equipment 500 can be process data any other
Electronic equipment.
In an embodiment, the first example of the disclosure can include a kind of Memory Controller, including: retrieval circuit, join
It is set to be based at least partially on the instruction retrieval from CPU (CPU) include with the some of the first order sequence
Data；Reorder circuit, couples with retrieval circuit and is configured to be based at least partially on received instruction reorder number
According to making the plurality of part to be different from the second order sequence of the first order；And storage circuit, it is configured at least partly
The plurality of part is stored in corresponding multiple positions of vector register file by ground based on received instruction with the second order
In putting.
Example 2 can include the Memory Controller of example 1, and wherein the second order is based at least partially on the initial of instruction
Column address.
Example 3 can include the Memory Controller of example 1, and what wherein the second order was based at least partially in instruction dashes forward
Send out the instruction of type.
Example 4 can include the Memory Controller of example 3, wherein the instruction of outburst type be outburst type be that order is prominent
Send out type or the instruction of interleaved burst type.
Example 5 can include the Memory Controller of example 1, and wherein the second order is based at least partially on the pin of CPU
Set.
Example 6 can include the Memory Controller of any one in example 1-5, wherein Memory Controller be configured to deposit
Dynamic random access memory (DRAM) coupling of storage data.
Example 7 can include the Memory Controller of any one in example 1-5, and wherein data are 64 byte longs.
Example 8 can include the Memory Controller of example 7, and each part in wherein said some is 8 words
Joint is long.
Example 9 can include a kind of method, including: by Memory Controller and be based at least partially on from centre
The Part I of instruction retrieval alphabetic data that reason unit (CPU) receives and the Part II of alphabetic data, Part I and the
Two parts in alphabetic data close to each other；By Memory Controller, Part I is placed on vector register file
In first non-sequential position；And by Memory Controller, Part II is placed on the second non-suitable of vector register file
During tagmeme is put.
Example 10 can include the method for example 9, wherein Memory Controller be configured to be placed on Part I to
For the primary vector processing unit processes coupled with Memory Controller in first non-sequential position of amount register file；And
And Memory Controller be configured to be placed on Part II in the second non-sequential position of vector register file for
The secondary vector processing unit processes of Memory Controller coupling.
Example 11 can include the method for example 9, also includes being based at least partially in instruction by Memory Controller
Starting column address from multiple positions of vector register file select vector register file the first non-sequential position.
Example 12 can include the method for example 9, also includes by Memory Controller based on retrieval it being prominent according to order
Send out type or interleaved burst type is come from the first of multiple positions of vector register file selection vector register file non-
Ordinal position.
Example 13 can include the method for any one in example 9-12, and wherein alphabetic data is stored in dynamic randon access and deposits
In reservoir (DRAM).
Example 14 can include the method for any one in example 9-12, and wherein the Part I of alphabetic data is 8 bytes
Data.
Example 15 can include the method for example 14, and wherein alphabetic data is the data of 64 bytes.
Example 16 can include a kind of device, including: couple with Memory Controller and be configured to storage order data
Dynamic random access memory (DRAM)；The CPU (CPU) coupled with Memory Controller, wherein CPU is configured to
To Memory Controller transmission instruction, and wherein Memory Controller is configured to: by Memory Controller and at least portion
Point Part I of based on the instruction retrieval alphabetic data received from CPU in ground and the Part II of alphabetic data, Part I with
Part II in alphabetic data close to each other；And Part I is placed on the first non-sequential of vector register file
In position；And Part II is placed in the second non-sequential position of vector register file.
Example 17 can include the device of example 16, also includes the first processor and second coupled with Memory Controller
Processor；Wherein first processor is configured to process the Part I in the first non-sequential position；And wherein the second processor
It is configured to process the Part II in the second non-sequential position with first processor simultaneously.
Example 18 can include the device of example 16, and wherein the first of vector register file the non-sequential position is at least portion
Point ground is based on multiple regioselective from vector register file of starting column address in instruction.
Example 19 can include the device of example 16, and wherein the first of vector register file the non-sequential position is by memorizer
It is to retrieve Part I and second according to sequential bursts type or interleaved burst type that controller is based at least partially on instruction
Partly select from multiple positions of vector register file.
Example 20 can include the device of example 16, and wherein the first of vector register file the non-sequential position is at least portion
It is multiple regioselective that point pin of based on CPU in ground sets from vector register file.
Example 21 can include the device of any one in example 16-20, and wherein instruction is the Part I of alphabetic data, is
The data of 8 bytes.
Example 22 can include the device of example 21, and wherein alphabetic data is the data of 64 bytes.
Example 23 can include one or more computer-readable medium including instruction, and described instruction is configured to by depositing
Memory controller performs to make Memory Controller during instruction: be based at least partially on the finger received from CPU (CPU)
The Part I of sorted order data and the Part II of alphabetic data, Part I and Part II is made to lean in alphabetic data
It is bordering on each other；Part I is placed in the first non-sequential position of vector register file；And Part II is placed
In the second non-sequential position of vector register file.
Example 24 can include one or more computer-readable mediums of example 23, and wherein instruction is configured to make storage
Device controller: Part I is placed in the first non-sequential position of vector register file for Memory Controller coupling
The primary vector processing unit processes closed；And Part II is placed in the second non-sequential position of vector register file
For the secondary vector processing unit processes coupled with Memory Controller.
Example 25 can include one or more computer-readable mediums of example 23, and wherein instruction is configured to make storage
The starting column address that device controller is based at least partially in instruction selects vector to post from multiple positions of vector register file
First non-sequential position of register file.
Example 26 can include one or more computer-readable mediums of example 23, and wherein instruction is configured to make storage
Device controller is to come from multiple positions of vector register file according to sequential bursts type or interleaved burst type based on retrieval
Put the first non-sequential position selecting vector register file.
Example 27 can include the one or more computer-readable mediums of any one, wherein ordinal number in example 23-26
According to being stored in dynamic random access memory (DRAM).
Example 28 can include the one or more computer-readable mediums of any one, wherein ordinal number in example 23-26
According to Part I be the data of 8 bytes.
Example 29 can include one or more computer-readable mediums of example 28, and wherein alphabetic data is 64 bytes
Data.
Example 30 can include a kind of device, including: it is based at least partially on the finger received from CPU (CPU)
Make the Part I of sorted order data and the component of the Part II of alphabetic data, Part I and Part II at ordinal number
Close to each other according to；Part I is placed on the component in the first non-sequential position of vector register file；And will
Part II is placed on the component in the second non-sequential position of vector register file.
Example 31 can include the device of example 30, also includes: Part I is placed on the of vector register file
For the component of primary vector processing unit processes in one non-sequential position；And Part II is placed on vector registor literary composition
For the component of secondary vector processing unit processes in second non-sequential position of part.
Example 32 can include the device of example 30, also include the starting column address that is based at least partially in instruction to
Multiple positions of amount register file select the component of the first non-sequential position of vector register file.
Example 33 can include the device of example 30, also includes based on retrieval it being according to sequential bursts type or to interweave prominent
Send out the component that type selects the first non-sequential position of vector register file from multiple positions of vector register file.
Example 34 can include the device of any one in example 30-33, and wherein alphabetic data is stored in dynamic randon access
In memorizer (DRAM).
Example 35 can include the device of any one in example 30-33, and wherein the Part I of alphabetic data is 8 bytes
Data.
Example 36 can include the device of example 35, and wherein alphabetic data is the data of 64 bytes.
Although illustrating and describing some embodiment the most for purposes of illustration, but it is intended to cover
Any adaptation of embodiments described herein or modification.Therefore, embodiment described herein clearly it is intended that only by right
Require to limit.
In the case of the disclosure records " one " or " first " element or its equivalent, such disclosure includes one or many
Individual such element, its two or more such elements the most neither requiring nor excluding.It addition, be used for the sequence of identified element
Number designators (such as first, second or the 3rd) is used for distinguishing element, and do not indicate or imply the required of such element or
The number limited, they the most do not indicate ad-hoc location or the order of such element, the most specifically state.
Claims (22)
1. a Memory Controller, including:
Retrieval circuit, is configured to be based at least partially on the instruction retrieval from CPU (CPU) and includes with first suitable
The data of the some of sequence sequence；
Reorder circuit, couples and is configured to be based at least partially on received instruction reorder data make with retrieval circuit
Obtain the plurality of part to be different from the second order sequence of the first order；And
Storage circuit, is configured to be based at least partially on received instruction and the plurality of part is stored in the second order
In corresponding multiple positions of vector register file.
2. the Memory Controller of claim 1, wherein the second order is based at least partially on the starting column address of instruction.
3. the Memory Controller of claim 1, the wherein finger of the outburst type that the second order is based at least partially in instruction
Show.
4. the Memory Controller of claim 3, wherein the instruction of outburst type be outburst type be sequential bursts type or
The instruction of interleaved burst type.
5. the Memory Controller of claim 1, wherein the second order is based at least partially on the pin setting of CPU.
6. the Memory Controller any one of claim 1-5, wherein Memory Controller be configured to store the dynamic of data
State random access memory (DRAM) couples.
7. the Memory Controller any one of claim 1-5, wherein data are 64 byte longs.
8. the Memory Controller of claim 7, each part in wherein said some is 8 byte longs.
9. a method, including:
By Memory Controller and be based at least partially on the instruction retrieval ordinal number received from CPU (CPU)
According to Part I and the Part II of alphabetic data, Part I and Part II in alphabetic data close to each other；
By Memory Controller, Part I is placed in the first non-sequential position of vector register file；And
By Memory Controller, Part II is placed in the second non-sequential position of vector register file.
10. the method for claim 9, wherein Memory Controller is configured to Part I is placed on vector register file
The first non-sequential position in for the primary vector processing unit processes coupled with Memory Controller；And
Memory Controller be configured to be placed on Part II in the second non-sequential position of vector register file for
The secondary vector processing unit processes coupled with Memory Controller.
The method of 11. claim 9, also includes the starting column address being based at least partially in instruction by Memory Controller
The first non-sequential position of vector register file is selected from multiple positions of vector register file.
The method of 12. claim 9, also includes by Memory Controller based on retrieval it being according to sequential bursts type or friendship
Knit outburst type and select the first non-sequential position of vector register file from multiple positions of vector register file.
Method any one of 13. claim 9-12, wherein alphabetic data is stored in dynamic random access memory (DRAM)
In.
Method any one of 14. claim 9-12, wherein the Part I of alphabetic data is the data of 8 bytes.
The method of 15. claim 14, wherein alphabetic data is the data of 64 bytes.
16. 1 kinds of devices, including:
Couple and be configured to the dynamic random access memory (DRAM) of storage order data with Memory Controller；
The CPU (CPU) coupled with Memory Controller, wherein CPU is configured to refer to Memory Controller transmission
Order, and wherein Memory Controller is configured to:
By Memory Controller and be based at least partially on from CPU receive instruction retrieval alphabetic data Part I and
The Part II of alphabetic data, Part I and Part II in alphabetic data close to each other；And
Part I is placed in the first non-sequential position of vector register file；And
Part II is placed in the second non-sequential position of vector register file.
The device of 17. claim 16, also includes first processor and the second processor coupled with Memory Controller；
Wherein first processor is configured to process the Part I in the first non-sequential position；And
Wherein the second processor is configured to process the Part II in the second non-sequential position with first processor simultaneously.
The device of 18. claim 16, wherein the first of vector register file the non-sequential position is at least partially based on finger
Multiple regioselective from vector register file of starting column address in order.
The device of 19. claim 16, wherein the first of vector register file the non-sequential position is by Memory Controller at least
Be based in part on instruction be retrieve Part I and Part II according to sequential bursts type or interleaved burst type and to
Multiple positions of amount register file select.
The device of 20. claim 16, wherein the first of vector register file the non-sequential position is at least partially based on CPU
Pin set multiple regioselective from vector register file.
Device any one of 21. claim 16-20, wherein instruction is the Part I of alphabetic data, is the number of 8 bytes
According to.
The device of 22. claim 21, wherein alphabetic data is the data of 64 bytes.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2013/077878 WO2015099746A1 (en) | 2013-12-26 | 2013-12-26 | Data reorder during memory access |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105940381A true CN105940381A (en) | 2016-09-14 |
| CN105940381B CN105940381B (en) | 2019-11-15 |
Family
ID=53479408
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201380081205.0A Active CN105940381B (en) | 2013-12-26 | 2013-12-26 | Memory Controller and the method executed by Memory Controller |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US20160306566A1 (en) |
| EP (1) | EP3087489A4 (en) |
| JP (1) | JP6388654B2 (en) |
| KR (1) | KR101937544B1 (en) |
| CN (1) | CN105940381B (en) |
| WO (1) | WO2015099746A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112703489A (en) * | 2020-04-14 | 2021-04-23 | 深圳市大疆创新科技有限公司 | Controller, memory device access system, electronic apparatus, and data transmission method |
| CN112771490A (en) * | 2018-09-24 | 2021-05-07 | 美光科技公司 | Addressing in memory by Reading Identification (RID) numbers |
| CN112799599A (en) * | 2021-02-08 | 2021-05-14 | 清华大学 | Data storage method, computing core, chip and electronic equipment |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105183568B (en) * | 2015-08-19 | 2018-08-07 | 山东超越数控电子有限公司 | A kind of scsi command synchronization methods between storage dual controller |
| US10152237B2 (en) | 2016-05-05 | 2018-12-11 | Micron Technology, Inc. | Non-deterministic memory protocol |
| US10534540B2 (en) | 2016-06-06 | 2020-01-14 | Micron Technology, Inc. | Memory protocol |
| US10776118B2 (en) * | 2016-09-09 | 2020-09-15 | International Business Machines Corporation | Index based memory access using single instruction multiple data unit |
| US10585624B2 (en) * | 2016-12-01 | 2020-03-10 | Micron Technology, Inc. | Memory protocol |
| US20180217838A1 (en) * | 2017-02-01 | 2018-08-02 | Futurewei Technologies, Inc. | Ultra lean vector processor |
| US10380034B2 (en) * | 2017-07-14 | 2019-08-13 | International Business Machines Corporation | Cache return order optimization |
| US11226816B2 (en) * | 2020-02-12 | 2022-01-18 | Samsung Electronics Co., Ltd. | Systems and methods for data placement for in-memory-compute |
| US10942878B1 (en) * | 2020-03-26 | 2021-03-09 | Arm Limited | Chunking for burst read transactions |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1825479A (en) * | 2005-01-18 | 2006-08-30 | 因芬尼昂技术股份公司 | Improved DDR II dram data path |
| US20070038842A1 (en) * | 2003-03-27 | 2007-02-15 | Graham Kirsch | Data recording processor and method for use in an active memory device |
| CN101176076A (en) * | 2005-05-13 | 2008-05-07 | 英特尔公司 | Dma reordering for dca |
| US8250322B2 (en) * | 2008-12-12 | 2012-08-21 | Sunplus Technology Co., Ltd. | Command reordering based on command priority |
| CN103092785A (en) * | 2013-02-08 | 2013-05-08 | 豪威科技(上海)有限公司 | Double data rate (DDR) 2 synchronous dynamic random access memory (SDRAM) controller |
| CN103262058A (en) * | 2010-12-21 | 2013-08-21 | 英特尔公司 | Mechanism for conflict detection by using SIMD |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3594260B2 (en) * | 1995-05-11 | 2004-11-24 | 富士通株式会社 | Vector data processing device |
| US6163839A (en) * | 1998-09-30 | 2000-12-19 | Intel Corporation | Non-stalling circular counterflow pipeline processor with reorder buffer |
| US6487640B1 (en) * | 1999-01-19 | 2002-11-26 | International Business Machines Corporation | Memory access request reordering to reduce memory access latency |
| US20110087859A1 (en) * | 2002-02-04 | 2011-04-14 | Mimar Tibet | System cycle loading and storing of misaligned vector elements in a simd processor |
| US8200945B2 (en) * | 2003-11-07 | 2012-06-12 | International Business Machines Corporation | Vector unit in a processor enabled to replicate data on a first portion of a data bus to primary and secondary registers |
| US20070226469A1 (en) * | 2006-03-06 | 2007-09-27 | James Wilson | Permutable address processor and method |
| US7450588B2 (en) * | 2006-08-24 | 2008-11-11 | Intel Corporation | Storage network out of order packet reordering mechanism |
| JP2009223758A (en) * | 2008-03-18 | 2009-10-01 | Ricoh Co Ltd | Image processing apparatus |
| GB2470780B (en) * | 2009-06-05 | 2014-03-26 | Advanced Risc Mach Ltd | A data processing apparatus and method for performing a predetermined rearrangement operation |
| JP5658556B2 (en) | 2010-12-24 | 2015-01-28 | 富士通株式会社 | Memory control device and memory control method |
| US20130339649A1 (en) * | 2012-06-15 | 2013-12-19 | Intel Corporation | Single instruction multiple data (simd) reconfigurable vector register file and permutation unit |
-
2013
- 2013-12-26 US US15/038,031 patent/US20160306566A1/en not_active Abandoned
- 2013-12-26 CN CN201380081205.0A patent/CN105940381B/en active Active
- 2013-12-26 EP EP13900263.8A patent/EP3087489A4/en not_active Withdrawn
- 2013-12-26 JP JP2016529467A patent/JP6388654B2/en active Active
- 2013-12-26 KR KR1020167013898A patent/KR101937544B1/en active IP Right Grant
- 2013-12-26 WO PCT/US2013/077878 patent/WO2015099746A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070038842A1 (en) * | 2003-03-27 | 2007-02-15 | Graham Kirsch | Data recording processor and method for use in an active memory device |
| CN1825479A (en) * | 2005-01-18 | 2006-08-30 | 因芬尼昂技术股份公司 | Improved DDR II dram data path |
| CN101176076A (en) * | 2005-05-13 | 2008-05-07 | 英特尔公司 | Dma reordering for dca |
| US8250322B2 (en) * | 2008-12-12 | 2012-08-21 | Sunplus Technology Co., Ltd. | Command reordering based on command priority |
| CN103262058A (en) * | 2010-12-21 | 2013-08-21 | 英特尔公司 | Mechanism for conflict detection by using SIMD |
| CN103092785A (en) * | 2013-02-08 | 2013-05-08 | 豪威科技(上海)有限公司 | Double data rate (DDR) 2 synchronous dynamic random access memory (SDRAM) controller |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112771490A (en) * | 2018-09-24 | 2021-05-07 | 美光科技公司 | Addressing in memory by Reading Identification (RID) numbers |
| CN112703489A (en) * | 2020-04-14 | 2021-04-23 | 深圳市大疆创新科技有限公司 | Controller, memory device access system, electronic apparatus, and data transmission method |
| WO2021207919A1 (en) * | 2020-04-14 | 2021-10-21 | 深圳市大疆创新科技有限公司 | Controller, storage device access system, electronic device and data transmission method |
| CN112799599A (en) * | 2021-02-08 | 2021-05-14 | 清华大学 | Data storage method, computing core, chip and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| EP3087489A4 (en) | 2017-09-20 |
| EP3087489A1 (en) | 2016-11-02 |
| JP2016538636A (en) | 2016-12-08 |
| CN105940381B (en) | 2019-11-15 |
| JP6388654B2 (en) | 2018-09-12 |
| KR101937544B1 (en) | 2019-01-10 |
| US20160306566A1 (en) | 2016-10-20 |
| WO2015099746A1 (en) | 2015-07-02 |
| KR20160075728A (en) | 2016-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105940381A (en) | Data reorder during memory access | |
| CN103677665B (en) | Embedded multi-media card controls its host and the method for operating its system | |
| US11016678B2 (en) | Channel optimized storage modules | |
| CN105702277B (en) | Accumulator system and Memory Controller | |
| CN102640226B (en) | There is the storer of internal processor and the method for control store access | |
| JP6373559B2 (en) | MEMORY DEVICE AND MEMORY DEVICE OPERATION METHOD | |
| CN106997324A (en) | Non-volatile memory module, computing system and its operating method with it | |
| US11681632B2 (en) | Techniques for storing data and tags in different memory arrays | |
| CN105849669A (en) | Method and apparatus for DRAM spatial coalescing within a single channel | |
| CN110059032A (en) | Memory interface and Memory Controller with memory interface | |
| CN105917414A (en) | Managing redundancy information in a non-volatile memory | |
| JP2018152112A (en) | Memory device and method of operating the same | |
| CN108351836A (en) | With the multi-stage non-volatile caching selectively stored | |
| CN111694513A (en) | Memory device and method including a circular instruction memory queue | |
| CN104903878B (en) | Data storage in mobile device with embedded mass storage device | |
| CN103186351A (en) | High-performance ahci interface | |
| US10504568B2 (en) | Integrated circuit memory devices with customizable standard cell logic | |
| EP3964971A1 (en) | Memory device performing configurable mode setting and method of operating the same | |
| CN109754841A (en) | Memory device including parity error detection circuit | |
| CN108962328A (en) | Storage system including memory devices | |
| KR20100070595A (en) | Access structure between processor and a plurality of nand flash memories |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |