CN106528217A - FPGA (Field Programmable Gate Array) program loading system and method - Google Patents
FPGA (Field Programmable Gate Array) program loading system and method Download PDFInfo
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- CN106528217A CN106528217A CN201610946997.9A CN201610946997A CN106528217A CN 106528217 A CN106528217 A CN 106528217A CN 201610946997 A CN201610946997 A CN 201610946997A CN 106528217 A CN106528217 A CN 106528217A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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Abstract
The invention discloses an FPGA (Field Programmable Gate Array) program loading system and method, and belongs to the field of FPGAs. The system comprises an FPGA chip and an ARM (Advanced RISC Machine) chip, wherein the FPGA chip is connected with the ARM chip; a PS (Passive Serial) interface is configured between the FPGA chip and the ARM chip; the FPGA chip also comprises a dual-interface RAM (Random Access Memory) module; the FPGA chip comprises a first transmission module which is used for sending an instruction to the ARM chip in the program operation process by the FPGA chip; the ARM chip comprises a second transmission module; the second transmission module is connected with the dual-interface RAM module, and is used for reading an SOF (SRAM Object file) from the dual-interface RAM module after the instruction is received; the ARM chip also comprises a processing module which is used for loading the SOF into the FPGA chip through the PS interface; the FPGA chip also comprises an executing module which is used for executing the SOF and operating Bootloader program in the SOF; the second transmission module is also used for writing an ELF (Executable and Linkable Format) file into the dual-interface RAM module; and the executing module is also used for loading and operating the ELF file through the Bootloader program.
Description
Technical field
The present invention relates to FPGA (Field Programmable Gate Array, field programmable gate array) field, special
It is not related to a kind of FPGA programs loading system and method.
Background technology
The program run on fpga chip is divided into configurator, and ((SRAM Object File, static random-access are deposited SOF
Reservoir obj ect file)) and software program (ELF (Executable and Linkable Format, it is executable and lattice can be linked
Formula) file), in operation program, SOF is first loaded, reloads ELF files.The program loading of fpga chip is divided into 2 kinds of loading moulds
Formula：Load outside loading and piece in piece.
The outer loading mode of traditional piece is to treat the EPCS (Erasable that program code execution is stored in outside fpga chip
Programmable configurable serial, erasable programmable configuration serial ports) on chip, it is special by between the two
The program loading on fpga chip after electricity is realized with serial line interface, as EPCS chips can provide relatively large program storage sky
Between and program loading velocity faster, the program loading of major part fpga chip at present all adopts such loading mode.
But being limited in that of the outer loading mode of this traditional piece can only realize on fpga chip one of program after electricity
Secondary property loading.After the completion of program loading, if necessary to load new program to fpga chip, it is necessary to gone up to fpga chip again
Electricity, this limitation cannot meet some application systems for fpga chip operation program the repeated loading in the case of non-power-failure
Demand.
The content of the invention
In order to solve prior art when new program is loaded to fpga chip, the problem for needing to re-power is of the invention
Embodiment provides a kind of FPGA programs loading system and method.The technical scheme is as follows：
In a first aspect, embodiments providing a kind of field programmable gate array program loading system, the system
Including：
On-site programmable gate array FPGA chip and Advanced Reduced Instruction Set processor ARM chips, the fpga chip with
ARM chips connection, and be configured with PS configuration pattern PS between the fpga chip and the ARM chips and connect
Mouthful, the fpga chip also includes dual port random access memory RAM module；
The fpga chip includes the first transport module, for during the fpga chip operation program, to institute
State ARM chips and send instruction；
The ARM chips include the second transport module, and second transport module is connected with the dual port RAM module, use
In after the instruction is received, static RAM obj ect file SOF is read from the dual port RAM module；
The ARM chips also include processing module, for the SOF is loaded into the fpga chip by PS interfaces
In；
The fpga chip also includes performing module, for performing the SOF and running the loading of the guiding in SOF
Bootloader programs, the SOF include the Bootloader programs；
Second transport module, is additionally operable to can perform and can link the form ELF files write dual port RAM module
In；
The performing module, is additionally operable to by ELF files described in the Bootloader program loading operations.
In a kind of implementation of the embodiment of the present invention, first transport module is additionally operable to the reception server transmission
Part I SOF；
The fpga chip also include synthesis module, for by the Part I SOF be stored in the fpga chip
Internal Part II SOF is synthesized, and obtains the SOF.
In another kind of implementation of the embodiment of the present invention, the system also include being connected with the fpga chip with
Machine accesses memory RAM, and first transport module is additionally operable to arrive the ELF files storage in the dual port RAM module
In the RAM；
The performing module, for loading the ELF files in the RAM by the Bootloader programs.
In another kind of implementation of the embodiment of the present invention, the processing module is additionally operable to reading the SOF
Afterwards, ELF files to be loaded are determined, be stored with the ARM chips at least two ELF files.
In another kind of implementation of the embodiment of the present invention, the processing module, for according to the fpga chip
Instruction, determines ELF files to be loaded；Or, according to the number of times for reading SOF, determine ELF files to be loaded.
Second aspect, the embodiment of the present invention additionally provide a kind of field programmable gate array program loading method, described
Fpga chip is connected with the ARM chips, and is configured with PS interfaces between the fpga chip and the ARM chips, described
Fpga chip includes dual port RAM module, and methods described includes：
The fpga chip during operation program sends to the ARM chips and instructs, so that the ARM chips
SOF is read from the dual port RAM module, and the SOF is loaded in the fpga chip by PS interfaces；
Perform the SOF and run the Bootloader programs in SOF, the SOF includes the Bootloader programs；
By the Bootloader program loading operations ELF files, the ELF files are written to by the ARM chips
In the dual port RAM module.
In a kind of implementation of the embodiment of the present invention, methods described also includes：
The Part I SOF that the reception server sends；
The Part I SOF is synthesized with the Part II SOF being stored in inside the fpga chip, institute is obtained
State SOF.
In another kind of implementation of the embodiment of the present invention, the fpga chip is also connected with RAM, and methods described is also wrapped
Include：The ELF files in the dual port RAM module are stored in the RAM；
It is described by the Bootloader program loading operations ELF files, including：
The ELF files in the RAM are loaded by the Bootloader programs.
The third aspect, the embodiment of the present invention additionally provide a kind of field programmable gate array program loading method, described
Fpga chip is connected with the ARM chips, and is configured with PS interfaces between the fpga chip and the ARM chips, described
Fpga chip includes dual port RAM module, and methods described includes：
The instruction that the ARM chips are sent during receiving the fpga chip operation program；
SOF is read from the dual port RAM module；
The SOF is loaded in the fpga chip by PS interfaces, so that the fpga chip performs the SOF simultaneously
Bootloader programs in operation SOF, the SOF include the Bootloader programs；
ELF files are write in the dual port RAM module, so that the fpga chip is by the Bootloader programs
ELF files described in load operating.
Described in a kind of implementation of the embodiment of the present invention, method also includes：
After the SOF is read, ELF files to be loaded are determined, in the ARM chips, be stored with least two
ELF files.
The beneficial effect that technical scheme provided in an embodiment of the present invention is brought is：
By fpga chip is connected with ARM chips, during operation program, new program is run if desired,
Then fpga chip sends to ARM chips and instructs, after ARM chips receive the instruction, the SOF in reading dual port RAM module, and by
ARM chips are loaded in fpga chip by PS patterns (being realized using PS interfaces), and fpga chip performs institute after loading SOF
State SOF and run the Bootloader programs in SOF, twoport is written to by Bootloader program performing ARM chips then
ELF files in RAM module, complete new program loading operation；In said procedure loading procedure, need not re-power, it is full
Foot demands of some application systems for fpga chip operation program repeated loading in the case of non-power-failure；On the other hand, will
ELF files are stored in ARM chips, are realized, solve the problems, such as that fpga chip memory space is little.
Description of the drawings
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, below will be to making needed for embodiment description
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, can be obtaining other according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of structural representation of FPGA programs loading system provided in an embodiment of the present invention；
Fig. 2 is a kind of flow chart of FPGA program loading methods provided in an embodiment of the present invention；
Fig. 3 is the flow chart of another kind of FPGA program loading methods provided in an embodiment of the present invention；
Fig. 4 is the flow chart of another kind of FPGA program loading methods provided in an embodiment of the present invention.
Specific embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 is a kind of structural representation of FPGA programs loading system provided in an embodiment of the present invention, and referring to Fig. 1, this is
System includes：
Fpga chip 10 and ARM (Advanced Risc Machines, Advanced Reduced Instruction Set processor) chip 11,
Fpga chip 10 is connected with ARM chips 11, and is configured with PS (Passive between fpga chip 10 and ARM chips 11
Serial configuration mode, PS configuration pattern) interface, fpga chip 10 includes dual port RAM (Random
Access Memory, random access memory) module 100.
Fpga chip 10 also includes the first transport module 101, for during 10 operation program of fpga chip, to
ARM chips 11 send instruction.
ARM chips 11 include the second transport module 111, and the second transport module 111 is connected with dual port RAM module 100, is used for
Upon receipt of the instructions, SOF is read from dual port RAM module 100.
ARM chips 11 also include processing module 112, for SOF being loaded in fpga chip 10 by PS interfaces.
Fpga chip 10 also includes performing module 102, (guides and adds for performing SOF and running the Bootloader in SOF
Carry) program, SOF includes Bootloader programs.
Second transport module 111, is additionally operable to write ELF files in the dual port RAM module 100 of fpga chip 10.
Performing module 102, is additionally operable to by Bootloader program loading operation ELF files.
Wherein, fpga chip 10 can be connected by IO (Input Output, input and output) interface with ARM chips 11.
Wherein, PS interfaces are logic interfacing, by running correspondingly agreement reality in fpga chip 10 with ARM chips 11
It is existing.Specifically, PS interfaces are the interfaces for realizing data transfer using PS patterns.PS patterns are referred to by peripheral control unit (ARM cores
Piece) control fpga chip configuration process pattern.In this mode, ARM chips are written to SOF in fpga chip, and it is right to realize
The programming of FPGA, completes the loading of SOF.
Wherein, dual port RAM module 100 refers to the memorizer equipped with two sets of independent addresses, data and control lines, twoport
RAM module 100 allows two independent controllers (fpga chip and ARM chips) while asynchronously accessing.
The present invention, is run new by fpga chip is connected with ARM chips during operation program if desired
Program, then fpga chip to ARM chips send instruct, after ARM chips receive the instruction, read dual port RAM module in
SOF, and be loaded in fpga chip by PS patterns (being realized using PS interfaces) by ARM chips, fpga chip is in loading SOF
Afterwards, perform SOF and run the Bootloader programs in SOF, be then written to by Bootloader program performing ARM chips
ELF files in dual port RAM module, complete new program loading operation；In said procedure loading procedure, without the need for going up again
Electricity, meets some application systems for the demand of fpga chip operation program repeated loading in the case of non-power-failure；The opposing party
Face, ELF files are stored in ARM chips, are realized, solve the problems, such as that fpga chip memory space is little.
Alternatively, the first transport module 101, is additionally operable to the Part I SOF of the reception server transmission；Fpga chip 10 is also
Including synthesis module, for Part I SOF is synthesized with the Part II SOF being stored in inside fpga chip 10, obtain
To SOF.SOF after synthesis is stored in dual port RAM module 100.
In the implementation, server and local is respectively stored in by SOF is divided to for two parts, it is to avoid FPGA cores
When piece 10 or stolen server, the problem that SOF is stolen improves safety.
Wherein, the first transport module 101 can carry out SOF synthesis (when splitting into two parts with SOF using predetermined manner
Mode correspondence), for example, directly two parts are stitched together, or two parts are carried out into simple operation (such as XOR).
Certainly, in other embodiments, it is also possible to which SOF is stored entirely in fpga chip 10 or server.
Further, the system can also include the random access memory ram being connected with fpga chip 10, the first transmission
Module 101, the ELF files for being additionally operable to will be stored in dual port RAM module 100 are stored in RAM；Performing module 102, for leading to
The ELF files crossed in Bootloader programs loading RAM.
In the implementation, by the external RAM outside the fpga chip 10, ELF files are stored in RAM, is solved
10 internal storage space of fpga chip less problem.
In embodiments of the present invention, be stored with ARM chips 11 at least two ELF files, and fpga chip 10 is after the power-up
First ELF file of load operating, second ELF file carry out load operating when needed.Therefore, ARM chips 11 are being received
To after the instruction of the transmission of fpga chip 10, it is thus necessary to determine which ELF file is transferred to fpga chip 10.
Therefore, in the implementation, processing module 112 can be also used for, after SOF is read, determining to be loaded
ELF files, to control the dual port RAM module that ELF files to be loaded are write the second transport module 111 fpga chip 10
100。
Specifically, processing module 112, can be used for the instruction according to fpga chip 10, determine that ELF to be loaded is literary
Part；Or, according to the number of times for receiving SOF, determine ELF files to be loaded.
In the implementation, while two or more ELF file is stored in ARM chips 11, it is to avoid existing outer
Loading mode needs to EPCS chips to record the problem of new program code when new program is reloaded.
Wherein, the instruction of the transmission of fpga chip 10 can include the numbering of ELF files, for example, if the instruction is 0,
ELF files to be loaded are aforementioned first ELF file, if the instruction is 1, ELF files to be loaded are aforementioned second
Individual ELF files.
Or, the record of ARM chips 11 receives the number of times of SOF, according to the number of times for receiving SOF, determines to be loaded
ELF files.For example, if 11 first time of ARM chips receives SOF, ELF files to be loaded are aforementioned first ELF text
Part, if ARM chips receive SOF for 11 second, ELF files to be loaded are aforementioned second ELF file.
Fig. 2 is a kind of flow chart of FPGA program loading methods provided in an embodiment of the present invention, in the system provided by Fig. 1
Fpga chip perform, referring to Fig. 2, the method includes：
Step 201：Fpga chip during operation program sends to ARM chips and instructs, so that ARM chips are from double
SOF is read in mouth RAM module, and SOF is loaded in fpga chip by PS interfaces.
Step 202：Perform SOF and run the Bootloader programs in SOF, SOF includes Bootloader programs.
Step 203：By Bootloader program loading operation ELF files, ELF files are written to twoport by ARM chips
In RAM module.
The present invention, is run new by fpga chip is connected with ARM chips during operation program if desired
Program, then fpga chip to ARM chips send instruct, after ARM chips receive the instruction, read dual port RAM module in
SOF, and be loaded in fpga chip by PS patterns (being realized using PS interfaces) by ARM chips, fpga chip is in loading SOF
Afterwards, perform SOF and run the Bootloader programs in SOF, be then written to by Bootloader program performing ARM chips
ELF files in dual port RAM module, complete new program loading operation；In said procedure loading procedure, without the need for going up again
Electricity, meets some application systems for the demand of fpga chip operation program repeated loading in the case of non-power-failure；The opposing party
Face, ELF files are stored in ARM chips, are realized, solve the problems, such as that fpga chip memory space is little.
Fig. 3 is the flow chart of another kind of FPGA program loading methods provided in an embodiment of the present invention, the system provided by Fig. 1
In ARM chips perform, referring to Fig. 3, the method includes：
Step 301：The instruction that ARM chips are sent during receiving fpga chip operation program.
Step 302：SOF is read from dual port RAM module.
Step 303：SOF is loaded in fpga chip by PS interfaces, so that fpga chip performs SOF and runs SOF
In Bootloader programs, SOF includes Bootloader programs.
Step 304：ELF files are write in dual port RAM module, so that fpga chip is loaded by Bootloader programs
Operation ELF files.
The present invention, is run new by fpga chip is connected with ARM chips during operation program if desired
Program, then fpga chip to ARM chips send instruct, after ARM chips receive the instruction, read dual port RAM module in
SOF, and be loaded in fpga chip by PS patterns (being realized using PS interfaces) by ARM chips, fpga chip is in loading SOF
Afterwards, perform SOF and run the Bootloader programs in SOF, be then written to by Bootloader program performing ARM chips
ELF files in dual port RAM module, complete new program loading operation；In said procedure loading procedure, without the need for going up again
Electricity, meets some application systems for the demand of fpga chip operation program repeated loading in the case of non-power-failure；The opposing party
Face, ELF files are stored in ARM chips, are realized, solve the problems, such as that fpga chip memory space is little.
Fig. 4 is the flow chart of another kind of FPGA program loading methods provided in an embodiment of the present invention, the system provided by Fig. 1
In fpga chip and ARM chips perform, referring to Fig. 4, the method includes：
Step 401：ARM chips read SOF from dual port RAM module.
Further, the method can also include：
The Part I SOF that fpga chip the reception server sends；Fpga chip by Part I SOF be stored in FPGA
The Part II SOF of chip internal is synthesized, and obtains SOF.The SOF that synthesis is obtained is stored in dual port RAM module.
In the implementation, server and local is respectively stored in by SOF is divided to for two parts, it is to avoid FPGA cores
When piece or stolen server, the problem that SOF is stolen improves safety.
Wherein, Part I SOF and Part II SOF can be carried out SOF synthesis using predetermined manner and (be split into SOF
Mode correspondence during two parts), for example, directly two parts are stitched together, or two parts are carried out into simple operation (as different
Or).
Certainly, in other embodiments, it is also possible to during SOF is stored entirely in fpga chip or server.
In embodiments of the present invention, be stored with ARM chips at least two ELF files, and fpga chip is loaded after the power-up
First ELF file of operation, second ELF file carry out load operating when needed.Therefore, ARM chips are receiving FPGA
After the SOF of chip transmission, it is thus necessary to determine which ELF file is transferred to fpga chip.Therefore, the method can also include：
ARM chips determine ELF files to be loaded after SOF is read, and be stored with ARM chips at least two ELF
File.
Specifically, after SOF is received, ELF files to be loaded are determined, can be included：
Instruction of the ARM chips according to fpga chip, determines ELF files to be loaded；Or, ARM chips are according to reception
To the number of times of SOF, ELF files to be loaded are determined.
In the implementation, while two or more ELF file is stored in ARM chips, it is to avoid existing additional
Load pattern needs to EPCS chips to record the problem of new program code when new program is reloaded.
Wherein, the instruction of fpga chip can include the numbering of ELF files, for example, if the instruction is 0, to be loaded
ELF files be aforementioned first ELF file, if the instruction is 1, ELF files to be loaded are aforementioned second ELF text
Part.
Or, ARM chips record receives the number of times of SOF, according to the number of times for receiving SOF, determines ELF to be loaded
File.For example, if ARM chips receive SOF for the first time, ELF files to be loaded are aforementioned first ELF file, such as
Fruit ARM chips receive SOF for the second time, then ELF files to be loaded are aforementioned second ELF file.
As shown in figure 4, as step 401 is performed during program operation, therefore before step 401, should
Method also includes：Fpga chip loads SOF ' and ELF ' (namely program that fpga chip is currently running in step 401).
Further, for the efficiency of ARM chip subsequent transmission ELF files, ARM chips can be before step 401 first
Read ELF files.
Further, fpga chip can be instructed by sending to ARM chips, to notify that ARM chips perform new procedures
Loading.I.e. the method can include：Fpga chip during operation program sends to ARM chips and instructs.
Step 402：ARM chips are loaded into SOF in fpga chip by PS interfaces.
Step 403：Fpga chip performs SOF and runs the Bootloader programs in SOF, and SOF includes Bootloader
Program.
Step 404：ELF files are write in the dual port RAM module of fpga chip by ARM chips.
Further, after step 403, fpga chip sends notification instruction to ARM chips, notifies that ARM chip SOF hold
Row is finished, and makes ARM chips execution step 404.
Step 405：Fpga chip passes through Bootloader program loading operation ELF files.
In embodiments of the present invention, fpga chip can be to be connected with RAM, correspondingly, and the method can also include：FPGA
Chip stores the ELF files in dual port RAM module in RAM.
Now, step 405 can include：Fpga chip loads the ELF files in RAM by Bootloader programs.Tool
Body ground, ELF files are stored in RAM, the initial address of ELF files is obtained, during Bootloader program loading ELF documents,
Jump directly to the initial address and run ELF files.
In the implementation, by the external RAM outside fpga chip, ELF files are stored in RAM, is solved
The less problem of fpga chip internal storage space.
The present invention, is run new by fpga chip is connected with ARM chips during operation program if desired
Program, then fpga chip to ARM chips send instruct, after ARM chips receive the instruction, read dual port RAM module in
SOF, and be loaded in fpga chip by PS patterns (being realized using PS interfaces) by ARM chips, fpga chip is in loading SOF
Afterwards, perform SOF and run the Bootloader programs in SOF, be then written to by Bootloader program performing ARM chips
ELF files in dual port RAM module, complete new program loading operation；In said procedure loading procedure, without the need for going up again
Electricity, meets some application systems for the demand of fpga chip operation program repeated loading in the case of non-power-failure；The opposing party
Face, ELF files are stored in ARM chips, are realized, solve the problems, such as that fpga chip memory space is little.
The foregoing is only presently preferred embodiments of the present invention, not to limit the present invention, all spirit in the present invention and
Within principle, any modification, equivalent substitution and improvements made etc. should be included within the scope of the present invention.
Claims (10)
1. a kind of field programmable gate array program loading system, it is characterised in that the system includes：
On-site programmable gate array FPGA chip and Advanced Reduced Instruction Set processor ARM chips, the fpga chip with it is described
ARM chips connect, and are configured with PS configuration pattern PS interface, institute between the fpga chip and the ARM chips
Stating fpga chip includes dual port random access memory RAM module；
The fpga chip also includes the first transport module, for during the fpga chip operation program, to described
ARM chips send instruction；
The ARM chips include the second transport module, and second transport module is connected with the dual port RAM module, for
After receiving the instruction, static RAM obj ect file SOF is read from the dual port RAM module；
The ARM chips also include processing module, for the SOF being loaded in the fpga chip by PS interfaces；
The fpga chip also includes performing module, for performing the SOF and running the loading Bootloader of the guiding in SOF
Program, the SOF include the Bootloader programs；
Second transport module, is additionally operable to can perform and can link in the form ELF files write dual port RAM module；
The performing module, is additionally operable to by ELF files described in the Bootloader program loading operations.
2. system according to claim 1, it is characterised in that first transport module, is additionally operable to the reception server and sends out
The Part I SOF for sending；
The fpga chip also include synthesis module, for by the Part I SOF be stored in inside the fpga chip
Part II SOF synthesized, obtain the SOF.
3. system according to claim 1 and 2, it is characterised in that the system also includes being connected with the fpga chip
Random access memory ram, first transport module is additionally operable to deposit the ELF files in the dual port RAM module
Store up in the RAM；
The performing module, for loading the ELF files in the RAM by the Bootloader programs.
4. system according to claim 1 and 2, it is characterised in that the processing module, be additionally operable to read it is described
After SOF, ELF files to be loaded are determined, be stored with the ARM chips at least two ELF files.
5. system according to claim 4, it is characterised in that the processing module, for according to the fpga chip
Instruction, determines ELF files to be loaded；Or, according to the number of times for reading SOF, determine ELF files to be loaded.
6. a kind of field programmable gate array program loading method, it is characterised in that the fpga chip is connected with the ARM chips
Connect, and be configured with PS interfaces between the fpga chip and the ARM chips, the fpga chip includes dual port RAM module,
Methods described includes：
The fpga chip during operation program sends to the ARM chips and instructs, so that the ARM chips are from institute
SOF is read in stating dual port RAM module, and the SOF is loaded in the fpga chip by PS interfaces；
Perform the SOF and run the Bootloader programs in SOF, the SOF includes the Bootloader programs；
By the Bootloader program loading operations ELF files, the ELF files are written to described by the ARM chips
In dual port RAM module.
7. method according to claim 6, it is characterised in that methods described also includes：
The Part I SOF that the reception server sends；
The Part I SOF is synthesized with the Part II SOF being stored in inside the fpga chip, is obtained described
SOF。
8. the method according to claim 6 or 7, it is characterised in that the fpga chip is also connected with RAM, methods described
Also include：The ELF files in the dual port RAM module are stored in the RAM；
It is described by the Bootloader program loading operations ELF files, including：
The ELF files in the RAM are loaded by the Bootloader programs.
9. a kind of field programmable gate array program loading method, it is characterised in that the fpga chip is connected with the ARM chips
Connect, and be configured with PS interfaces between the fpga chip and the ARM chips, the fpga chip includes dual port RAM module,
Methods described includes：
The instruction that the ARM chips are sent during receiving the fpga chip operation program；
SOF is read from the dual port RAM module；
The SOF is loaded in the fpga chip by PS interfaces, so that the fpga chip performs the SOF and runs
Bootloader programs in SOF, the SOF include the Bootloader programs；
ELF files are write in the dual port RAM module, so that the fpga chip is loaded by the Bootloader programs
Run the ELF files.
10. method according to claim 9, it is characterised in that methods described also includes：
After the SOF is read, ELF files to be loaded are determined, at least two ELF that are stored with the ARM chips are literary
Part.
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| CN201610946997.9A CN106528217B (en) | 2016-10-26 | 2016-10-26 | on-site programmable gate array program loading system and method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN113190289A (en) * | 2021-05-18 | 2021-07-30 | 厦门紫光展锐科技有限公司 | FPGA version downloading method, device and equipment |
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| CN114489826A (en) * | 2020-11-09 | 2022-05-13 | 哲库科技(上海)有限公司 | Chip operation method and device, storage medium and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108920197A (en) * | 2018-06-29 | 2018-11-30 | 北京遥测技术研究所 | A kind of loaded circuit and loading method improving the serial passive loading speed of FPGA |
| CN108920197B (en) * | 2018-06-29 | 2021-09-03 | 北京遥测技术研究所 | Loading circuit and loading method for improving serial passive loading rate of FPGA (field programmable Gate array) |
| CN114489826A (en) * | 2020-11-09 | 2022-05-13 | 哲库科技(上海)有限公司 | Chip operation method and device, storage medium and electronic equipment |
| CN114489826B (en) * | 2020-11-09 | 2024-06-04 | 哲库科技(上海)有限公司 | Chip operation method and device, storage medium and electronic equipment |
| CN113190289A (en) * | 2021-05-18 | 2021-07-30 | 厦门紫光展锐科技有限公司 | FPGA version downloading method, device and equipment |
| CN113467610A (en) * | 2021-05-28 | 2021-10-01 | 北京脑陆科技有限公司 | Architecture method, device, terminal and medium of brain-computer interface BCI (brain computer interface) equipment |
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| CN106528217B (en) | 2019-12-06 |
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