CN1776663A - Method and device for designing register in process or - Google Patents
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- CN1776663A CN1776663A CN 200510125971 CN200510125971A CN1776663A CN 1776663 A CN1776663 A CN 1776663A CN 200510125971 CN200510125971 CN 200510125971 CN 200510125971 A CN200510125971 A CN 200510125971A CN 1776663 A CN1776663 A CN 1776663A
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Abstract
The method designs register by using cheap RAM units instead of logic gate circuit of using costly traditional resources of register. In order to solve the target for reading/writing multiple data of 'register' at same time the invention uses parallel operatable RAM modules with multiple ports to save multiple sets of content of register, i.e. to generate multiple sets of copy of 'register'. Number of copy of 'register' is determined by maximal number of register, in which data are needed read by all instructions from processor. In order to keep data consistency, data to be returned back to 'register' are written bake to all copies of 'register'. The arrangement includes sub unit of memory and interface, reading sub unit of management/control and interface, and writing sub unit of management/control and interface.
Description
Technical field
The present invention relates to the processor architecture field in the computer technology category, is method and the device that designs register (group) in processor specifically.
Background technology
A kind of novel Computer Architecture is invented, and the principal feature of the Computer Architecture that this kind is novel is: under the precondition that does not need Interrupt Process, can walk abreast and carry out multiprogramming concomitantly at synchronization in same processor.To call in same processor the computing machine that can carry out the architecture of multiprogramming at synchronization in the following text is the L architecture computer, adopts the processor of L computer organization to be called L structure treatment device.Yet the design of relevant register (group) has certain defective in relevant patent document.
Register (group) is a crucial ingredient of processor, not only provides a great convenience for the user works out its application software system, has also played critical effect for the processing speed that improves processor.
In the processor of traditional architectures,, only need design one cover register (group) to get final product owing to one program only arranged in commission at synchronization.Yet, synchronization can walk abreast with the processor of carrying out multiprogramming concomitantly in, be in the L structure treatment device, the design of register (group) just becomes the important problems of a system for restricting combination property.If it is shared for multiprogramming that one group of register (group) only is set, obviously can not bring into play the parallel advantage with concurrent execution of multiprogramming at synchronization.If the program that can walk abreast with concurrent execution for each road all is provided with one group of register (group), when the program road number with concurrent execution of can walking abreast is big, then the number of the register that need be provided with (group) also will be bigger, obviously be infeasible.Fruit is laid down hard and fast rule for another example, and the maximum permission of a processor walks abreast and the road number of the program of concurrent execution is N (N＞1) and N group register (group) is set, and can not bring into play the advantage of L structure treatment device equally well.
Summary of the invention
In view of this, the present invention proposes a kind of method that designs register (group) in L structure treatment device according to the characteristics of L structure treatment device.This method replaces expensive, traditional register logical gate circuit to design register (group) with more cheap Memory Storage Unit, so that L structure treatment device does not limit the maximum purpose that allows the road number of parallel and concurrent executive routine substantially.
One of main thought of the present invention is to use the storage unit of more cheap RAM resource to replace the logic gates of expensive register resources to design register (group).
Finish the function of register with the RAM resource, most importantly how to solve the problem that reads a plurality of ' register ' data simultaneously.But another main thought of the present invention is to adopt RAM module a plurality of parallel work-flows, multiport to preserve the content of many cover registers (group), promptly generate many cover ' register ' copies, reaching with this can be in the purpose of synchronization read/write a plurality of ' register ' data.
According in all instructions of processor simultaneously the needs maximum number that reads register data determine the number of generation ' register ' copy.If each RAM has a plurality of read ports, then take the circumstances into consideration to reduce the number of ' register ' copy.For example, when the maximum number that needs to read register data in all instructions of processor simultaneously equaled 2, an available dual-read port RAM realized.
In order to guarantee the consistance of data, the data that need write back ' register ' will be write back in all ' register ' copies simultaneously.If the maximum number that needs simultaneously to write back register data in all instructions of processor is greater than 1, then the number of the write port of each RAM is also greater than 1.
The information of transmitting between each functional part of L structure treatment device mainly is driven by program device PD.A driven by program device PD includes one program of driving and carries out needed all information, comprises the information of present instruction.Command information comprises that present instruction requires the information of the operation carried out; If this instruction need be carried out read register operation, then the information of this instruction also comprises the number of read register, the information such as storeroom of the content of registers of numbering and reading; If this instruction need be write register manipulation, then the information of this instruction also comprise the numbering of writing register, by the information such as storeroom of write data.The specific definition of relevant procedures driver please refer to the patent document of relevant L structure treatment device.
A kind of device that in processor, designs register, the main composition of its hardware components is at least:
● the sub-device of storer: this sub-device is made up of a plurality of independently RAM modules; The number of RAM module equals to ask simultaneously the maximum number of read register in all instructions of processor; Each RAM module has a read port and a write port; But read port and write port parallel work-flow; Each port all is made up of one group of data, address equisignal line; The degree of depth of each RAM module equals maximum program road number of parallel/concurrent execution and the product that the per pass program allows the maximum register number of use of allowing of processor; The width of each RAM module equals the maximum number of digits of register;
When the RAM module has a plurality of read port, the corresponding reduction of the number of RAM module; The maximum number of writing register when request simultaneously in all instructions of processor is greater than 1 the time, and the number that then requires each RAM module write port is also greater than 1;
● read to manage/control sub-device: mainly by one be used to receive request/transmissions finished the input/output end port of the PD of read register operation, N individual read address output end mouth, a N read data input port and accordingly management/steering logic formed; It mainly acts on:
A) receive the driven by program device PD that the request read register is operated;
B) obtain n (the individual numbering for the treatment of read register of n≤N) from the appointment of above-mentioned PD;
C) appointment from above-mentioned PD obtains the program Taoist monastic name;
D) a said n register number and program Taoist monastic name are combined into the address of reading of n RAM module;
E) address of reading with a said n RAM module sends to n corresponding RAM module;
F) read operation of a startup said n RAM module;
G) n the data of reading are write back in the unit of n appointment in advance among the PD;
H) the functional processor parts that the above-mentioned PD that finishes the read register operation is returned to certain prior appointment carry out next step processing;
● write and manage/control sub-device: mainly be used to receive request/transmission and finished the input/output end port of the PD that writes register manipulation, write address output port, write data output port and corresponding control logic and formed by one; It mainly acts on:
A) receive the driven by program device PD that register manipulation is write in request;
B) appointment from above-mentioned PD obtains the numbering of register to be written and data to be written;
C) appointment from above-mentioned PD obtains the program Taoist monastic name;
D) above-mentioned register number and program Taoist monastic name are combined into the write address of a RAM module;
E) write address with above-mentioned RAM module sends to corresponding RAM module;
F) write operation of the above-mentioned RAM module of startup;
G) finish the functional processor parts that the PD that writes register manipulation returns to certain prior appointment and carry out next step processing above-mentioned.
The described device that in processor, designs register, the PD input/output end port that sub-device was managed/controlled to the reading of this device links to each other with certain port of the driven by program device PD dispenser DU of L structure treatment device, finishes the operation of reading a plurality of content of registers simultaneously; When promptly the content of n register was read in the present instruction request that drives as certain PD, the driven by program device PD dispenser DU of L structure treatment device will send to this PD the PD input/output end port of reading to manage/control sub-device of this device; When the sub-device of management/control of reading of this device is finished ' register ' read operation, and after ' register ' content that will read is written to this PD, will be sent to the driven by program device PD dispenser DU of L structure treatment device by the PD that its PD input/output end port will be finished the read register operation; Afterwards, DU will be sent to this PD certain L structure treatment device functional part according to circumstances and carry out next step processing.
The described device that in processor, designs register, the input/output end port of writing management/sub-device of control of this device links to each other with another port of the driven by program device PD dispenser DU of L structure treatment device, finishes an operating result is write back to the function of specifying register; When promptly register manipulation was write in the present instruction request that drives as certain PD, the driven by program device PD dispenser DU of L structure treatment device will send to this PD the PD input/output end port of writing management/sub-device of control of this device; After the writing the sub-device of management/control and finish ' register ' write operation of this device, will will finish the driven by program device PD dispenser DU that the PD that writes register manipulation sends to L structure treatment device by its PD input/output end port; Afterwards, DU will be sent to this PD certain L structure treatment device functional part according to circumstances and carry out next step processing.
Some basic explanations under the technology of the present invention design.And, all should belong to protection scope of the present invention according to any equivalent transformation that technical though of the present invention is done.
Description of drawings
Fig. 1 is the principle structure block diagram of register (group) device.
Fig. 2 is the read operation workflow synoptic diagram of register (group) device.
Fig. 3 is the write operation workflow synoptic diagram of register (group) device.
Fig. 4 is a L structure treatment device principle structure block diagram.
Fig. 5 is the L structure treatment device principle structure block diagram that adopts register of the present invention (group) device.
Embodiment
Fig. 1 is the principle structure block diagram of register as herein described (group) device.If it is max_Prg_nu that the processor maximum allows the program road number of parallel/concurrent execution, the maximum register number that the per pass program allows to use is max_reg_nu, the maximum number of digits of each register is max_reg_bit, and asking the maximum number of read register in all instructions of processor simultaneously is that the maximum number that register is write in N, request simultaneously is 1.The main composition of register (group) device (hereinafter to be referred as RFdev):
1. the sub-device of storer: this sub-device is formed (is RFram hereinafter to be referred as the RAM module) by a plurality of independently RAM modules; The number of RFram equals N; Each RFram has a read port and a write port; But read port and write port parallel work-flow; Each port is all formed (in this article, other signal wire, selecting, energize etc. as clock, sheet all is omitted) by one group of data signal line and address signal line; The degree of depth of each RFram equals max_prg_nu*max_reg_nu; The width of each RFram equals max_reg_bit.
When each RFram has a plurality of read port, the corresponding reduction of the number of RFram; The maximum number of writing register when request simultaneously in all instructions of processor is greater than 1 the time, and the number that then requires each RFram write port is also greater than 1;
Read to manage/control sub-device: mainly by one be used to receive request/transmissions finished the input/output end port of the PD of read register operation, N individual read address output end mouth, a N read data input port and accordingly management/steering logic formed; Its major function is:
● receive the driven by program device PD of request read register operation;
● obtain n (the individual numbering for the treatment of read register of n≤N) from above-mentioned appointment;
● obtain the program Taoist monastic name from the appointment of above-mentioned PD;
● a said n register number and program Taoist monastic name are combined into the address of reading of n RFram;
● the address of reading of a said n RFram is sent to n corresponding RFram;
● start the read operation of a said n RFram;
● n the data of reading are write back in the unit of n appointment in advance among the PD;
● the functional processor parts that the above-mentioned PD that finishes the read register operation is returned to certain prior appointment carry out next step processing;
3. write and manage/control sub-device: mainly be used to receive request/transmission and finished the input/output end port of the PD that writes register manipulation, write address output port, write data output port and corresponding control logic and formed by one; Its major function is:
● the driven by program device PD of register manipulation is write in the request of reception;
● obtain the numbering of register to be written and data to be written from the appointment of above-mentioned PD;
● obtain the program Taoist monastic name from the appointment of above-mentioned PD;
● above-mentioned register number and program Taoist monastic name are combined into the write address of a RFram;
● the write address of above-mentioned RFram is sent to corresponding RFram;
● start the write operation of above-mentioned RFram;
● finish the functional processor parts that the PD that writes register manipulation returns to certain prior appointment and carry out next step processing above-mentioned.
Fig. 2 is the read operation workflow synoptic diagram of register as herein described (group) device.In fact the read operation workflow is exactly the workflow of reading sub-device of register (group) device, also is the operating process that sub-device reads a plurality of content of registers simultaneously of reading of register (group) device.Its main flow process is as follows:
Step 1:, change step 2 if the current PD of the sub-device of register read of L structure treatment device requires the read register operation; Otherwise, when the new PD of the next one arrives the sub-device of this register read, change step 1;
Step 2: (obtain the numbering of the required n that the reads register of this PD the individual discrete cell of n≤N) from certain n of the current PD of the sub-device of register read of L structure treatment device; If the present instruction that PD drives need be read the number of registers less than N, can set up control signal to control the read-only register that those need read; Also can start simultaneously and read N operation registers, just the content of those registers that need read is only exported or is only used in control;
Step 3: in the front of each register number and put the program Taoist monastic name of this road program, form the address of n RFram (RAM);
Step 4: n RFram (RAM) address according to step 2 draws, send to n RFram successively respectively and read address register, start the read operation of this n RFram simultaneously, to read n data simultaneously;
Step 5: will be written to by n the data that step 3 reads in certain n unit of current PD appointment; When arriving this register read device, changes the new PD of the next one step 1.
Fig. 3 is the write operation workflow synoptic diagram of register as herein described (group) device.In fact the write operation workflow is exactly the workflow of writing sub-device of register (group) device, also is that the sub-device of writing of register (group) device writes back to appointment operation registers flow process with an operating result.Its main flow process is as follows:
Step 1:, change step 2 if the current PD of the register write device of L structure treatment device requires to write register manipulation; Otherwise, when the new PD of the next one arrives this register and writes sub-device, change step 1;
Step 2: from the register of L structure treatment device is write certain discrete cell of current PD of sub-device, obtain the required data that write back of this PD;
Step 3: the numbering that from the register of L structure treatment device is write certain discrete cell of current PD of sub-device, obtains the required register that writes back of this PD;
Step 4: in the front of this register serial number and put the program Taoist monastic name of this road program, form the address of a RFram (RAM);
Step 5: will give all RFram (RAM) by the address assignment that writes back that data and step 3 obtain that writes back that step 1 obtains; Start the write operation of N RFram simultaneously, write back to the data that simultaneously needs write back in the address location of appointment of all RFram; When arriving this register write device, changes the new PD of the next one step 1.
Fig. 4 is a L structure treatment device principle structure block diagram.Also provided the annexation of L structure treatment device each parts of system in this kind embodiment among the figure: parts 1 to 6 are linked parts 7 by their input/defeated ports separately respectively.In the embodiment of the L structure treatment device that Fig. 4 gave, register (group) is not configured to the parts of example, in hardware, but is designed to an ingredient for driven by program device PD.The main drawback of this method is that the figure place of PD is long, the resource use amount is excessive.Annotate, in this article, owing to introduced register (group) part/device of example, in hardware, so the driven by program device PD that mentions does not in this article comprise register section.
Fig. 5 is the synoptic diagram that register of the present invention (group) device (RFdev) is connected with L structure treatment device.The PD input/output end port that sub-device was managed/controlled to the reading of RFdev links to each other with certain port of the driven by program device PD dispenser DU of L structure treatment device, finishes the operation of reading a plurality of content of registers simultaneously.The input/output end port of writing management/sub-device of control of RFdev links to each other with another port of the driven by program device PD dispenser DU of L structure treatment device, finishes an operating result is write back to the function of specifying register.
When the content of n register was read in the present instruction request of certain PD driving, the driven by program device PD dispenser DU of L structure treatment device will send to this PD the PD input/output end port of reading to manage/control sub-device of RFdev.When the sub-device of management/control of reading of RFdev is finished ' register ' read operation, and after ' register ' content that will read is written to this PD, will be sent to the driven by program device PD dispenser DU of L structure treatment device by the PD that its PD input/output end port will be finished the read register operation; Afterwards, DU will be sent to this PD certain L structure treatment device functional part according to circumstances and carry out next step processing.
When register manipulation was write in the present instruction request of certain PD driving, the driven by program device PD dispenser DU of L structure treatment device will send to this PD the PD input/output end port of writing management/sub-device of control of RFdev.After the writing the sub-device of management/control and finish ' register ' write operation of RFdev, will will finish the driven by program device PD dispenser DU that the PD that writes register manipulation sends to L structure treatment device by its PD input/output end port; Afterwards, DU will be sent to this PD certain L structure treatment device functional part according to circumstances and carry out next step processing.
In the embodiment shown in this figure, suppose that the maximum number that PD asks to write register simultaneously is 1.The maximum number of asking to write register simultaneously as PD greater than 1 the time, but then require each RFram to have the write port of a plurality of parallel work-flows to get final product.
Claims (8)
1, a kind of method that designs register in processor is characterized in that, replaces traditional register logical gate circuit to design register with ram memory cell; But adopt RAM module a plurality of parallel work-flows, multiport to preserve the content of many cover registers, promptly generate many cover ' register ' copies, reaching with this can be in the purpose of synchronization read/write a plurality of ' register ' data.
2, according to claim 1 in processor the method for design register, it is characterized in that, according in all instructions of processor simultaneously the needs maximum number that reads register data determine the number of generation ' register ' copy; If each RAM has a plurality of read ports, then take the circumstances into consideration to reduce the number of ' register ' copy; When the maximum number that needs to read register data in all instructions of processor simultaneously equaled 2, an available dual-read port RAM realized.
3, according to claim 1 and 2 in processor the method for design register, it is characterized in that in order to guarantee the consistance of data, the data that need write back ' register ' will be write back in all ' register ' copies simultaneously; If the maximum number that needs simultaneously to write back register data in all instructions of processor is greater than 1, then the number of the write port of each RAM is also greater than 1.
4, according to claim 1 or the 2 or 3 described methods that in processor, design register, it is characterized in that the groundwork flow process of its read operation is as follows:
Step 1: if the current PD of the sub-device of register read of L structure treatment device requires read register
Step 2 is changeed in operation; Otherwise, when the new PD of the next one arrives the sub-device of this register read, change step 1;
Step 2: (obtain the numbering of the required n that the reads register of this PD the individual discrete cell of n≤N) from certain n of the current PD of the sub-device of register read of L structure treatment device; If the present instruction that PD drives need be read the number of registers less than N, can set up control signal to control the read-only register that those need read; Also can start simultaneously and read N operation registers, just the content of those registers that need read is only exported or is only used in control;
Step 3: in the front of each register number and put the program Taoist monastic name of this road program, form the address of n RAM module;
Step 4: according to n the RAM module's address that step 2 draws, send to n RAM module successively respectively and read address register, start the read operation of this n RAM module simultaneously, to read n data simultaneously;
Step 5: will be written to by n the data that step 3 reads in certain n unit of current PD appointment; When arriving this register read device, changes the new PD of the next one step 1.
5, according to claim 1 or the 2 or 3 described methods that in processor, design register, it is characterized in that the groundwork flow process of its write operation is as follows:
Step 1:, change step 2 if the current PD of the register write device of L structure treatment device requires to write register manipulation; Otherwise arriving at the new PD of the next one changes when this register is write sub-device
Step 1;
Step 2: from the register of L structure treatment device is write certain discrete cell of current PD of sub-device, obtain the required data that write back of this PD;
Step 3: the numbering that from the register of L structure treatment device is write certain discrete cell of current PD of sub-device, obtains the required register that writes back of this PD;
Step 4: in the front of this register serial number and put the program Taoist monastic name of this road program, form the address of a RAM module;
Step 5: will give all RAM modules by the address assignment that writes back that data and step 3 obtain that writes back that step 1 obtains; Start the write operation of N RAM module simultaneously, write back to the data that simultaneously needs write back in the address location of appointment of all RAM modules; When arriving this register write device, changes the new PD of the next one step 1.
6, a kind of device that designs register in processor is characterized in that the main composition of its hardware components is at least:
● the sub-device of storer: this sub-device is made up of a plurality of independently RAM modules; The number of RAM module equals to ask simultaneously the maximum number of read register in all instructions of processor; Each RAM module has a read port and a write port; But read port and write port parallel work-flow; Each port all is made up of one group of data, address equisignal line; The degree of depth of each RAM module equals maximum program road number of parallel/concurrent execution and the product that the per pass program allows the maximum register number of use of allowing of processor; The width of each RAM module equals the maximum number of digits of register;
When the RAM module has a plurality of read port, the corresponding reduction of the number of RAM module; The maximum number of writing register when request simultaneously in all instructions of processor is greater than 1 the time, and the number that then requires each RAM module write port is also greater than 1;
● read to manage/control sub-device: mainly by one be used to receive request/transmissions finished the input/output end port of the PD of read register operation, N individual read address output end mouth, a N read data input port and accordingly management/steering logic formed; It mainly acts on:
A) receive the driven by program device PD that the request read register is operated;
B) obtain n (the individual numbering for the treatment of read register of n≤N) from the appointment of above-mentioned PD;
C) appointment from above-mentioned PD obtains the program Taoist monastic name;
D) a said n register number and program Taoist monastic name are combined into the address of reading of n RAM module;
E) address of reading with a said n RAM module sends to n corresponding RAM module;
F) read operation of a startup said n RAM module;
G) n the data of reading are write back in the unit of n appointment in advance among the PD;
H) the functional processor parts that the above-mentioned PD that finishes the read register operation is returned to certain prior appointment carry out next step processing;
● write and manage/control sub-device: mainly be used to receive request/transmission and finished the input/output end port of the PD that writes register manipulation, write address output port, write data output port and corresponding control logic and formed by one; It mainly acts on:
A) receive the driven by program device PD that register manipulation is write in request;
B) appointment from above-mentioned PD obtains the numbering of register to be written and data to be written;
C) appointment from above-mentioned PD obtains the program Taoist monastic name;
D) above-mentioned register number and program Taoist monastic name are combined into the write address of a RAM module;
E) write address with above-mentioned RAM module sends to corresponding RAM module;
F) write operation of the above-mentioned RAM module of startup;
G) finish the functional processor parts that the PD that writes register manipulation returns to certain prior appointment and carry out next step processing above-mentioned.
7, the device that in processor, designs register according to claim 6, it is characterized in that, the PD input/output end port that sub-device was managed/controlled to the reading of this device links to each other with certain port of the driven by program device PD dispenser DU of L structure treatment device, finishes the operation of reading a plurality of content of registers simultaneously; When promptly the content of n register was read in the present instruction request that drives as certain PD, the driven by program device PD dispenser DU of L structure treatment device will send to this PD the PD input/output end port of reading to manage/control sub-device of this device; When the sub-device of management/control of reading of this device is finished ' register ' read operation, and after ' register ' content that will read is written to this PD, will be sent to the driven by program device PD dispenser DU of L structure treatment device by the PD that its PD input/output end port will be finished the read register operation; Afterwards, DU will be sent to this PD certain L structure treatment device functional part according to circumstances and carry out next step processing.
8, the device that in processor, designs register according to claim 6, it is characterized in that, the input/output end port of writing management/sub-device of control of this device links to each other with another port of the driven by program device PD dispenser DU of L structure treatment device, finishes an operating result is write back to the function of specifying register; When promptly register manipulation was write in the present instruction request that drives as certain PD, the driven by program device PD dispenser DU of L structure treatment device will send to this PD the PD input/output end port of writing management/sub-device of control of this device; After the writing the sub-device of management/control and finish ' register ' write operation of this device, will will finish the driven by program device PD dispenser DU that the PD that writes register manipulation sends to L structure treatment device by its PD input/output end port; Afterwards, DU will be sent to this PD certain L structure treatment device functional part according to circumstances and carry out next step processing.
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| CN104834501A (en) * | 2015-04-20 | 2015-08-12 | 江苏汉斯特信息技术有限公司 | L structure processor-based register and register operation method |
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