CN1975693A - Command simulation analytic system with automatic driving function and realizing method thereof - Google Patents
Command simulation analytic system with automatic driving function and realizing method thereof Download PDFInfo
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Abstract
The invention is self-driven instruction emulation system and implementation. The system includes instruction logic controller to conduct instruction parsing, generate scripts serial information, etc; hardware simulation unit to emulate hardware mode and driving method; instruction pre-processor, to finish the instruction reading and decomposing before the instruction processing, and store the decomposed instruction into the pre-fetch queue for instruction control unit to use; instruction table, to store target instruction format, properties, driving method and other information. The implementation method includes: construct instruction pre-processor, set up the memory control mechanism in processor level, set up the processor working mode switching mechanism; construct corresponding virtual instruction set format and construct logical controller of instructions. The timing complexity of the instruction inquiry in the invention is reduced to O(1).
Description
[technical field]: the present invention relates to a kind of emulation resolution system, particularly a kind of command simulation resolution system and analytic method thereof with self-driven function.
[background technology]: in finishing Embedded System Design, soft, hardware effort is normally carried out synchronously.Therefore but before hardware system is not also finished, be starved of a virtual hardware environment and come the support software system works, in recent years the virtual emulation technology of hardware environment has been obtained fast development.The command simulation resolver that we finished belongs to the work of this category.
Simulation hardware simulation to embedded system, at first be will be to the simulation of given processor, and do not have ready-made technology to use to the simulation of application specific processor, to the simulation of processor importantly to the simulation of processor instruction set action, to the instruction set of the flush bonding processor of special use carry out efficiently, instruction flexibly resolves.
The instruction analytic model that present most of virtual machine uses is: at first binary instruction stream is decomposed into individual instructions, and then the order code of every instruction is carried out retrieval and inquisition, after finding the corresponding instruction functions of and instruction sign indicating number, submit to resolve and carry out.In order to improve the search efficiency of instruction, also can adopt the method for instruction list by the frequency of utilization ordering of instruction simultaneously, instruction placement order promptly commonly used more is forward more, to reduce query time.It is related normally to adopt the mode of mapping (Mapping) to set up between the order code in the instruction list and analytical function, and wherein overwhelming majority instruction and analytical function adopt one to one mapping mode to realize.
Mainly there is following problem in this instruction analytic model:
1) the time complexity height of query script
Can be in order to improve simulation efficiency by modes such as mathematical statistics and empirical analysis, with the preferential placement of usual instructions (for example move instruction, add instruction etc.).But the program mirror image changes the actual access frequency of instruction, and the frequency of utilization of instruction often has much relations with the specific tasks that program will be finished.From time complexity, the time complexity of query script is O (n).When fairly large instruction repertorie mirror image is carried out virtual emulation, the execution efficient of emulation platform will obviously descend.
2) the redundant degree height between analytical function
In order to resolve all instructions, need set up the analytical function array usually, finish different actions respectively.But owing to exist related between the instruction action, often exist redundant between analytical function, be mainly reflected in two aspects: the one, exist direct or indirect function call (Function call) between analytical function, the 2nd, there are a lot of repeated code segments (Code segment) between analytical function each other.Redundant will directly cause instructing the execution decrease in efficiency of resolving, maintenance cost rises.
Therefore in instruction resolving, exist two bottlenecks, the one, in the query script, the order code location efficiency is low, and influence is to the fast resolving of instruction stream; Another is, instruction is resolved and is almost completely depended on manual compiling instruction driving function, the dumb of analytic method causes the maintenance cost to instruction set significantly to rise, and be relatively poor to the extended capability of instruction set simultaneously, and it is also very high to finish the transplanting cost of associated instruction set.
[summary of the invention]: the objective of the invention is to solve the problems referred to above that exist in the existing traditional instruction analytic model, a kind of brand-new command simulation analytic method is provided, and set up the command simulation resolution system that has self-driven function in the emulation executive system based on this, so that improve the command simulation analyzing efficiency of virtual emulation device, improve the adaptability of system.
Command simulation resolution system with self-driven function provided by the invention comprises command logic controller, hardware virtual component, instruction pretreater and instruction list, wherein:
1) instruction pretreater: comprise respectively and the two-way communication unit that is connected of the control module of looking ahead, pretreatment unit and instruction prefetching; The control module of looking ahead of instruction pretreater passes through the bus control unit in its communication unit access hardware virtual component, and reads one section instruction stream in the storer analogue unit from the hardware virtual component; Control module look ahead then again by communication unit access instruction table, read the order format that has configured, and in pretreatment unit, carry out instruction stream and decompose; Instruction stream after the decomposition leaves in the instruction prefetching by the control module of looking ahead, as the input information of command logic controller;
2) command logic controller: comprise respectively and two-way digital control unit that is connected of communication unit and logic control element, and script resolution unit and script semantical definition unit; The command logic controller obtains to resolve by the script resolution unit in the command logic controller through pretreated command information from the instruction prefetching of instruction pretreater by its communication unit; In script resolving, need continuous communication unit to obtain required instruction description information by instruction list; Calculating process in the instruction need be finished by digital control unit and logic control element; Instruction action after the parsing is submitted to away by its communication unit, is delivered to and does further processing in the hardware virtual component;
3) hardware virtual component: comprise bus control unit, hardware effort mode definition unit, and distinguish storer analogue unit, register analogue unit, the storehouse analogue unit of two-way connection with it; Bus control unit transmits the instruction that receives the pretreater from instruction, finishes simulated operation to storer, register, storehouse according to command content; For analog hardware working method exactly, adopt bus control unit to carry out uniform dispatching to the visit of each nextport hardware component NextPort, and the user program that the analog simulation result feeds back to the upper strata is responsible for finishing simulation work to hardware pattern and type of drive;
4) instruction list: comprise interconnective instruction set definition unit and instruction set memory block, and the communication unit of the two-way connection in and instruction collection memory block; Instruction list is mainly used in the descriptor of holding instruction, and comprises form, instruction attributes, the type of drive of instruction, and instruction list is the systematicness file of instruction parsing operation, and different target machine systems will have different instruction list contents.
A kind of implementation method with command simulation resolution system of self-driven function, this method may further comprise the steps:
(1) makes up the instruction pretreater: finish reading and disintegration before the instruction process by the instruction pretreater; Wherein, have access to the bus control unit of hardware virtual component, the assigned address reading command stream from the storer analogue unit by communication unit, the control module of looking ahead; Or, therefrom read the order format of target machine by the control module access instruction table of looking ahead; The information that obtains is finished instruction stream in pretreatment unit decompose; Instruction stream after decomposing is done simple parsing, leave in the instruction prefetching by the control module of looking ahead, for the command simulation resolution system provides input;
(2) set up the memory management mechanism of processor level: be not subjected to the restriction of data storage method for making the command simulation resolution system, palpus design memory analogue unit in the virtual hardware simulation component, this unit is converted to storage format on the target machine according to configuration information with multibyte data when loading bytecode;
(3) make up the processor operating mode handover mechanism: the hardware virtual component of promptly setting up target machine; In order to increase system flexibility, in these parts, need to set up the processor operating mode handover mechanism; Be system is supported simultaneously based on register with based on two kinds of mode of operations of storehouse, need in hardware is virtual, simulate two kinds of mode of operations respectively, by concluding the characteristic of two kinds of processor operating modes, the descriptive language of definition processor (Processor Definition Language) is also supplied with other module by the bus control unit in the hardware virtual component and is used;
(4) make up corresponding fictitious order collection form: promptly behind the virtual component of having finished target machine hardware, set up instruction table description based on this, the effect of instruction table description is to realize the unified of different instruction table described by the instruction set definition rule, when the instruction strip number of order set greater than 2
8The time, in guaranteed performance, do not take too much index stores structure by setting up the Hash index structure;
(5) make up the command logic controller: promptly instruct the feature field of storing in instruction list to be the basis that the script sequence generates, belong to the instruction down of same instruction system, its script sequence adopts same template generation; Script template has been described the key operations directly related with hardware driving, the bus, and the operation rule that comprise read-write rule, addressing mode, data source, the use of operand, comprise script semantical definition unit and script resolution unit in the command logic controller, substep is realized the logic control of instruction.
Advantage of the present invention and effect:
Effect of the present invention be from finish the instruction analysis feature, this instruction resolver has been eliminated the bottleneck problem in the traditional instruction resolving, its advantage is:
The first, the time complexity of order code query script is reduced to O (1);
The second, solved the strong contradiction of property associated with each other between analytical function;
Three, the dirigibility of script mode makes the maintenance to order set become very easy;
Four, provide safer access mechanism, as to the unified visit of order set, script authentication etc.In fact, security mechanism not only is embodied in the instruction interpretive model, will design the normal operation that a cover complete safe mechanism guarantees simulation system in analogue system.
From the structural design angle, new instruction parser has proposed the tabledriven model of instruction.Set up good media for soft, hardware development personnel link up, instruction list is to realize the self-driven kernel data structure of instruction resolution system.Based on the drive pattern of instruction list, make the execution flow process of system more clear.From realizing functional perspective, new instruction interpretive model has advantages such as easy realization, easy care, easy revision, easy expansion.
[description of drawings]:
Fig. 1 is an instruction resolution system structural representation of the present invention;
Fig. 2 is the design level synoptic diagram of instruction resolution system of the present invention;
Fig. 3 is the inner workings synoptic diagram of simulation hardware of the present invention;
Fig. 4 is a kind of the realization based on the self-driven instruction analytic model synoptic diagram of instruction list of the present invention.
[embodiment]:
Embodiment 1:
Resolution system
Command simulation resolution system with self-driven function provided by the invention comprises command logic controller, hardware virtual component, instruction list and instruction pretreater.Native system can be finished the emulation of multiple instruction set and resolve, and can adapt to the change of multiple processor internal mechanism, give security for the virtual operation of target machine code, and be a core instrument in the Embedded System Design.
Wherein: (referring to Fig. 1)
1) instruction pretreater: comprise respectively and the two-way communication unit that is connected of the control module of looking ahead, pretreatment unit and instruction prefetching; The control module of looking ahead of instruction pretreater passes through the bus control unit in its communication unit access hardware virtual component, and reads one section instruction stream in the storer analogue unit from the hardware virtual component; Control module look ahead then again by communication unit access instruction table, read the order format that has configured, and in pretreatment unit, carry out instruction stream and decompose; Instruction stream after the decomposition leaves in the instruction prefetching by the control module of looking ahead, as the input information of command logic controller;
2) command logic controller: comprise respectively and two-way digital control unit that is connected of communication unit and logic control element, and script resolution unit and script semantical definition unit; The command logic controller obtains to resolve by the script resolution unit in the command logic controller through pretreated command information from the instruction prefetching of instruction pretreater by its communication unit; In script resolving, need continuous communication unit to obtain required instruction description information by instruction list; Calculating process in the instruction need be finished by digital control unit and logic control element; Instruction action after the parsing is submitted to away by its communication unit, is delivered to and does further processing in the hardware virtual component;
3) hardware virtual component: comprise bus control unit, hardware effort mode definition unit, and distinguish storer analogue unit, register analogue unit, the storehouse analogue unit of two-way connection with it; Bus control unit transmits the instruction that receives the pretreater from instruction, finishes simulated operation to storer, register, storehouse according to command content; For analog hardware working method exactly, adopt bus control unit to carry out uniform dispatching to the visit of each nextport hardware component NextPort, and the user program that the analog simulation result feeds back to the upper strata is responsible for finishing simulation work to hardware pattern and type of drive;
4) instruction list: comprise interconnective instruction set definition unit and instruction set memory block, and the communication unit of the two-way connection in and instruction collection memory block; Instruction list is mainly used in the descriptor of holding instruction, and comprises form, instruction attributes, the type of drive of instruction, and instruction list is the systematicness file of instruction parsing operation, and different target machine systems will have different instruction list contents.
In native system, divide three phases to finish to the parsing of instruction stream, i.e. system initialization, instruction resolved and command simulation.Resolving to individual instructions can directly be finished by four parts cooperations that provide among Fig. 1, wherein instructs preprocessing process and instruction resolving can realize concurrent working.Processing procedure and information flow to instruction in the system are described below:
When system moves, at first carry out system initialization, mainly finish at initial phase the initial configuration and the instruction process rule of hardware virtual component, instruction list and command logic controller are loaded; The working method, the bus structure that have comprised target processor after the initialization in the hardware virtual component, and the working method and the structure of storer, register, storehouse; Comprise the description such as form, instruction attributes, type of drive of target machine instruction set in the instruction list; Comprise the work script of universal command, the contents such as work script of custom instruction in the command logic controller.
The instruction pretreater was started working after system initialization was finished, it is by the bus control unit in the communication unit access hardware virtual component of the control module of looking ahead, from the storer analogue unit, read one section instruction stream, and then by access instruction table reading command form, and instruction stream is decomposed by pretreatment unit, instruction after the decomposition is left in the instruction prefetching by the control module of looking ahead, and uses for the command logic controller.
The command logic controller obtains to resolve by the script resolution unit through pretreated command information from the instruction pretreater; Script in resolving the required command information communication unit by instruction list obtain.The calculating process of instruction is finished by digital control unit and logic control element; Instruction after parsing action is submitted in the bus control unit of hardware virtual component by communication unit, and bus control unit can drive other processing units in the hardware virtual component and realize simulation operations to hardware such as storer, register, storehouses.
In the hardware virtual component,, adopt bus control unit to carry out uniform dispatching to the visit of each nextport hardware component NextPort, and the analog simulation result is fed back to the user program on upper strata for analog hardware working method exactly.Adopt the action of control class by the control bus scheduling in realization, the action of read-write class is realized by the method for data bus scheduling.
At system constructing and in implementing, groundwork is to realize hardware-related part and instruct parsing and emulation to carry out driving mechanism being encapsulated in the complete system (as shown in Figure 1).Be the self-driven process that realizes that instruction is resolved, inside of the present invention comprises one from controlling mechanism, and its assistance system is finished scheduling and operation.During instruction of every execution, system reads a command unit to be resolved from the instruction pretreater, resolves and execution result to the upper strata output order when the parsing of finishing instruction and after handling, and then prepares to begin the execution of next bar instruction.
For improving the efficient that instruction is read, we shall carry out preliminary processing to instruction stream before will instructing pretreater to be placed on the instruction stream submission.Pretreated meaning is: on the one hand, adopt the thought of instruction pipelining, make instruction look ahead and processing procedure can parallel processing; On the other hand, the part action that instruction semantic is resolved consigns to pretreatment unit and finishes, like this can the balance instruction read and the instruction process operation between the time mismatch problem, further improve the efficient of Radar System Simulation Parallel.This process has provided explanation in Fig. 3." the virtual machine controller " that marks among the figure is the upper strata parts that are associated with native system, native system has the input and output connectivity port with it, in the transmission that can walk abreast of manipulation internal instruction analysis request and instruction prefetch request, and order also can independently be finished in system.
In the design of technical solution of the present invention, we are divided three classes the usual instructions in the embedded system:
1) computing type instruction:, account for six to seventy percent to calculate, to be transmitted as the instruction of purpose.For example arithmetic instruction, move instruction, test instruction, or the like.The resolving of computing type instruction roughly comprises value, computing, the value of writing several steps.
2) jump class instruction: to judge that shifting is the instruction of purpose, accounts for one to twenty percent.For example conditional transfer, declare zero branch, or the like.The resolving of redirect type instruction roughly comprises value, generates decision condition, result of determination several steps.
3) other instructions:, account for to twenty percent with the closely-related instruction of par-ticular processor.For example Interrupt Process, stack instruction, combined command, or the like.
The basic script maneuver library of design in system, the most regular instructions in the system can be used an incompatible realization of associated script action group in the storehouse.Basic script action in the script storehouse comprises:
1) read: sampling process, from emulates hardware devices, to read, these emulators may be storer, register or external unit;
2) calculate: calculating process, with the data that read according to the instruction mode computing of agreement in advance;
3) write: the value of writing process writes back to the result in the emulates hardware devices;
4) configuration: the configuration specified register may be flag register, control register etc.;
5) judge: only be used for the instruction of redirect type, generate decision condition and result of determination.
According to these features of instruction, the present invention proposes a kind of new command simulation resolution system, promptly finishes system design according to " based on the self-driven analytic model of the instruction of instruction list " (Instruction table based auto-drive parse model).
In this instruction resolution system, except that the distinctive attribute of order set, the overwhelming majority can define by the mode of adjusting configuration information the description of instruction set.When the mode of instruction by script action dispose finish after, promptly can realize the parsing process certainly of dynamic mode.Native system can solve the bottleneck problem in the traditional instruction parsing, significantly promotes the realization performance that instruction is resolved.
Embodiment 2
The implementation method of resolution system:
When realizing the self-driven resolution system of command simulation, should adopt layered architecture to finish design, system can be divided into three aspects, promptly resolves Drive Layer, order set layer and hardware abstraction layer, shown in the right side among Fig. 2.
In hardware abstraction layer, mainly comprise organize content, as the management of memory mode, the management of processor execution pattern at target machine hardware; This one deck can play the effect that simulation hardware and particular hardware are separated, for system lays good basis to adapt to different hardware execution environments.Include functions such as order set definition, script semantical definition, instruction list definition in the order set layer, they have provided and instruction description rule, relevant control and the descriptive information of instruction executing rule.Comprised functions such as script definition, script drivings, script management resolving Drive Layer, these functions have constituted the logic control mode and rule during instruction is resolved, and are the entities of instruction parsing, ordering calculation.
Can realize realizing that according to different user programs the instruction parsing of the working method of storage mode, different processor to different instruction collection, different processor moves with virtual emulation on a cover virtual emulation operation platform according to the design proposal that provides among the present invention.Left part is represented among the structure of this treatment mechanism such as Fig. 2.
The realization of technical solution of the present invention, specifically finish following design procedure:
1. make up the instruction pretreater; The function of instruction pretreater is at first instruction to be read and operation splitting before instruction process.In the instruction pretreater, can have access to the bus control unit of hardware virtual component by communication unit, the control module of looking ahead; Can also from the assigned address the storer analogue unit, reading command flow; Simultaneously can also therefrom read the order format of target machine by the control module access instruction table of looking ahead; The information that obtains is finished instruction stream in pretreatment unit decompose; Instruction stream after decomposing is done simple parsing, leave in the instruction prefetching by the control module of looking ahead, for the command simulation resolution system provides input, as shown in Figure 1.
2. set up the memory management mechanism of processor level; Because the multibyte data value has two kinds of location mode: Big-endian (the big ending of translations, or descending) mode and Little-endian (the little ending of translations, or ascending order) mode usually in internal memory.The storage mode of multibyte data depends on employed hardware platform.What for example, 32 bit processor families of Intel Company used all is the Little-endian storage mode.Big-endian is then selected for use by some flush bonding processors, and in addition, procotols such as TCP/IP also require transmission information must meet the Big-endian form.
For making analogue system not be subjected to the restriction of data storage method, must the design memory analogue unit in the virtual hardware simulation component.This module realizes multibyte data is converted to storage format on the target machine according to the configuration information of target machine when loading bytecode.
3. make up the processor operating mode handover mechanism; CPU can be divided into usually based on register with based on two kinds of mode of operations of storehouse.Based on the CPU of register,, 8 32 bit registers that are used for finishing fundamental operation are arranged as the Pentium chip of Intel Company.Based on the CPU of storehouse,, storehouse on two sheets that are used for finishing fundamental operation is arranged as the RTX 32P chip of Harris semiconductor company.Two kinds of processor operating modes respectively have characteristics, and basic characteristics are as described in Table 1.
Table 1, based on register with based on the CPU mode of operation of storehouse
| Processor based on storehouse | Processor based on register | |
| Implementation | Memory cost is less | More transparent, be easy to debugging |
| Function call | Comparatively fast | Need do a lot of odd words, slower |
| Context switches | Comparatively fast | Need to consume a large amount of internal memories, slower |
| Basic operation (conventional computing) | Slower | Comparatively fast (overall performance is better) |
For making the command simulation resolution system can support the multiple mode of operation of processor simultaneously, simulate with regard to two kinds of mode of operations respectively at hardware abstraction layer.By concluding the characteristic of two kinds of processor operating modes, processor descriptive language (ProcessorDefinition Language) that definition is special-purpose and the mode by interface provide service for the upper strata.
The advantage of doing like this is, adopts the mode of unified interface that the data access difference between processor and the internal memory is eliminated, and when in the face of different processor mode, can finish configuration to processor operating mode by the interface of reserving.
4. make up corresponding fictitious order collection form; Promptly having finished behind target machine hardware abstract, set up instruction table description based on this, the effect of instruction table description is to realize the unified of different instruction table described by the instruction set definition rule.The description of instruction set is divided into again to the definition of form with to the definition of semanteme.
The descriptor of order format is stored in the instruction list.Instruction list is by and instruction form such as order code, instruction length, operand format (length, addressing mode etc.), access module, instruction system and instruct analytically dependent kernel data structure to form.During system initialization, the information of reading command table with the initialization directive system, is set up index structure simultaneously and accelerated access speed.A content that mainly comprises description in the table 2 through the instruction list after the definition.
Instruction list elementary item after table 2, the definition
| Order code | Memonic symbol | Instruction is long | The operand number | First operand is long | Second operand is long | The first operand type | The second operand type | The data access mode | Storer uses numbering | Instruction system |
| 10 | ADDB | 3 | 2 | 1 | 1 | REG | REG | BYTE | NULL | ADD |
| 20 | ADD | 3 | 2 | 1 | 1 | REG | REG | WORD | NULL | ADD |
| 30 | ADDB | 3 | 2 | 1 | 1 | REG | IMM | BYTE | NULL | ADD |
| 40 | ADD | 4 | 2 | 1 | 2 | REG | IMM | WORD | NULL | ADD |
This order set construction method has following characteristics:
(be no more than 2 in that instruction number is less
8) time, the linear directory structure that direct foundation is key with the order code can guarantee that system can be with the quick positioning instruction sign indicating number of the time complexity of O (1).
(surpass 2 when the instruction strip number of order set is more
8) time, can in guaranteed performance, not take too much index stores structure by setting up the Hash index structure.
5. make up the command logic controller; Promptly instruct the feature field of storing in instruction list to be the basis that the script sequence generates, belong to the instruction down of same instruction system, its script sequence adopts same template generation.Script template has been described the key operations directly related with hardware driving such as the bus, operation rule of read-write rule, addressing mode, data source, the use of operand, comprises that in the command logic controller script semantical definition unit and script resolution unit realize the logic control of instructing step by step.Give the method for parallel processing in the instruction parsing in Fig. 3, wherein " virtual machine controller " is the upper strata parts that call native system, and it and native system have the input and output port of standard; The explanation of the instruction resolving represented among the figure is in the transmission that can walk abreast of manipulation internal instruction analysis request and instruction prefetch request, and these operate in the system and also independently finish.
After the implication of instruction is finished definition by the script sequence, just can finish the emulation of instruction action by the hardware virtual component.The working method of native system is described with concrete execution in step below.
In finishing Embedded System Design, soft, hardware effort is normally carried out synchronously.But before hardware system is not also finished, be starved of a virtual hardware environment and come support software system design work.In order to realize the function of target machine, at first in host, carry out a large amount of work, as programming, compiling, link, these need finish (not belonging to this patent institute set forth) in the cross compilation environment of host.After finishing the cross compile link, generate the executable code of target machine.These codes can't directly be sent in the target machine and move because perhaps at this moment the hardware of target machine also do not finish, or hardware system can't guarantee the correct execution of program also through checking.At this moment need be on host artificial debugging, dispel all logic error and most execution error, and then be delivered in the target machine by communication port and move, this implementation as shown in Figure 4.The self-driven workflow of instruction resolving comprises following steps:
1) system initialization: after user program starts, system reads the analytically dependent field information of and instruction from instruction list, finish the initial configuration and the instruction process rule of hardware virtual component, instruction list and command logic controller are loaded, carry out the early-stage preparations that instruction is resolved;
2) instruction pre-service: reading command from the routine storage, and carry out preliminary analysis and decomposition;
3) instruction is resolved and the generation of script sequence: according to pretreated result the instruction system that chooses is carried out the script sequence and generate, finish this work with reference to type template and mode of operation; The script sequence is used for describing instruction action, and it can be used as input and submits to the virtual hardware parts and finish emulation to binary command stream.
4) emulation of instruction action script is carried out: instruction action script sequence generates automatically according to the description of instruction in instruction list, the execution result of script sequence passes to the upper strata calling system, obtain implementation effect by system's judgement, determine by implementation effect what work next step finishes.
Host described in Fig. 4 is the underlying hardware of instruction parsing and virtual operation, has made up the virtual emulation debugging enironment thereon, resolves and the simulation hardware executive system comprising setting up the target machine instruction; Wherein a plurality of target machine explanation native systems of mark can be supported multiple embedded system, pass to the command simulation resolution system by instruction with target machine, finish the instruction parsing and the restructuring procedure of target machine, and then the instruction after will resolving passes to the virtual hardware module, finishes the artificial debugging of target machine by it.After most of mistake of program all is corrected, more correct target machine code is passed to the target machine operation by communication port.Can reach like this and shorten the Embedded System Design cycle, in design, adopt software and hardware cooperating design method rapid adjustment design proposal, improve the system design quality effectively.
Claims (2)
1, a kind of command simulation resolution system with self-driven function is characterized in that this system comprises command logic controller, hardware virtual component, instruction pretreater and instruction list, wherein:
1) instruction pretreater: comprise respectively and the two-way communication unit that is connected of the control module of looking ahead, pretreatment unit and instruction prefetching; The control module of looking ahead of instruction pretreater passes through the bus control unit in its communication unit access hardware virtual component, and reads one section instruction stream in the storer analogue unit from the hardware virtual component; Control module look ahead then again by communication unit access instruction table, read the order format that has configured, and in pretreatment unit, carry out instruction stream and decompose; Instruction stream after the decomposition leaves in the instruction prefetching by the control module of looking ahead, as the input information of command logic controller;
2) command logic controller: comprise respectively and two-way digital control unit that is connected of communication unit and logic control element, and script resolution unit and script semantical definition unit; The command logic controller obtains to resolve by the script resolution unit in the command logic controller through pretreated command information from the instruction prefetching of instruction pretreater by its communication unit; In script resolving, need continuous communication unit to obtain required instruction description information by instruction list; Calculating process in the instruction need be finished by digital control unit and logic control element; Instruction action after the parsing is submitted to away by its communication unit, is delivered to and does further processing in the hardware virtual component;
3) hardware virtual component: comprise bus control unit, hardware effort mode definition unit, and distinguish storer analogue unit, register analogue unit, the storehouse analogue unit of two-way connection with it; Bus control unit transmits the instruction that receives the pretreater from instruction, finishes simulated operation to storer, register, storehouse according to command content; For analog hardware working method exactly, adopt bus control unit to carry out uniform dispatching to the visit of each nextport hardware component NextPort, and the user program that the analog simulation result feeds back to the upper strata is responsible for finishing simulation work to hardware pattern and type of drive;
4) instruction list: comprise interconnective instruction set definition unit and instruction set memory block, and the communication unit of the two-way connection in and instruction collection memory block; Instruction list is mainly used in the descriptor of holding instruction, and comprises form, instruction attributes, the type of drive of instruction, and instruction list is the systematicness file of instruction parsing operation, and different target machine systems will have different instruction list contents.
2, the described implementation method with command simulation resolution system of self-driven function of a kind of claim 1 is characterized in that this method may further comprise the steps:
(1) makes up the instruction pretreater: finish reading and disintegration before the instruction process by the instruction pretreater; Wherein, have access to the bus control unit of hardware virtual component, the assigned address reading command stream from the storer analogue unit by communication unit, the control module of looking ahead; Or, therefrom read the order format of target machine by the control module access instruction table of looking ahead; The information that obtains is finished instruction stream in pretreatment unit decompose; Instruction stream after decomposing is done simple parsing, leave in the instruction prefetching by the control module of looking ahead, for the command simulation resolution system provides input;
(2) set up the memory management mechanism of processor level: be not subjected to the restriction of data storage method for making the command simulation resolution system, palpus design memory analogue unit in the virtual hardware simulation component, this unit is converted to storage format on the target machine according to configuration information with multibyte data when loading bytecode;
(3) make up the processor operating mode handover mechanism: the hardware virtual component of promptly setting up target machine; In order to increase system flexibility, in these parts, need to set up the processor operating mode handover mechanism; Be system is supported simultaneously based on register with based on two kinds of mode of operations of storehouse, need in hardware is virtual, simulate two kinds of mode of operations respectively, by concluding the characteristic of two kinds of processor operating modes, the descriptive language of definition processor (Processor Definition Language) is also supplied with other module by the bus control unit in the hardware virtual component and is used;
(4) make up corresponding fictitious order collection form: promptly behind the virtual component of having finished target machine hardware, set up instruction table description based on this, the effect of instruction table description is to realize the unified of different instruction table described by the instruction set definition rule, when the instruction strip number of order set greater than 2
8The time, in guaranteed performance, do not take too much index stores structure by setting up the Hash index structure;
(5) make up the command logic controller: promptly instruct the feature field of storing in instruction list to be the basis that the script sequence generates, belong to the instruction down of same instruction system, its script sequence adopts same template generation; Script template has been described the key operations directly related with hardware driving, the bus, and the operation rule that comprise read-write rule, addressing mode, data source, the use of operand, comprise script semantical definition unit and script resolution unit in the command logic controller, substep is realized the logic control of instruction.
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| CNB2006101301035A CN100428184C (en) | 2006-12-13 | 2006-12-13 | Command simulation analytic system with automatic driving function and realizing method thereof |
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| CNB2006101301035A CN100428184C (en) | 2006-12-13 | 2006-12-13 | Command simulation analytic system with automatic driving function and realizing method thereof |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102081653A (en) * | 2010-12-31 | 2011-06-01 | 杭州华三通信技术有限公司 | Equipment service management method and device based on drive |
| CN107636609A (en) * | 2015-06-25 | 2018-01-26 | 英特尔公司 | Method and apparatus for execution pattern selection |
| CN111413897A (en) * | 2020-03-18 | 2020-07-14 | 四川中微芯成科技有限公司 | Method for safely and randomly switching working modes of chip and chip |
| CN112416857A (en) * | 2020-12-09 | 2021-02-26 | 重庆金美通信有限责任公司 | Processor-independent FPGA peripheral chip dynamic configuration method |
| CN112559039A (en) * | 2020-12-03 | 2021-03-26 | 类人思维(山东)智慧科技有限公司 | Instruction set generation method and system for computer programming |
| CN113221318A (en) * | 2021-03-30 | 2021-08-06 | 北京计算机技术及应用研究所 | DDS-based system-level simulation test environment construction method |
| CN113515348A (en) * | 2021-07-16 | 2021-10-19 | 江苏师范大学 | Simulator modeling method and device based on opportunity action flow |
| CN116431220A (en) * | 2023-06-14 | 2023-07-14 | 青岛鑫晟汇科技有限公司 | Multi-system architecture intercommunication system based on data distributed instruction set |
| CN112416857B (en) * | 2020-12-09 | 2024-04-26 | 重庆金美通信有限责任公司 | Processor-independent FPGA peripheral chip dynamic configuration method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3564445B2 (en) * | 2001-09-20 | 2004-09-08 | 松下電器産業株式会社 | Processor, compiling device and compiling method |
| CA2381744A1 (en) * | 2002-04-15 | 2003-10-15 | Ibm Canada Limited-Ibm Canada Limitee | A parsing technique to respect textual language syntax and dialects dynamically |
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| CN102081653A (en) * | 2010-12-31 | 2011-06-01 | 杭州华三通信技术有限公司 | Equipment service management method and device based on drive |
| CN102081653B (en) * | 2010-12-31 | 2013-06-26 | 杭州华三通信技术有限公司 | Equipment service management method and device based on drive |
| CN107636609A (en) * | 2015-06-25 | 2018-01-26 | 英特尔公司 | Method and apparatus for execution pattern selection |
| CN111413897B (en) * | 2020-03-18 | 2021-05-14 | 四川中微芯成科技有限公司 | Method for safely and randomly switching working modes of chip and chip |
| CN111413897A (en) * | 2020-03-18 | 2020-07-14 | 四川中微芯成科技有限公司 | Method for safely and randomly switching working modes of chip and chip |
| CN112559039A (en) * | 2020-12-03 | 2021-03-26 | 类人思维(山东)智慧科技有限公司 | Instruction set generation method and system for computer programming |
| CN112416857A (en) * | 2020-12-09 | 2021-02-26 | 重庆金美通信有限责任公司 | Processor-independent FPGA peripheral chip dynamic configuration method |
| CN112416857B (en) * | 2020-12-09 | 2024-04-26 | 重庆金美通信有限责任公司 | Processor-independent FPGA peripheral chip dynamic configuration method |
| CN113221318A (en) * | 2021-03-30 | 2021-08-06 | 北京计算机技术及应用研究所 | DDS-based system-level simulation test environment construction method |
| CN113515348A (en) * | 2021-07-16 | 2021-10-19 | 江苏师范大学 | Simulator modeling method and device based on opportunity action flow |
| CN113515348B (en) * | 2021-07-16 | 2023-11-14 | 江苏师范大学 | Simulator modeling method and device based on opportunity action flow |
| CN116431220A (en) * | 2023-06-14 | 2023-07-14 | 青岛鑫晟汇科技有限公司 | Multi-system architecture intercommunication system based on data distributed instruction set |
| CN116431220B (en) * | 2023-06-14 | 2023-08-18 | 青岛鑫晟汇科技有限公司 | Multi-system architecture intercommunication system based on data distributed instruction set |
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