CN1296815C - Marker digit optimizing method in binary system translation - Google Patents
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Abstract
The present invention relates to the technical fields of instruction set architecture and binary translation. In view of interpretive execution in the binary translation, the present invention provides a solution method with the combination of immediate calculation and delay calculation, and the method is used for optimizing mark bit processing in interpretive execution. As for dynamic translation in binary translation, the present invention provides a solution method with the combination of data flow analysis and delay calculation, and the method is used for optimizing mark bit processing during the dynamic translation. The method deletes object codes for processing redundant mark bits by a data flow analysis method in a basic translation unit, and redundant object codes generated by processing redundant mark bits among translation units are reduced by a delay calculation method which is called a DFADC method for short as follows. The number of object codes generated by mark bits used for a simulated source ISA is reduced in translation by the two methods, and the quality of translation codes is improved, thereby increasing the execution speed of translation.
Description
Technical field
The present invention relates to instruction set architecture, binary translation technical field, the optimization process method of zone bit in particularly a kind of binary translation, and corresponding compile optimization technology.
Technical background
Binary translation is one of code important method of transplanting, can (Instruction Set Architecture, ISA) code translation on is gone up operation to another kind of ISA with a kind of instruction set architecture.The purpose of binary translation is not only emulation source ISA, and higher target is original code that speed that code that translation produces moves on target ISA is equal to even surpasses source ISA.
Binary translation based on software, [E R Altman can be divided three classes, D Kaeli andY Sheffer.Welcome to the opportunities of binary translation.IEEEComputer, 2000,33 (3): 40 ~ 45]: explain and carry out, static translation, dynamically translation, because three class methods have his own strong points, research in recent years is more prone to the combination of three class methods.Which kind of translation form no matter, all must with original program semantic identical, execution result is identical, so must be kept at the system state of preserving in the special register of source ISA among the target ISA.
(as the VAX of the X86 series of Intel, Digital and Motorola68000 etc.) exists for the preservation condition sign indicating number and the flag register used on CISC ISA, the execution of a lot of instructions all can be provided with a part of zone bit wherein, and other instruction (as conditional order) can decide next step execution of program by the state of these zone bits.Yet (, Alpha), do not comprise the instruction that Status Flag is set usually as MIPS for RISC ISA.Therefore, target RISCISA can only come the Status Flag of emulation source ISA by a series of instructions.Because flag register uses frequent, its processing both had been related to the correctness that program is carried out, be related to the execution efficient after the program translation again.
To the existing vicennial history of the research of binary translation, all relate to the translation system of zone bit in the world, all zone bit are handled and are optimized, and the method that is adopted is relevant with the characteristics of system separately, as Digital company FX! 32[R J Hookway and M A Herdeg.Digital FX! 32:combining emulation and binary translation.DigitalTechnical J, 1977,9 (1): 3 ~ 12] and the Wabi[P Hohensee of Sun Microsystems, MMyszewski, and D Reese.WABI CPU emulation.Hot Chips VIII, PaloAlto, CA 1996] all adopt and postpone computing method and the zone bit in the simulator is handled optimized; The UQBT[C Cifuentes and M Van Emmerik.UQBT:adaptable binary translation at low cost.IEEE Computer of Queensland university, 2000,33 (3): 60 ~ 66] wait some static translation systems, use the data-flow analysis method to delete redundant zone bit and handle; The Code Morphing[A Klaiber.The technologybehind Crusoe processor.Transmeta Corporation of Transmeta Company, Tech Rep:Jan.2000] software then has the processing of special hardware supported zone bit.The present data-flow analysis that static translation the is adopted method comparative maturity of optimizing zone bit, the present invention solved emphatically explain carry out and dynamically in the translation zone bit handle optimization problem, new condition code optimization disposal route has been proposed.
Difference between the different instruction collective architecture (ISA), to utilizing binary translation technology transplant code to cause very big difficulty, wherein do not have the emulation of the target ISA of zone bit register support, need to increase a large amount of target ISA codes source ISA zone bit in order to realize.
Summary of the invention
The invention provides the optimization process method of zone bit in a kind of binary translation, its purpose is to reduce in binary translation process, be used for the target ISA code that zone bit is handled in a large number owing to what the zone bit emulation to source ISA generated, utilize the principle that generates the zone bit processing instruction as required to reduce redundant code, improve the quality of object code, quicken the execution of binary translation process and translation generating code.
The zone bit that the invention solves the binary translation process from source ISA to target ISA is handled problems, and can reduce the target ISA instruction that is used for emulation source ISA zone bit well, thereby improves the efficient of this type of translater.The present invention is directed to explanation in the binary translation carries out and to have proposed instant calculating and to have postponed the combine solution of (Instant Computing and Delayed Computing) of calculating, being used for optimizing the executory zone bit of explanation handles, reduced the object code memory access expense of only bringing, hereinafter to be referred as the ICDC method with the delay computing method.The dynamic translation that the present invention is directed in the binary translation has proposed data-flow analysis and the solution that postpones to calculate combine (Data FlowAnalysis and Delayed Computing), zone bit when optimizing dynamically translation is handled, this method adopts the deletion of data-flow analysis method to handle the object code of redundant zone bit in basic translation unit, reduces the redundancy object code of handling redundant zone bit between the translation unit and generating and postpone computing method in employing between the translation unit.Hereinafter to be referred as the DFADC method.By above-mentioned two kinds of methods, reduce the object code quantity that is used for the zone bit of emulation source ISA and produces in the time of can making translation, improved the quality of interpreter code, thereby the translation execution speed is improved.
The present invention is used for the zone bit of binary translation process between the computing machine and handles, and is widely used among the computing machine.
One, explains executory instant calculating and postpone to calculate the method (ICDC method) that combines
Statistics finds that the definite value of a plurality of zone bits is not to isolate, and normally an instruction is to a plurality of signs while definite values.For example in the X 86 processor, the overwhelming majority all is to indicate definite value together to all commonly used, referring to the appendix A of [Intel Architecture SoftwareDeveloper ' s Manual Volume 1 Basic Architecture] to the instruction of zone bit definite value.For fear of a large amount of accessing operations, we are used for preserving same command information to the identical information memory cell of all sign definition.When the instruction of certain bar, is used to postpone Calculation Method simultaneously during definite value to all N zone bits, when being saved in default storage unit for delay calculation flag position, use operational code, operand and the operation result of this instruction; And work as certain bar instruction only to the part definite value in N the zone bit, then according to the zone bit number of definite value, will postpone to calculate and instant calculations incorporated use according to following two kinds of rules:
A) if being less than, the sign number of definite value equals N/2, then when this instruction of simulation, these three signs are also calculated immediately according to the computing situation, be stored in the flag register of simulation, when subsequent instructions is quoted this several sign, can directly take the state in the register, need not from information memory cell, to take out message delay and calculate sign.The content of information memory cell remains unchanged, without the information covering of this instruction.
B) if the conventional number of definite value, then at first will not decided (information that this may need by instruction preservation in front in the information memory cell postpones to calculate, and deposits the result in flag register) greater than N/2 by several zone bit states of this instruction definite value.And then the relevant information that will instruct deposits the canned data unit in, use when quoting these by the sign of this instruction definite value for subsequent instructions (subsequent instructions needs message delay calculation flag in view of the above).
ICDC method flow process is described
Define an information memory cell M{opcode, operand1, operand2, result}.Define the flag register Rfx of simulation, be used to preserve N the zone bit of source ISA.Definition and the corresponding state indication of each sign Fx Sx{defined, undefined}, defined represent that this sign is calculated, and the result has placed Rfx.
When explaining certain bar instruction, explain according to following flow process and carry out this instruction:
1. if this instruction need be quoted certain sign, then read the corresponding Sx state of Rfx
I. as if Sx=undefined, promptly this sign is not calculated, and then reads the information among the M, do corresponding sign and calculate, draw the sign state, this state is write back corresponding Rfx, and change the corresponding Sx of Rfx into defined, explain according to this result then and carry out this instruction;
Ii. as if Sx=defined, promptly this sign is calculated, and then directly carries out the explanation execution of this instruction according to the sign state among the Rfx.
2. if this instruction has definite value to n sign, then
I. if n＜=N/2 then when explaining this instruction of execution, calculates this n sign state immediately, write back corresponding Rfx, and change the corresponding Sx state of Rfx into defined;
Ii. if n＞N/2, (this does not depend on this N-n the original corresponding Sx of sign to that N-n sign state of its definite value then at first to calculate this instruction, may need to calculate by the value that reads among the M, also these sign states of possibility have been to calculate to deposit among the Rfx), the Sx of these several signs changes defined into afterwards, and the result writes back corresponding Rfx.
The corresponding information that will instruct is saved in M at last, and will need n the corresponding Sx of sign of definite value to change undefined into;
Repeat above-mentioned steps up to end.
Above-mentioned instant calculating is calculated the flag bit processing method that combines with delay, utilize instruction among the ISA of source to the characteristics of zone bit definite value, reduced delay and calculated the target ISA code memory access expense that the phantom load position is caused, made and explain that the efficient of carrying out is improved.
Two, the data-flow analysis in the dynamic translation calculates the method (DFADC method) that combines with delay
Binary translation is only just translated this section code when source ISA program code is performed, the control flow relation of source program is along with program implementation forms gradually, and is not dynamically constantly to generate whole control flow graphs.Generally, when one section code of translation, (do not carry out this section code this moment), and do not know to continue thereafter, thereby the data-flow analysis method that static translation adopted can only be applied in dynamic translation in the subrange of a translation unit (as a fundamental block).In order to make follow-up translation unit can quote forerunner's translation unit is the fixed value of zone bit, can only when translation, several the instructions of outlet increase at each translation unit calculate this translation unit inside to the final definite value result of zone bit, no matter and whether follow-up translation unit can be quoted.
So it is limited to the optimization effect that dynamic translation reaches that data-flow analysis is deleted the method for redundant zone bit definite value, the instruction of the calculation flag place value that is increased in each translation unit outlet still may be redundant zone bit constant value command.
Characteristics at dynamic translation, our condition code optimization in dynamic translation process, condition code optimization strategy in conjunction with static translation and explanation execution, proposition is adopted the data-flow analysis method in basic translation unit, postpone Calculation Method and between translation unit, use, make it can either reduce basic translation unit inside, can reduce again between the basic translation unit because of handling the redundancy object code that redundant zone bit generates.
This method rule is as follows:
A) the sign definite value in the translation unit is quoted and is carried out data-flow analysis, identifies redundant zone bit definite value, when this translation unit of translation, this type of definite value is not handled.
B) if the instruction of certain bar is to the last definite value point of certain zone bit in this translation unit, then when this instruction of translation, generate the preservation current state and (may comprise source operand, execution result and operational code) instruction, calculate use when really needing this value of statistical indicant after being provided with, but do not generate the instruction of the current value of statistical indicant of instant calculating.
C) if instructing, need quote certain bar certain sign, but the definite value of this value of statistical indicant point is not in this translation unit inside, then need many translations to generate some instructions, be used to read the information that forerunner's translation unit is preserved for this zone bit definite value, and carry out the calculating of zone bit according to these information.
DFADC method flow process is described
In order to realize data-flow analysis in the above-mentioned basic translation unit, postpone Calculation Method between translation unit, we slightly make an amendment static data flow analysis, make it both can delete the redundant definite value in the basic translation unit, can provide information for postponing to calculate again, certain definite value is the inner use of elementary cell, the elementary cell outside may be used or useless definite value thereby can indicate.After obtaining these information, according to following flow processing:
When certain basic translation unit B of translation, if interpretive order Iy, y[1, N] then:
1. if Iy quotes Fx
A) if Sx is defined, translation generates instruction, is used for reading the value of Rfx Fx,
B) otherwise, translation generates instruction, is used for reading the value of Mx, and calculates Fx; (be and postpone to calculate)
Translation generates instruction, is used for carrying out different paths or finishing different functions according to the different value of Fx;
2. if Iy definite value Fx
A) if this definite value will be translated instruction use in the unit, then translation generates instruction, is used for calculating Fx and deposits the Fx value that calculates in Rfx, also Sx will be changed into defined;
B) if this definite value may be translated the unit external instruction to be used, then translation generates instruction, is used for being saved in Mx and changing Sx into undefined postponing to calculate the required current information of Fx;
C) if this definite value is useless definite value, then do not generate the instruction of any processing zone bit;
3. if Iy does not have influence to Fx, then do not generate the instruction of any processing zone bit;
In the above-mentioned flow process, Fx is value of statistical indicant, Iy for instruction, B are that basic translation unit, Rfx are that flag register, Sx are that corresponding state position, the Mx of flag register is information memory cell (Mx), and this translation unit has the instruction of N bar.Wherein Rfx preserves the value of sign Fx; Whether Sx is used for indicating the value of corresponding flag register Rfx available, if defined is then available, if undefined could use after then needing this value of statistical indicant calculated; Mx is used to preserve the information that is used to calculate the Fx right value.
Use between the translation unit of mentioning in the DFADC method to postpone computing method, combine part equally and postpone to calculate,, do not repeat them here owing in the ICDC method, illustrate.
Description of drawings
Fig. 1 is the instant synoptic diagram that calculates and postpone to calculate of zone bit in the binary translation of the present invention;
Fig. 2 is the instant calculating zone bit handled when carrying out of explanation of the present invention and the process flow diagram that postpones the ICDC disposal route that calculating combines;
The process flow diagram that postpones the DFADC disposal route that calculating combines in the basic translation unit of when Fig. 3 is dynamic translation of the present invention zone bit being handled between data-flow analysis and basic translation unit.
Among Fig. 1, these two kinds differences of handling the method for zone bit as can be seen:
A has represented one section code of source ISA among the figure, (1) can change the value of certain zone bit F after the instruction of representing this place is carried out, (2) instruction of representing this place need be operated (the CMP instruction as x86 changes the ZF sign, and JZ instructs and indicates according to ZF whether successful decision control is shifted) accordingly according to the value that indicates F; Figure B represents that target ISA calculates immediately to the zone bit definite value of figure shown in the A, promptly when handling the instruction of (1) locating, simulates whole zone bit definite value semantemes, uses during the instruction located for processing (2); Figure C represents that target ISA postpones to calculate to the zone bit definite value shown in the figure A, promptly when handling the instruction of (1) locating, phantom load position definite value semanteme not, but preserve the command information that (1) is located, when handling the instruction of (2) locating, just the command information of reading and saving is only simulated and is generated the value of statistical indicant that this place's actual needs uses.Postpone as can be seen to calculate to compare, saved the expense of many useless sign simulations, but also increased the expense of preservation and reading command information with instant calculating.
Among Fig. 2, alphabetical implication in the process flow diagram: information memory cell M{opcode, operand1, operand2, result}.The flag register Rfx of simulation, N the zone bit Fx content that is used to preserve source ISA.With the corresponding state indication of each sign Fx Sx{defined, undefined}, defined represent that this sign is calculated, and the result has placed Rfx.
At first execution in step S1 takes out a source ISA instruction, if this instruction is not END instruction, then divides following three kinds of situations:
1, some zone bit is quoted, then execution in step S2 reads the pairing state Sx of Rfx successively, if Sx is undefined, then execution in step S3 reads the state that content among the information memory cell M postpones to calculate sign fx, write back Rfx, and change corresponding Sx into defined.Last execution in step S4,, explain according to the sign state Fx among the Rfx and to carry out this instruction.Read Rfx sign state, explain and carry out this instruction.
2, n (n＞0) zone bit there is definite value, then if n＞N/2 is execution in step S5.1 ~ S5.4 successively then; 1, postpones to calculate remaining N-n sign state, and write back corresponding Rfx.The corresponding information that S5.2, corresponding Sx put defined S5.3, preserve this instruction is to Information Access unit M, and needs that n the corresponding Sx of sign of definite value to be changed to undefined (in order to delay calculating); If n＜=N/2 is execution in step S6.1 ~ S6.3 successively then; 6.1, calculate this n sign state immediately, and write back corresponding RfxS6.2, corresponding Sx and be changed to definedS6.3, explain and carry out this instruction.
3, if this instruction zone bit is not had quote, definite value, execution in step S7 then, directly this instruction of explanation execution.
Same Fig. 2 of alphabetical implication among Fig. 3.Preprocessing part is finished improved data-flow analysis to a dynamic translation unit, has obtained the classified information of every instruction of this translation unit to the zone bit definite value, handles every instruction of this translation unit on this information basis again by following steps in sequence.
Execution in step S8 takes out source ISA instruction, if this instruction is not the translation unit END instruction, then:
1, if this instruction reference indication Fx, judge then whether the pairing Sx of Fx is defined, if, illustrate that then the value in the Rfx register can directly use, execution in step S9, translation generates the target instruction target word that is used for reading Rfx Fx value, and execution in step S10 translation generates instruction, is used for carrying out different paths or finishing different functions according to the different value of Fx; If not then the Fx value among explanation Rfx this moment is not correct value, then execution in step S11 translation generates instruction, is used for reading the value of Mx, and postpones to calculate Fx; Deposit this value in Rfx, Sx puts defined, postpones to calculate correct Fx value, execution in step S10 then.
2, if this instruction definite value sign Fx, the information that obtains according to pre-service then, carry out following processing:
If this definite value is in the inner use of this translation unit, then execution in step S12 translation generates instruction, is used for calculating Fx and deposits the Fx value that calculates in Rfx, also will change Sx into defined;
If this definite value may be used outside this translation unit, then execution in step S13 translation generates instruction, is used for being saved in Mx and changing Sx into undefined postponing to calculate the required current information of Fx;
If this definite value is not used, then execution in step S14 does not generate the instruction of any processing zone bit;
Claims (2)
1, the optimization process method of zone bit in a kind of binary translation is characterized in that:
Reduce the object code that the processing sign generates in the inner data-flow analysis method of using of basic translation unit; Utilize to postpone computing method reduce between the basic translation unit because of handling the object code that sign increases; This method step is as follows:
A) the zone bit definite value in the translation unit is quoted and is carried out data-flow analysis, identifies redundant zone bit definite value, when this translation unit of translation, this type of definite value is not handled;
B) if the instruction of certain bar is to the last definite value point of certain zone bit in this translation unit, then when this instruction of translation, generate the instruction of preserving current state, calculate when really needing this zone bit definite value after being provided with and use, do not generate the instruction of instant calculating current mark bit definite value;
C) if instructing, need quote certain bar certain zone bit, the definite value point of this zone bit is not in this translation unit inside, then need many translations to generate some instructions, be used to read the information that forerunner's translation unit is preserved for this zone bit definite value, and carry out the calculating of zone bit according to these information.
2, according to the optimization process method of zone bit in the binary translation of claim 1, data-flow analysis combines with postponing calculating substantially between translation unit in the basic translation unit of when dynamically translating zone bit being handled, and its step is as follows:
Step S8 takes out source ISA instruction, if this instruction is not the translation unit END instruction, then:
1) if this instruction reference indication Fx, judge then whether the pairing Sx of Fx is defined, if, illustrate that then the value in the Rfx register can directly use, execution in step S9, translation generates the target instruction target word that is used for reading Rfx Fx value, and execution in step S10 translation generates instruction, is used for carrying out different paths or finishing different functions according to the different value of Fx; If not then the Fx value among explanation Rfx this moment is not correct value, then execution in step S11 translation generates instruction, is used for reading the value of Mx, and postpones to calculate Fx; Deposit this value in Rfx, Sx puts defined, postpones to calculate correct Fx value, execution in step S10 then;
2) if this instruction definite value sign Fx, the information that obtains according to pre-service then, carry out following processing:
If this definite value is in the inner use of this translation unit, then execution in step S12 translation generates instruction, is used for calculating Fx and deposits the Fx value that calculates in Rfx, also will change Sx into defined;
If this definite value may be used outside this translation unit, then execution in step S13 translation generates instruction, is used for being saved in Mx and changing Sx into undefined postponing to calculate the required current information of Fx;
If this definite value is not used, then execution in step S14 does not generate the instruction of any processing zone bit.
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| CN1332308C (en) * | 2004-09-10 | 2007-08-15 | 中国科学院计算技术研究所 | Translation method in dynamic binary translation |
| CN100377088C (en) * | 2005-03-04 | 2008-03-26 | 中国科学院计算技术研究所 | Local variant identification and upgrading processing method in binary translation |
| CN100359472C (en) * | 2005-07-01 | 2008-01-02 | 中国科学院计算技术研究所 | Method for processing library function call in binary translation |
| CN100462922C (en) * | 2007-11-01 | 2009-02-18 | 上海交通大学 | Binary translation method using intermediate command set |
| CN101299192B (en) * | 2008-06-18 | 2010-06-02 | 中国科学院计算技术研究所 | Non-aligning access and storage processing method |
| CN106873944A (en) * | 2016-12-23 | 2017-06-20 | 北京北大众志微系统科技有限责任公司 | The method and apparatus that indirectly transferring instruction is processed in dynamic binary translation system |
| CN117369830A (en) * | 2023-07-26 | 2024-01-09 | 龙芯中科技术股份有限公司 | Binary translation method, electronic device, and readable storage medium |
| CN117555555B (en) * | 2024-01-11 | 2024-04-12 | 龙芯中科技术股份有限公司 | Exception processing method, device, electronic equipment and storage medium |
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| US5842017A (en) * | 1996-01-29 | 1998-11-24 | Digital Equipment Corporation | Method and apparatus for forming a translation unit |
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| US5842017A (en) * | 1996-01-29 | 1998-11-24 | Digital Equipment Corporation | Method and apparatus for forming a translation unit |
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| CN101221496B (en) * | 2008-01-23 | 2011-10-26 | 中国科学院计算技术研究所 | RISC processor device and data processing method thereof |
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Granted publication date: 20070124 |