CN100351813C - Method of storage unit access in digital signal processing system and processing system therefor - Google Patents
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Abstract
The present invention relates to a method for accessing a storage unit in a digital signal processing system and a processing system for accessing a storage unit in a digital signal processing system, which are used for finishing carrying out an N2 bit access of a storage unit the data width of each address of which is N1 bit. The method comprises: (1) establishing the mapping relationship between the storage unit and logic space; (2) carrying out the N2 bit access of the storage unit. Establishing the mapping relationship between the storage unit and the logic space comprises a 1: setting Q areas in the logic space, and Q equals N1/N2; a 2: establishing corresponding relationship between each address unit of the storage unit and one address of each of the areas of the step a 1; a 3: establishing mapping relationship between the storage unit and the Q areas and making mapping relationship exists between the [N2*(X-1), N2*X-1] bit of each of the address units of the storage unit and the address unit corresponding to the number X area in the logic space; when carrying out the N2 bit access of the storage unit, firstly judging on which area X the access address is positioned, then reading data/writing data from the [N2*(X-1), N2*X-1] bit of the address units corresponding to the storage unit. The method not only overcomes the defect of wasting DSP resources, but also raises the utilization rate of stored resources.
Description
Technical field
The present invention relates to the method and the digital information processing system thereof of storage unit access in the digital information processing system (DSP), relate in particular to 16 bit DSPs and support 8 bits visit method for addressing and digital information processing system thereof.
Background technology
Dsp system also claims digital signal processor (dsp chip), and it is a kind of microprocessor with special construction.The Harvard structure that the inside of dsp chip adopts program and data to separate has special hardware multiplier, extensively adopts stream line operation, and special DSP instruction is provided, and can be used for realizing apace various digital signal processing algorithms.Since early 1980s, dsp chip was born, dsp chip had obtained development at full speed in more than 20 years time, and the ratio of performance to price of dsp chip improves constantly, and development tool is more and more perfect.Dsp chip is widely used in many fields such as Communication and E1ectronic Systems, Signal and Information Processing, control automatically, radar, military affairs, Aero-Space, medical treatment, household electrical appliance.
See also Fig. 1, it is the inner structure synoptic diagram of existing a kind of DSP embedded system.It comprises DSP kernel 11, Memory Management Unit 12 and the storage unit 13 that is used to store the DSP instruction and data.Wherein, DSP kernel 11 is core cells of dsp system, finishes data-signal by the instruction of programming in advance and handles.Usually, instruction that operates on it and the object of instruction manipulation (as data) come from the external unit or the external chip of dsp system.DSP kernel 11 will be handled after will being mapped as virtual logical space to the external data of DSP operation,, by logical space external data be read in the aftertreatment of DSP kernel that is.
Memory Management Unit 12 is used to set up the mapping relations between the physical storage address of logical space and storage unit 13, finishes DSP kernel 11 from storage unit 13 reading of data and with the function of data write storage unit 13.In addition, Memory Management Unit 12 also is used to finish the DSP Access Management Access and storage unit is organized two parts function.
Such as: because DSP is a high-performance treatments system, therefore need access data from storage unit 13 at a high speed.Usually, high performance DSP generally contains a plurality of FPDP, guarantees the smooth and easy of the inner streamline of DSP thus.And these a plurality of FPDP need be visited same logical space, and the queuing during those FPDP access logic spaces, the management of access conflict, the buffer memory of visit data are generally all finished by Memory Management Unit.Simultaneously, the Storage Unit Management system also is responsible for the tissue to the instruction and data unit.
See also Fig. 2, the exemplary plot of the mapping relations one by one between logical space of in Memory Management Unit 12, setting up and the storage unit (as the RAM of storage data) 13.Suppose that real RAM total volume has 64K, its width is 16 bits, and the concrete configuration form is not limit.And the capacity of logical space is 128K, and its width also is 16 bits.The 0-64K of logical space sets up mapping relations one by one with the 0-64K of storage unit respectively.That is, when access instruction was a certain address of access logic space 0～64K, what return was the value of corresponding with it storage unit; If when access instruction was a certain address of access logic space 64K～128K, what return was null value.
DSP is to realize by the data access command in the DSP instruction set to the visit of storage unit 13.Data read (load) instruction is read into external data in the inner general-purpose register, and data write command (store) is write (as RAM) in the storage unit 13 with the data of inner general-purpose register.Its inner general-purpose register of 16 bit DSPs generally all is 16.The width of supposing storage unit 13 also is 16 bits, and then DSP supports storage unit 13 is carried out the visit of 16 bits at least.In order to satisfy the data throughput of DSP, generally have more rich data access instruction in the instruction set of DSP, such as: support storage unit 13 is carried out 32 bits even to the visit of 64 bits, promptly an instruction can a plurality of data of access.But some DSP, as the ZSP system of Infineon Technologies Corp., the address unit of its data-carrier store is 16 bits, does not support 8 bit access instructions to storage unit in its instruction set.
That is to say that in the application of communication and Flame Image Process, its data layout often is 8 bits.DSP is when handling these application like this, if adopt two bytes be synthesized to one 16 bit storage in storage unit 13, then when reading a certain 8 Bit datas, because storage unit is that unit stores with 16 bits, therefore the 16 bit storage contents that need to comprise this 8 Bit data earlier are read into a certain internal storage unit earlier, and then, put into general-purpose register at last with taking out this 8 Bit data in this 16 bit storage content.The method of this storage unit access can expend DSP and handle resource, causes the wasting of resources thus.Superimpose data is that the unit is stored in the storage unit with 8 bytes, and obviously, the width of storage unit is 16 bits, causes the waste of a large amount of storage resources thus.
That is to say, for some dsp systems, the unit address data width of its storage unit is N1 bit (width that is data storage is the N1 bit), need finish storage unit is carried out the visit of N2 bit, but there is not support the data storage unit to be carried out the visit (N2＜N1) of N2 bit in the existing instruction set, in this case, the existing scheme that storage unit is carried out the visit of N2 bit will cause DSP to handle the wasting of resources or cause the waste of DSP storage resources.
Summary of the invention
The object of the present invention is to provide the method and the digital information processing system thereof of storage unit access in a kind of digital information processing system, to solve the visit that needs storage unit is finished lower particle in the prior art, but when instruction set is not supported this visit, how to finish the visit of storage unit and do not influence the technical matters of the DSP wasting of resources.
For addressing the above problem, the present invention discloses the method for storage unit access in a kind of digital information processing system, being used to finish to the unit address data width is that the storage unit of N1 bit is carried out the visit of N2 bit, comprise: (1) sets up the mapping relations of storage unit and logical space: a1: Q zone is set: first zone, second zone on logical space ... Q zone, wherein, Q=N1/N2; A2: mapping relations are set up in a storage unit and a described Q zone: there are mapping relations in [N2 * (X-1), N2 * X-1] position of each address location of this storage unit, X ∈ [1, Q] with X of logical space regional corresponding address unit; (2) when storage unit being carried out N2 bit when visit, judge earlier which regional X reference address is positioned at, then from [N2 * (X-1), N2 * X-1] position sense data/write data of storage unit corresponding address unit, wherein, N1＞N2.
Also comprise before the step a2: storage unit is divided into special access zone and generic access zone, and wherein, there are mapping relations one to one in each address location in generic access zone and an address location of logical space; Storage unit is meant the special access zone of storage unit described in step a2, the step (2).
Also comprise before the step a2: set in advance a zone bit, be used to identify the special access zone is carried out the visit of N2 bit or carried out the visit that instruction set is supported.
By two variablees of Low_add, High_add are set storage unit is divided into special access zone and generic access zone, wherein, is positioned at that [Low_add, storage unit High_add) is the special access zone.
When if the memory capacity of storage unit is JKB, then among the step a1 first zone be [Low_add, High_add), second area is [Low_add+JKB, High_add+JKB) ... Q zone be [Low_add+JKB * (Q-1), High_add+JKB * (Q-1)); Among the step a2 each address location add in the special access zone of storage unit respectively with the X zone in add+JKB * (X-1) there are mapping relations one by one in the address, X ∈ [1, Q].
Wherein N1 is 16 among the present invention, and N2 is 8.
The invention also discloses a kind of digital information processing system, being used to finish to the unit address data width is that the storage unit of N1 bit is carried out the visit of N2 bit, comprise the DSP kernel, Memory Management Unit and storage unit, Memory Management Unit connects DSP kernel and storage unit respectively, Memory Management Unit also comprises mapping subelement and visit subelement, wherein, described mapping subelement: there is corresponding relation in an address in each zone in Q the zone that each address location of storage unit sets in advance with logical space respectively, and the Q of storage unit and logical space sets up mapping relations in a zone: each address location of this storage unit [N2 * (X-1), N2 * X-1] there are mapping relations in the regional corresponding address unit of position and X of logical space, X ∈ [1, Q]; Visit subelement: connect the mapping subelement, be used to receive when storage unit carried out the order of N2 bit visit, judge earlier which regional k reference address is positioned at, then from [N2 * (X-1), N2 * X-1] position sense data of storage unit corresponding address unit/write data.
Mapping is preserved in the subelement is the corresponding relation of address existence in each zone in Q zone setting in advance with logical space respectively of each address location in the special access zone of storage unit, and preserve the special access zone of storage unit and Q the mapping relations that the zone is set up of logical space, the visit subelement is [N2 * (X-1), N2 * X-1] position sense data/the write data from corresponding address unit, the special access of storage unit zone.
Compared with prior art, the present invention has the following advantages: the present invention realizes checking the visit that storage unit is finished lower particle in the DSP by the mapping relations that rebulid storage unit and logical space, and the processing resource of DSP is not wasted in this visit.
This method can also the exented memory space.Such as, when the data in the internal memory have only N2 significance bit, adopt the present invention can expand more address space, and then improved the utilization factor of resource.
Description of drawings
Fig. 1 is the inner structure synoptic diagram of existing a kind of DSP embedded system;
Fig. 2 is the logical space set up in Memory Management Unit and the exemplary plot of the mapping relations one by one between the storage unit;
Fig. 3 is the process flow diagram of the method for storage unit access in the digital information processing system of the present invention;
Fig. 4 is the mapping relations figure of special access zone among the present invention and generic access zone and logical space;
Fig. 5 for the zone of special access zone and logical space [low_addr, high_addr) and regional [low_addr+0x10000, mapping relations figure high_addr+0x10000);
Fig. 6 is 8 and reads/8 instance graphs of writing;
Fig. 7 is 8 and reads/16 instance graphs of writing.
Embodiment
Below in conjunction with accompanying drawing, specify the present invention.
The present invention does not increase the instruction of DSP kernel at the configuration mode that does not change original storage unit (as RAM) yet, but by changing the mapping relations of storage unit and logical space in the Memory Management Unit, reaches the purpose of storage unit access.
See also Fig. 3, it is the process flow diagram of the method for storage unit access in the digital information processing system of the present invention.This method is mainly used in and finishes the unit address data width is that the storage unit of N1 bit is carried out the visit of N2 bit, and N1 is some multiples of N2.It may further comprise the steps:
S110: the mapping relations of setting up storage unit and logical space:
S210: Q zone is set: first zone, second zone on logical space ... Q zone, wherein, Q=N1/N2;
S220: each address location of storage unit respectively with each zone of step S210 in an address set up corresponding relation;
S230: mapping relations are set up in a storage unit and a described Q zone: there are mapping relations in [N2 * (X-1), N2 * X-1] position of each address location of this storage unit, X ∈ [1, Q] with X of logical space regional corresponding address unit;
S120: when storage unit being carried out N2 bit when visit, judge earlier which regional X reference address is positioned at, then from [N2 * (X-1), N2 * X-1] position sense data/write data of storage unit corresponding address unit, wherein, N1＞N2.
One, the specific implementation of description of step S110
More flexible in order to visit, storage unit can be divided into two zones: special access zone and generic access zone, wherein, still there are mapping relations one to one in generic access zone and logical space, and the visit of N2 bit is then supported storage unit is carried out in the special access zone.Certainly, the present invention can not carry out subregion to storage unit yet.
When subregion, whole memory unit can be divided into statically two zones.If the memory capacity of storage unit is JKB, such as, [0, M) zone is the special access zone, and [M, JKB) zone is the generic access zone.But consider the dirigibility of follow-up data storage, can storage unit be divided into special access zone and generic access zone by two variablees of Low_add, High_add are set.These two variablees of Low_add, High_add all be positioned at the zone [0, JKB) in the scope.Wherein, be positioned at [Low_add, storage unit High_add) is the storage unit in special access zone, the storage unit that is not positioned at this zone is the storage unit in generic access zone.Variables L ow_add, High_add can have DSP dynamically to specify, and can change according to demand at any time.
At first, Q zone is set at least on logical space: first zone, second zone ... Q zone, wherein Q=N1/N2.If the memory capacity of storage unit is JKB, then first zone is [Low_add, High_add), second area be [Low_add+JKB, High_add+JKB), Q zone is [Low_add+JKB * (Q-1), High_add+JKB * (Q-1)), promptly X zone be [Low_add+JKB * (X-1), High_add+JKB * (X-1)), X ∈ [1, Q] wherein.
Then, set up storage unit the special access zone each address location respectively with Q the zone each zone in an address set up corresponding relation.Such as, each address location add respectively with the add+JKB address in first regional add, second zone ..., Q zone add+JrKB * (Q-1) mapping relations are set up in the address, be storage unit the special access zone each address location add respectively with the X zone in add+JKB * (X-1) there are mapping relations in the address, X ∈ [1, Q].
Subsequently, mapping relations are set up with the data in special access zone in Q zone: [0 of each address of first area and the corresponding address unit in special access zone, N2-1] there are mapping relations in the position, [the N2 of each address of second area and the corresponding address unit in special access zone, N2 * 2-1] there are mapping relations in the position, [N2 * (Q-1), N2 * Q-1] of the corresponding address unit in each address and the special access zone in Q zone exists mapping relations.That is, mapping relations are set up with a described Q zone in the special access of storage unit zone: [N2 * (X-1), N2 * X-1] of the corresponding address unit in X each regional address and special access zone exists mapping relations, X ∈ [1, Q].
When storage unit not during subregion, each address location of storage unit respectively with each zone of step a1 in an address set up corresponding relation; S230: mapping relations are set up in a storage unit and a described Q zone: have mapping relations, X ∈ [1, Q] with [N2 * (X-1), N2 * X-1] position of each address location of this storage unit with X of logical space regional corresponding address unit.
Two, the specific implementation of description of step S120
When storage unit being carried out N2 bit when visit, judge earlier which regional X reference address is positioned at, then from [N2 * (X-1), N2 * X-1] position sense data/write data of storage unit corresponding address unit, wherein, N1＞N2.
If storage unit is divided into two zones in advance, special access zone and generic access zone judge earlier then whether the logical space address of visit is positioned at this Q zone of logical space, if, then can carry out the visit of N2 bit to it, otherwise, can be that it is carried out generic access.When storage unit is carried out N2 bit reading of data, judge earlier which regional k reference address is positioned at, then from [N2 * (k-1), N2 * k-1] position sense data of corresponding address unit, special access zone.Storage unit is carried out the N2 bit when writing data, judge earlier which regional k reference address is positioned at, then data are write in [N2 * (k-1), N2 * k-1] position of corresponding address unit, special access zone.
If storage unit sets in advance a zone bit, detect zone bit earlier, if zone bit shows the visit of the special access zone not being carried out the N2 bit, then the visit that instruction set is supported is carried out in the special access zone.Described zone bit is used to identify the special access zone is carried out the visit of N2 bit or carried out the visit that instruction set is supported.
Based on access method of the present invention, the present invention transforms existing dsp system.
A kind of digital information processing system, being used to finish to the unit address data width is that the storage unit of N1 bit is carried out the visit of N2 bit, comprise DSP kernel, Memory Management Unit and storage unit, Memory Management Unit connects DSP kernel and storage unit respectively, Memory Management Unit also comprises mapping subelement and visit subelement, wherein
Described mapping subelement: there is corresponding relation in an address in each zone in Q the zone that each address location of storage unit sets in advance with logical space respectively, and the Q of storage unit and logical space sets up mapping relations in a zone: each address location of this storage unit [N2 * (X-1), N2 * X-1] there are mapping relations in the regional corresponding address unit of position and X of logical space, X ∈ [1, Q];
Visit subelement: connect the mapping subelement, be used to receive when storage unit carried out the order of N2 bit visit, judge earlier which regional k reference address is positioned at, then from [N2 * (X-1), N2 * X-1] position sense data of storage unit corresponding address unit/write data.
Storage unit comprises special access zone and generic access zone, wherein, mapping is preserved in the subelement is the corresponding relation of address existence in each zone in Q zone setting in advance with logical space respectively of each address location in the special access zone of storage unit, and the relation of mapping is set up with Q zone of logical space in the special access zone of preserving storage unit, the visit subelement is [N2 * (X-1), N2 * X-1] position sense data/the write data from corresponding address unit, the special access of storage unit zone.
Transformation to Memory Management Unit normally realizes by software.
Below just to be that the visit that the storage unit of 16 bits is carried out 8 bits is an example to the unit address data width, specify the present invention.The capacity of supposing storage unit is 64K, then in Memory Management Unit of the present invention, changes existing man-to-man mapping relations.It is to organize with the unit more than 16 that some application datas are always arranged in application, and another part is organized with 8, in order to keep dirigibility, data space RAM is divided into two zones: special access zone and generic access zone, the mapping scheme of these two zones and logical space as shown in Figure 4.Wherein the generic access zone also keeps original mapping relations one to one, at the gray area of Fig. 4.The special access zone is the shadow region of Fig. 4, supports the various differences of read-write access type flexibly by different mapping configurations.The special access zone is specified by parameter l ow_addr and high_addr.
In implementation procedure, parameter l ow_addr and high_addr can have DSP dynamically to specify, and can change according to demand at any time.Set a variable byte_en simultaneously, when this variable was 1, the special access zone effectively; If byte_en=0, then all 64K data RAM spaces are all shone upon by normal one-one relationship.
The special access zone corresponding to the zone of logical space [low_addr, high_addr) and the zone [low_addr+0x10000, high_addr+0x10000).These two zones corresponding to the physical space in special access zone [low_addr, high_addr).Its mapping relations as shown in Figure 5.
If logical space address addr satisfy addr ∈ [low_addr+0x10000, high_addr+0x10000), then [7:0] bit of addr is mapped to [15:8] bit of physical space address addr-0x10000; If logical space address addr satisfies addr ∈ [low_add, high_addr), then [7:0] bit of addr is mapped to physical space address addr[7:0].
Therefore, in Memory Management Unit, the present invention has adopted two kinds of mapping modes: general mapping mode and special mapping mode.For the generic access zone, adopt general mapping mode, DSP is according to original mode accesses data memory.For the special access zone, read and write can select to adopt general mapping mode and special mapping mode respectively, and the special access mode that therefore combines can be divided into 3 kinds.Write for 8, read for 8; Write for 16, read for 8; Writing 16 for 8 reads.
If special write operation is defined as 8 and writes, when a write operation address addr (low_addr, high_addr) interval in the time, the least-significant byte of data writes the least-significant byte of data RAM addr address, its most-significant byte remains unchanged; When a write operation address addr (0x10000+low_addr, in the time of 0x10000+high_addr), the least-significant byte of data writes the most-significant byte of corresponding address ram (addr-0x10000), its least-significant byte data remain unchanged.
In like manner, if the special area read operation is defined as 8 and reads, when read operation address addr was in [low_addr, high_addr] is interval, tentation data RAM was ram[15:0 in the data of address addr storage], the data of then reading back are { 0x00, ram[7:0] }; When reading the address when [0x10000+low_addr, 0x10000+high_addr], the data of reading back are { 0x00, ram[15:8] }.
When the data in the internal memory have only 8 significance bits, adopt this pattern can effectively utilize storage resources, be equivalent to [0x10000+low_addr, 0x10000+high_addr] address space in increased the RAM of one 8 bit for DSP this moment.
Embodiment
The present invention can be used for the exchange with external data, can finish the operation of unpacking easily.In application such as Flame Image Process, data often are 8 and are arranged in closely in the data-carrier store of DSP outside.When data are called in the internal RAM of DSP, must adopt 16 to write to guarantee the correctness of data.Adopt 8 modes of reading this moment, only need simple load instruction just can finish unpacking of data, be about to most-significant byte and be read into respectively in the different general-purpose registers, as shown in Figure 6 with least-significant byte.16 read/8 write
With 8 read/16 write similarly, this pattern is applied to carry out exchanges data with the external memory storage of DSP, can finish the group package operation easily, as shown in Figure 7.DSP reads data from storage unit in 16 modes, and writes in 8 mode.
More than disclosed only be several specific embodiment of the present invention, but the present invention is not limited thereto, any those skilled in the art can think variation, all should drop in protection scope of the present invention.
Claims (8)
1, the method for storage unit access in a kind of digital information processing system, being used to finish to the unit address data width is that the storage unit of N1 bit is carried out the visit of N2 bit, it is characterized in that, comprising:
(1) sets up the mapping relations of storage unit and logical space
A1: Q zone is set: first zone, second zone on logical space ... Q zone, wherein, Q=N1/N2;
A2: mapping relations are set up in a storage unit and a described Q zone: there are mapping relations in [N2 * (X-1), N2 * X-1] position of each address location of this storage unit, X ∈ [1, Q] with X of logical space regional corresponding address unit;
(2) when storage unit being carried out N2 bit when visit, judge earlier which regional X reference address is positioned at, then from [N2 * (X-1), N2 * X-1] position sense data/write data of storage unit corresponding address unit, wherein, N1＞N2.
2, the method for storage unit access in the digital information processing system as claimed in claim 1 is characterized in that,
Also comprise before the step a2: storage unit is divided into special access zone and generic access zone, and wherein, there are mapping relations one to one in each address location in generic access zone and an address location of logical space;
Storage unit is meant the special access zone of storage unit described in step a2, the step (2).
3, the method for storage unit access in the digital information processing system as claimed in claim 2, it is characterized in that, also comprise before the step a2: set in advance a zone bit, be used to identify the special access zone is carried out the visit of N2 bit or carried out the visit that instruction set is supported.
4, the method for storage unit access in the digital information processing system as claimed in claim 2, it is characterized in that, by two variablees of Low_add, High_add are set storage unit is divided into special access zone and generic access zone, wherein, be positioned at that [Low_add, storage unit High_add) is the special access zone.
5, the method for storage unit access in the digital information processing system as claimed in claim 4 is characterized in that, if when the memory capacity of storage unit is JKB, then
Among the step a1 first zone be [Low_add, High_add), second area be [Low_add+JKB, High_add+JKB) ... Q zone be [Low_add+JKB * (Q-1), High_add+JKB * (Q-1));
Among the step a2 each address location add in the special access zone of storage unit respectively with the X zone in add+JKB * (X-1) there are mapping relations one by one in the address, X ∈ [1, Q].
As the method for storage unit access in claim 1 or the 5 described digital information processing systems, it is characterized in that 6, wherein, N1 is 16, N2 is 8.
7, a kind of digital information processing system, being used to finish to the unit address data width is that the storage unit of N1 bit is carried out the visit of N2 bit, comprise DSP kernel, Memory Management Unit and storage unit, Memory Management Unit connects DSP kernel and storage unit respectively, it is characterized in that, Memory Management Unit also comprises mapping subelement and visit subelement, wherein
Described mapping subelement: there is corresponding relation in an address in each zone in Q the zone that each address location of storage unit sets in advance with logical space respectively, and the Q of storage unit and logical space sets up mapping relations in a zone: each address location of this storage unit [N2 * (X-1), N2 * X-1] there are mapping relations in the regional corresponding address unit of position and X of logical space, X ∈ [1, Q];
Visit subelement: connect the mapping subelement, be used to receive when storage unit carried out the order of N2 bit visit, judge earlier which regional X reference address is positioned at, then from [N2 * (X-1), N2 * X-1] position sense data of storage unit corresponding address unit/write data.
8, digital information processing system as claimed in claim 7, it is characterized in that, storage unit comprises special access zone and generic access zone, wherein, mapping is preserved in the subelement is the corresponding relation of address existence in each zone in Q zone setting in advance with logical space respectively of each address location in the special access zone of storage unit, and preserve the special access zone of storage unit and Q the mapping relations that the zone is set up of logical space, the visit subelement is [N2 * (X-1), N2 * X-1] position sense data/the write data from corresponding address unit, the special access of storage unit zone.
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| CN112363959B (en) * | 2021-01-14 | 2021-06-15 | 北京欣博电子科技有限公司 | Data addressing method, storage device, chip and data storage system |
| CN115827787B (en) * | 2023-02-15 | 2023-06-20 | 仁通融合(南京)信息技术有限公司 | Internet Yun Zhiku management method |
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| US5835973A (en) * | 1991-04-25 | 1998-11-10 | Kabushiki Kaisha Toshiba | Instruction processing unit capable of efficiently accessing the entire address space of an external memory |
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