JP2005044363A - Device and method for simultaneously processing two or more threads - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microprocessor. <P>SOLUTION: This application is characterized by that a memory space independent of respective threads in a process is allocated when a virtual memory is allocated to the process by this microprocessor. Independent allocation of a process memory space and a thread memory space to the process has effect capable of preventing problems of conflict of memories among the threads and protection of a program can be prevented, and particularly capable of relieving effort applied to memory management in programming by a programmer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to electronic circuit devices, and more particularly to microprocessors.

A microprocessor is a computer processor comprising a microchip and is also called a logic chip. A microprocessor is a type of “engine” that runs as soon as the computer is turned on. Microprocessors are designed to perform arithmetic and logical operations using very small storage elements called registers. Typical microprocessor operations include addition, subtraction, comparison of two numbers, and moving numbers from one place to another. Such operations are the result of executing an instruction set that is part of the microprocessor design. When the computer is activated, the microprocessor is designed to automatically execute the basic input / output system, ie, the first instruction (command) of the BIOS, which is then executed by the BIOS, OS, or application program. The microprocessor operates by providing instructions.
With the development of semiconductor process technology, the number of transistors that can be realized per unit area has increased geometrically. This gradually complicates the circuit implemented on the chip. Such a phenomenon also occurs in the microprocessor field, and the microprocessor is gradually becoming a more complicated structure.

  As the amount of data processed by the microprocessor increases, the processing speed also becomes an important performance factor of the microprocessor. Various methods have been studied to improve the processing speed of the microprocessor. A 5-stage pipeline, a super scaler, a virtual memory address, an internal cache, and the like are techniques for improving the processing speed of the microprocessor. In particular, recently, the SMT (simultaneous-multi-thread) technology that attempts to execute two or more programs, that is, two or more processes, on a single CPU without performance degradation improves the processing speed of the microprocessor. Used as a technology for

  Many microprocessors have a virtual memory space and a virtual memory address in order to use the memory efficiently. In a microprocessor supporting virtual memory, a virtual memory address and a physical memory address have different meanings. The virtual memory address is an address area referred to by a program or a programmer, and the physical memory address is a memory address space for accessing an actual main memory.

  In a conventional microprocessor, one process has one virtual memory space. For example, in the case of a 32-bit microprocessor, one process has one virtual memory space of up to 4 GB (Giga Byte). The virtual memory space is mapped to the physical memory space using an address conversion table for converting virtual memory addresses into physical memory addresses. That is, the virtual page number is converted into a physical page number through the address conversion table, and an actual memory is accessed. Such a conversion technique is used not only by a microprocessor that does not support SMT but also by a microprocessor that realizes SMT.

  A typical address translation table includes an address translation reference buffer (TLB).

  1A and 1B are diagrams illustrating conversion of a virtual memory address to a physical memory address using a conventional address translation reference buffer. FIG. 1A illustrates address conversion when a process identification number (Process ID) is included, and FIG. 1B illustrates address conversion when a process identification number (Process ID) is not included. The process identification number may be expressed by an address space number (ASN).

  In FIG. 1A, the virtual memory address includes a process identification number (process ID), a virtual page number (virtual page number), and a page offset (page offset). In FIG. 1B, there is no process identification number, and a virtual memory address is configured only by a virtual page address and a page offset.

  When converting from a virtual memory address to a physical memory address, the conversion is usually performed in units of 4K bytes for conversion efficiency. In this case, the entire virtual memory address is not converted into the entire physical memory address, but only the upper virtual page number (or the process identification number is included) is converted into the physical page number. Then, the conversion between the virtual page and the physical page is not executed, but is passed through as it is.

  2A and 2B show the structure of an address translation reference number in the prior art, FIG. 2A shows a case where a process identification number is included, and FIG. 2B shows a case where a process identification number is not included. A conventional address translation reference buffer is roughly divided into a tag (tag) and data (data).

  2A and 2B, the address translation reference buffer tag is composed of a process identification number, a virtual memory page buffer, a page offset, V (valid), and L (lock), and data is a physical page number and access permission. It consists of protection information like

  The operation of the address translation reference buffer configured as described above is as follows. If the input process identification number and the virtual memory page number match the contents of the tag held in the address translation reference buffer and match, and V has a valid value, the physical of the input (entry) The memory page number and protection information are output.

  In SMT, these processes can be composed of multiple threads so that multiple processes or multiple threads are executed simultaneously on one CPU. In the case of a microprocessor that has realized SMT to date, it is possible to cause a single CPU to simultaneously execute a number of processes using a memory management unit (MMU) or an address translation reference buffer. However, when a single process having a large number of threads is executed in an SMT environment, many problems such as protection problems between threads are caused.

  When a microprocessor executes one program, there is one upper process, and a number of lower processes can be placed in the upper process. In such a case, there are the following problems. First, the lower process is a process completely independent of the upper process, has an independent memory space, and is executed independently. That is, it is the same as executing completely different programs together. If communication between the two is necessary, communication can be performed only through a file on the hard disk or an OS kernel. Thus, communication between them is very slow and inefficient. Therefore, it is impossible to directly access each other's memory area.

When one program is executed by the microprocessor, there is one process, and the program can be executed with a structure having a large number of threads in the process. In this case, all threads within a process can use not only the memory together, but also all the resources of the process. Further, when communication between threads is necessary, it is also possible to directly access the other party's memory, so that data can be processed very quickly and efficiently. However, since the threads use the memory together, a protection problem may occur. In addition, since the programmer must be responsible for memory management by thread generation, there is a problem in that much effort is required for efficient memory management at the programming stage.
Richard L. Sites, Richard T. Witek, “Alpha AXP Architecture Reference Manual, Second Edition”, Copyright (C); 1995 Butterworth-Heinemann, Order number: EY-T132E-DP II-A / 3-12p., II- B / 3-9p. “ARM Architecture Reference Manual,” june 2000, ARMDDI0100E, “Chap.B6 Fast Context Switch Extension.”

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a microprocessor capable of high-speed communication between threads in a process and minimizing a memory management burden on a programmer. And

  In order to achieve the above object, according to the present invention, in a microprocessor that processes a plurality of processes simultaneously, one process memory space is allocated to each of the processes, One thread memory space is allocated to each thread, and the thread memory space is a memory space independent of the process memory space.

  In a preferred embodiment, the thread memory space is a memory space independent of each other, and the process memory space is commonly used by threads belonging to the process.

  The above object is to allocate a virtual memory to a microprocessor that simultaneously processes a large number of processes, in which a process memory space is allocated to each process, and threads in each process are allocated to each process. Each thread memory space can be allocated so that the thread memory space is independent of the process memory space.

  In a preferred embodiment, the thread memory space is a memory space independent of each other, and the process memory space is commonly used by threads belonging to the process.

  The object includes a tag portion including a thread identification number and a virtual memory page number, and a data portion including a physical memory page number, and determining the data portion corresponding to the tag portion to thereby determine a virtual memory address. Can be achieved by utilizing an address translation reference buffer characterized by mapping to a physical memory address.

  According to the present invention, when allocating memory to one process, an independent memory space is allocated to threads in the process, and a process memory space that can be commonly accessed and shared by each thread is allocated. As a result, it is possible to prevent memory collision between threads and the problem of program protection.

  In addition, there is an effect that it is possible to reduce the labor that a programmer spends on memory management during programming.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings according to the present invention, the same reference numerals are used for components having substantially the same configuration and the same function.

  The present invention provides a memory structure that can prevent various problems that may occur when a process is composed of a large number of threads and the threads are executed simultaneously.

  FIGS. 3 and 4 are views for explaining a method of allocating memory space to one process according to a preferred embodiment of the present invention. FIG. 3 shows a case where a single thread belongs to one process (single-process). FIG. 4 is a diagram illustrating a memory structure when a plurality of threads belong to one process (single-process multiple-thread).

  In the preferred embodiment of the present invention, one process has a process memory space and a thread memory space independent of the process memory space. Referring to FIG. 3, a process having one thread is assigned one process memory space VP10 and one thread memory space VT10 independent of the process memory space VP10.

  Referring to FIG. 4, one process memory space VP10 and n thread memory spaces VT10 to VTn0 for each thread are allocated to a virtual memory space for a process having n threads.

  The process memory space VP10 is a memory space that can be accessed by all n threads, and is mainly used for transmission / reception of messages / parameters / global data. The n thread memory spaces VT10 to VTn0 are memory spaces in which each thread is executed independently.

  The n thread memory spaces VT10 to VTn0 are independent of the process memory space VP10 and the virtual memory space. Also, the n thread memory spaces VT10 to VTn0 are virtual memory spaces that are independent from each other. These memory spaces are independent of each other and cannot be accessed or read from each other. When it is necessary to communicate between threads, the process memory space VP10 must be used. Each thread is allocated all the resources of the process as it is, and can use it freely.

  5A and 5B are diagrams for explaining a method of converting a virtual memory address to a physical memory address according to a preferred embodiment of the present invention, and FIGS. 6A and 6B are diagrams according to a preferred embodiment of the present invention. It is drawing which shows the structure of an address translation reference buffer.

  5A and 6A show a case where a process identification number is used, and FIGS. 5B and 6B show a case where a process identification number is not used.

  Referring to FIGS. 5A and 6A, in the address translation reference buffer according to the preferred embodiment of the present invention, the tag portion includes a process identification number, a thread identification number, a thread bit T, a virtual memory page number, a page offset, and V (Valid ), L (lock), and the data portion includes a physical memory page number and protection information.

  The thread identification number indicates the identification number of a currently generated thread. For example, when the thread identification number is composed of 3 bits, the maximum number of threads that can be generated by one process is eight.

  The thread bit (T bit) is used to identify whether the memory address to be currently converted is a memory address in the process memory space or a memory address in the thread memory space. When the thread bit (T bit) is 0, the process memory space is used, and when the thread bit (T bit) is 1, the thread memory space with which the current thread matches is used. That is, when the thread bit (T bit) is 1, the thread identification numbers are compared, and when it is 0, no comparison is made. Through this, if the thread bit is 1, the thread is executed in the thread memory space and is separate from other threads, has an independent memory space, and if the thread bit is 0, the process memory space is Use to communicate data / messages / parameters etc. between threads.

  Referring to FIG. 7, when the T bit is 1, a thread operation is performed in the thread memory space to generate a memory space. The generated memory space is independent of other threads. Also, when the T bit is 0, the thread uses processor memory space to transmit data, messages, parameters and / or information associated therewith.

  The thread identification number and the thread bit can be a part of the virtual memory address, or can be realized separately by a separate register. For example, virtual memory addresses such as a thread identification number (3 bits), a thread bit (1 bit), a process identification number (8 bits), a virtual memory page number (40 bits), and a page offset (12 bits) may be realized by a 64-bit device. In a 32-bit device, a thread identification number (3 bits), a thread bit (1 bit), and a process identification number (8 bits) are realized by separate registers, such as a virtual memory page number (20 bits) and a page offset (12 bits). Virtual memory addresses can also be realized.

  Here, the thread bit can be set to 0 or 1 through a separate instruction, or can be set in a part of the virtual memory address and classified according to the address.

  The configuration and operation of the circuit according to the present invention have been illustrated in accordance with the above description and the drawings. However, this is merely described by way of example, and various modifications can be made without departing from the technical idea and scope of the present invention. Of course, changes are possible.

6 is a diagram illustrating conversion of a virtual memory address into a physical memory address using a conventional address conversion reference buffer. 6 is a diagram illustrating conversion of a virtual memory address into a physical memory address using a conventional address conversion reference buffer. 6 is a diagram illustrating a structure of a conventional address translation reference buffer. 6 is a diagram illustrating a structure of a conventional address translation reference buffer. 3 is a diagram illustrating a method for allocating memory space to one process according to a preferred embodiment of the present invention. 3 is a diagram illustrating a method for allocating memory space to one process according to a preferred embodiment of the present invention. 3 is a diagram for explaining a method of converting a virtual memory address into a physical memory address according to an exemplary embodiment of the present invention; 3 is a diagram for explaining a method of converting a virtual memory address into a physical memory address according to an exemplary embodiment of the present invention; 3 is a diagram illustrating a configuration of an address translation reference buffer according to a preferred embodiment of the present invention. 3 is a diagram illustrating a configuration of an address translation reference buffer according to a preferred embodiment of the present invention. FIG. 3 is a flow chart of an address translation reference buffer according to a preferred embodiment of the present invention.

Explanation of symbols

VP10 process memory space VP10 to VPn0 thread memory space PA physical memory space

Claims (19)

In a microprocessor that processes multiple processes simultaneously,
At least one process memory allocated to a plurality of processes;
A plurality of thread memories respectively allocated to a plurality of threads in the plurality of processes;
The microprocessor according to claim 1, wherein the plurality of thread memories are independent of the process memory.   The microprocessor according to claim 1, wherein each of the plurality of thread memories is assigned to a corresponding thread.   The microprocessor of claim 1, wherein the process memory is used by a plurality of threads. In a method of allocating virtual memory in a microprocessor that processes a plurality of processes simultaneously,
Allocating process memory to multiple corresponding processes;
Allocating thread memory to threads in a plurality of corresponding processes,
A method of allocating virtual memory in a microprocessor, wherein the thread memory is independent of the process memory.   The method of claim 4, wherein each of the thread memories is assigned to a corresponding thread.   The method of claim 4, wherein the process memory is used by the thread. In the conversion reference buffer of the microprocessor,
A tag unit including a thread ID and a virtual memory page number;
A conversion reference buffer for a microprocessor, comprising: a data unit including a physical memory page number, the data unit corresponding to the tag unit and used for converting a virtual memory address into a physical memory address.   The microprocessor conversion reference buffer according to claim 7, wherein the tag unit includes a process ID.   8. The conversion reference buffer according to claim 7, wherein the tag unit includes a thread bit for determining whether the virtual memory address is an address of a process memory or a thread memory. Process memory corresponding to a process having at least one thread;
A thread memory that is independent of the process memory and that corresponds to the at least one thread;
The apparatus, wherein the process and the at least one thread access the process memory. Including virtual memory with at least one process memory and at least two thread memories;
The apparatus wherein each of the at least two thread memories corresponds to a separate thread and is independent of the at least one process memory.   12. The thread memory is accessed only by the at least one process memory without accessing another thread memory, and the thread memory is accessed only by the at least one process memory. Equipment.   The apparatus of claim 11, wherein the thread memory accessed by the at least one process memory includes a read operation.   12. The apparatus of claim 11, wherein the at least one process memory is used by another one of the two threads to access one of the at least two threads.   The apparatus of claim 13, wherein the at least one process memory is used by one of the at least two threads to access any one of the plurality of threads. In a method for allocating virtual memory,
Allocating at least one process to process memory;
Allocating at least one thread in the process to a thread memory, wherein the thread memory is independent of the process memory. In a method of converting a virtual memory address to a physical memory address,
Determining the value of the thread bit;
Performing an operation in a thread memory or a process memory according to the determined thread bit value.   The address conversion method of claim 17, wherein the determined thread bit value is determined by executing a thread operation, and the thread operation is executed in a corresponding thread memory.   The address of claim 17, wherein the determined thread bit value is due to performing an operation using the process memory to transmit at least one of data, a message, or a parameter. Conversion method.

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