CN117369830A - Binary translation method, electronic device, and readable storage medium - Google Patents
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Abstract
The embodiment of the invention provides a binary translation method, electronic equipment and a storage medium, wherein the method comprises the following steps: in the process of translating the precursor basic block, translating a combination of an operation instruction and a conditional jump instruction in a source instruction sequence of a first instruction set into a conditional jump instruction and a zone bit calculation instruction of a target instruction sequence of a second instruction set; and in the process of translating the subsequent basic blocks, if the flag bit generated by the source instruction sequence in the subsequent basic blocks covers the flag bit generated by the operation instruction in the precursor basic blocks, optimizing the flag bit calculation instruction in the target instruction sequence corresponding to the precursor basic blocks. According to the embodiment of the invention, the instruction optimization across basic blocks can be realized without translating the subsequent basic blocks in advance, the translation efficiency can be improved, the generation of redundant instructions in the binary translation process can be reduced, and the running efficiency of a translated program can be improved.
Description
The application is a divisional application of China patent application with the application number of 202310925338.7 and the name of binary translation method, binary translation device, electronic equipment and storage medium, which is filed by China patent office on the 26 th year of 2023.
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a binary translation method, an electronic device, and a readable storage medium.
Background
Binary translation may convert a source program running on one architecture platform to a target program running on another architecture platform to solve the problem of application running across instruction set architectures at the binary level. Binary translation is one of the research hotspots in the field of computer technology in recent years.
In the binary translation process, due to the difference of two architecture instruction sets, the difference of semantic expression levels of the instruction sets is caused, more redundant instructions can be possibly generated, the redundant instructions can be reduced through instruction optimization, and the efficiency of a translated program is improved.
Binary translation is performed in basic blocks (Translation Block, TB), instruction optimization is typically performed within a single basic block. Because there may be a dependency relationship between different basic blocks, it is necessary to translate the subsequent basic blocks of the dependency preamble in advance to achieve instruction optimization across basic blocks (between different basic blocks), but this will result in an increase of translation overhead and a decrease of translation efficiency.
Disclosure of Invention
In view of the foregoing, embodiments of the present invention are provided to provide a binary translation method that overcomes the foregoing problems or at least partially solves the foregoing problems, and can implement instruction optimization across basic blocks without translating subsequent basic blocks in advance, so as to improve translation efficiency.
Correspondingly, the embodiment of the invention also provides a binary translation method, electronic equipment and a storage medium, which are used for ensuring the realization and the application of the method.
In a first aspect, an embodiment of the present invention discloses a binary translation method, where the method includes: in the process of translating the precursor basic block, translating a combination of an operation instruction and a conditional jump instruction in a source instruction sequence of a first instruction set into a conditional jump instruction and a flag bit calculation instruction of a target instruction sequence of a second instruction set, wherein in the first instruction set, the operation instruction generates a flag bit in a flag bit register while generating an operation result, and in the second instruction set, the flag bit is generated by a single flag bit calculation instruction; and in the process of translating the subsequent basic block, if the flag bit generated by the source instruction sequence in the subsequent basic block covers the flag bit generated by the operation instruction in the preceding basic block, optimizing the flag bit calculation instruction in the target instruction sequence corresponding to the preceding basic block.
In a second aspect, an embodiment of the present invention discloses an electronic device, including: a processor; and a memory having computer executable instructions stored thereon that, when executed by the processor, cause the processor to perform the steps of the binary translation method of any of the preceding claims.
The binary translation method, the electronic device and the storage medium provided by the embodiment of the invention can identify and implement more deep optimization, can reduce the generation of redundant instructions (semantics) in the binary translation process, and can improve the running efficiency of the translated program.
Drawings
FIG. 1 is a flow chart of steps of an embodiment of a binary translation method of the present invention;
FIG. 2 is a schematic diagram of an architecture of a binary translation method of the present invention;
FIG. 3 is a schematic illustration of the translation and optimization process of example one of the present invention;
FIG. 4 is a block diagram of a binary translation apparatus embodiment of the present invention;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present invention may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, the term "and/or" as used in the specification and claims to describe an association of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The term "plurality" in embodiments of the present invention means two or more, and other adjectives are similar.
Binary translation may be used to solve the problem of binary-level applications running across instruction set architectures (Instruction Set Architecture, ISA). In particular, binary translation techniques may translate sequences of instructions in one instruction set architecture into sequences of instructions in another instruction set architecture. For example, binary translation may translate instruction sequences in an x86 instruction set architecture into instruction sequences in an arm instruction set architecture (e.g., arm 64), and vice versa. Binary translation includes both static translation and dynamic translation. Static translation is the translation of binary A on the source platform to translate the binary A into binary file B on the target platform prior to its execution. Based on the static translation technology, the translation result obtained by one translation can be used for a plurality of times. Dynamic translation is the translation of fragments that are executed when a binary is run. The binary translation method of the embodiment of the invention can be applied to dynamic translation, and the translation is performed by taking basic blocks as units. A basic block typically ends with control flow change instructions (e.g., jumps, function calls, etc.).
In the embodiment of the present invention, the source program refers to a program to be binary translated, and the source program may be any type of application program. A source platform refers to a machine platform that can run a source program. In some embodiments, the source platform may also be referred to as a client. The processor of the source platform may be a processor based on a first instruction set architecture. The first instruction set architecture may be, for example, an x86 instruction set architecture or an arm instruction set architecture (e.g., arm 64). The source program is a program developed based on the first instruction set architecture, and thus, the source program can be normally run on the source platform. The target platform is a machine platform where migration of source programs is desired. In some embodiments, the target platform may also be referred to as a host. The processor of the target platform may be a processor based on a second instruction set architecture. The second instruction set architecture is a different instruction set architecture than the first instruction set architecture. For example, the first instruction set architecture is the x86 instruction set architecture and the second instruction set architecture is the arm instruction set architecture. As another example, the first instruction set architecture is an arm instruction set architecture and the second instruction set architecture is an x86 instruction set architecture. For another example, the first instruction set architecture is the x86 instruction set architecture and the second instruction set architecture is the LoongArch architecture. The source program may run on the source platform using source binary code. The source binary code is code based on a first instruction set architecture. If it is desired to run the source program on the target platform, the source binary needs to be translated into target binary. The target binary is code based on the second instruction set architecture such that the target binary can be run on the target platform.
FIG. 1 shows a flow chart of steps of an embodiment of a binary translation method of the present invention, which may include the steps of:
step 101, translating the precursor basic block and determining an uncertain optimization instruction existing in the translated precursor basic block; the uncertain optimization instruction indicates that the optimization condition of the instruction can be determined whether the optimization condition can be met or not in the process of translating the subsequent basic block;
102, recording relevant information of the uncertain optimization instruction; the related information comprises optimization conditions of the uncertain optimization instruction;
step 103, in the process of translating the subsequent basic block, if the optimization condition is determined to be met, optimizing the uncertain optimization instruction in the preamble basic block.
The binary translation method provided by the embodiment of the invention can be applied to a dynamic translation scene, and the instructions are optimized in the translation process, so that the generation of redundant instructions is reduced as much as possible, and the running efficiency of a translated program is improved.
Referring to fig. 2, a schematic diagram of an operation architecture of a binary translation method according to an embodiment of the present invention is shown. As shown in FIG. 2, the binary translation architecture of an embodiment of the present invention includes a disassembler, an optimizer, a translator, and an assembler. Firstly, inputting a source program into a disassembler for disassembly, cutting the source program into basic blocks, and acquiring information of each instruction in each basic block; the optimizer analyzes the disassembled information, finds out possible instructions to be optimized in the information and marks the instructions; the translator translates each instruction correspondingly according to the disassembled information, and optimizes the translation process with the help of the marking information provided by the optimizer; the final optimized translated instructions are fed into an assembler for assembly. Wherein the instructions to be optimized include determinable instructions to be optimized that exist in a single basic block, and further include uncertain optimization instructions across basic blocks that are temporarily unable to determine whether optimizable.
In the binary translation process, due to the difference of two architecture instruction sets, the difference of the semantic expression level of the instruction sets is caused, more redundant instructions can be generated, and therefore the efficiency of a translated program is affected. The embodiment of the invention optimizes the instructions in the binary translation process, and particularly can realize the instruction optimization across basic blocks on the premise of not translating the subsequent basic blocks in advance, so as to reduce redundant instructions and improve the efficiency of the translated program.
The preceding basic block and the following basic block are in relative terms, for example, basic block 1 is translated, basic block 2 is translated, basic block 3 is translated, and basic block 1 is a preceding basic block of basic block 2, basic block 1 may also be a preceding basic block of basic block 3, basic block 2 is a following basic block of basic block 1, basic block 3 may also be a following basic block of basic block 1, and basic block 3 is also a following basic block of basic block 2, in order of instruction stream.
In translating basic block 1, basic block 1 may be referred to as a leading basic block, or may be referred to as a current basic block. In the embodiment of the invention, in the process of translating an instruction sequence of a first instruction set architecture in a preamble basic block into an instruction sequence of a second instruction set architecture, analyzing the translated instruction, judging whether an uncertain optimization instruction exists, and if so, recording the related information of each uncertain optimization instruction; the relevant information includes, but is not limited to, optimization conditions of the uncertain optimization instruction. The optimization condition of the uncertain optimization instruction is used for representing a temporarily indeterminate reason for judging whether the uncertain optimization instruction can be optimized. The optimization conditions include, but are not limited to, data that is dependent on or required by the uncertain optimization instruction to be generated by a subsequent basic block.
For example one, assume that the instruction sequence in a leading basic block (e.g., basic block 1) that includes a first instruction set architecture (e.g., X86 instruction set) is as follows:
CMP A,B
Jcc C
the instruction sequence includes two instructions, which will be referred to as "CMP+JCC" instruction sequence for convenience of description. Wherein CMP is a compare instruction, jcc is a conditional jump instruction, and the semantics of the "CMP+jcc" instruction sequence are: comparing two operands in the CMP instruction, and if the comparison result meets the jump condition set by the Jcc instruction, jumping to the position indicated by C. Assume that the instruction sequence for translating the "CMP+JCC" instruction sequence into a second instruction set architecture (e.g., loongArch instruction set) is as follows:
Bcc A,B,C
CMP EFLAGS
in the translation process, the CMP+JCC instruction sequence can be translated into a conditional jump instruction Bcc of a LoongArch instruction set according to semantics so as to complete corresponding conditional jump actions. However, the X86 instruction set defines an independent operand tag register EFLAGS that is updated by the instruction while the result value is being generated, and the conditional jump instruction performs a jump determination based on the value of EFLAGS. In the X86 instruction set, in addition to generating an operation result, one operation also generates a plurality of flags such as carry, overflow, etc. However, the LoongArch instruction set does not carry out calculation of EFLAGS like X86, so that during translation, additional EFLAGS calculation instructions (such as the Bcc instruction described above and added with a "CMP EFLAGS" calculation instruction) are required to simulate the EFLAGS information generation process of X86 to obtain correct EFLAGS information, so as to ensure that the translated instruction sequence is consistent with the semantics of the instruction sequence before translation.
The "CMP EFLAGS" computing instruction has a dependency relationship with the subsequent basic block, and it is required to determine whether the "CMP EFLAGS" computing instruction can be optimized according to whether the subsequent basic block will use the computing result of the "CMP EFLAGS" computing instruction. For example, if during the computation of the subsequent basic block, the computation result of the "CMP EFLAGS" computation instruction would be overwritten by the computation result of other instructions in the subsequent basic block, then it is indicated that the "CMP EFLAGS" computation instruction at this time is redundant, that is, the optimization condition of the "CMP EFLAGS" computation instruction is satisfied, and the "CMP EFLAGS" computation instruction may be optimized (e.g., the "CMP EFLAGS" computation instruction is eliminated); if the computation of other instructions in the subsequent basic block requires the computation result of the "CMP EFLAGS" computation instruction, then the optimization condition of the "CMP EFLAGS" computation instruction is not satisfied, and the "CMP EFLAGS" computation instruction requires reservation and cannot be optimized.
Thus, for example one, after translation of a precursor basic block (e.g., basic block 1), it may be determined that an uncertain optimization instruction (e.g., a "CMP EFLAGS" calculation instruction) is present in the translated precursor basic block and relevant information for the uncertain optimization instruction, including the optimization conditions for the uncertain optimization instruction, is recorded. For example, the optimization condition of the uncertain optimization instruction may be recorded as "no subsequent basic block is used CMP EFLAGS", i.e., "CMP EFLAGS" if the calculation instruction can be optimized depends on whether the subsequent basic block will use the calculation result of "CMP EFLAGS" calculation instruction.
In the process of translating the subsequent basic blocks, the recorded optimization conditions of the uncertain optimization instructions of the preamble basic blocks can be scanned, and whether the recorded optimization conditions are met or not is judged; if satisfied, the corresponding uncertain optimization instruction may be optimized. Illustratively, assuming that the subsequent basic block does not use the calculation result of the uncertain optimization instruction in the preceding basic block, the uncertain optimization instruction is described as a redundant instruction, and the optimization condition of the uncertain optimization instruction is satisfied, the uncertain optimization instruction may be optimized, such as the uncertain optimization instruction is eliminated.
According to the embodiment of the invention, the related information of the instructions (uncertain optimization instructions) which can not be determined whether to optimize temporarily in a single basic block can be recorded through an optimization algorithm crossing the basic block, and whether the uncertain optimization instructions can be optimized is dynamically confirmed in a subsequent translation process. In the embodiment of the invention, only the related information of the uncertain optimization instructions in the translated precursor basic blocks is required to be recorded in the binary translation process, the follow-up basic blocks are not required to be translated in advance, and whether the uncertain optimization instructions can be optimized or not is dynamically confirmed in the follow-up translation process, and if so, the corresponding optimization actions are executed, so that the optimization of the precursor basic blocks is completed. The embodiment of the invention reduces the expenditure of the translator, and can accurately identify and complete the executable instruction optimization across basic blocks.
In a specific implementation, for a certain subsequent basic block, there may be several uncertain optimization instructions in a certain or several preceding basic blocks on which it depends. Further, in the process of translating the preamble basic block, if it is determined that the uncertain optimization instruction exists in the preamble basic block, location information of the uncertain optimization instruction can be recorded, that is, the related information can also include location information of the uncertain optimization instruction, so that in the process of translating the following basic block, when it is determined that the optimization condition of the uncertain optimization instruction of the preamble basic block is met, the uncertain optimization instruction can be located according to the recorded location information, and the uncertain optimization instruction at the location information can be optimized.
In an alternative embodiment of the present invention, the translation precursor basic block may include:
step S11, matching the instruction sequence in the preamble basic block with the translation templates in the translation template library to obtain matched translation templates; if the translation template contains an uncertain optimization instruction, the translation template comprises a preset domain, wherein the preset domain is used for recording the uncertain optimization instruction and related information contained in the translation template;
And step S12, translating the instruction sequence in the precursor basic block based on the matched translation template.
The translation template is a preset instruction sequence conforming to a specific rule. Specifically, the translation template may translate the instruction sequence of the first instruction set architecture into the instruction sequence corresponding to the second instruction set architecture, where the operands in the translation template are abstract operands (e.g., A, B and C in table 1) and do not represent real values. That is, the translation template is a translation rule, and the instruction sequence conforming to the translation template can be translated according to the rule of template translation.
The instruction sequence can be translated in whole based on the translation template, rather than translating the instructions one by one. The translation template is utilized for translation, so that the integral translation of the instruction sequence can be realized, the optimization of the instruction on the semantic level is realized in the translation process, and redundant instructions are reduced on the premise of keeping the semantics unchanged. Instructions within a single basic block may be optimized during translation using translation templates. Further, the embodiment of the invention maintains the related information of the uncertain optimization instruction contained in the translation template, and further, in the translation process, the related information of the uncertain optimization instruction of the basic block can be obtained by utilizing the matched translation module, so that the instruction optimization across the basic block can be realized.
In one example, a translation template is shown in Table 1:
TABLE 1
The rule of the translation template is to translate the two instructions of CMP A, B and JCC into the two instructions of Bcc A, B, C and CMP EFLAGS, and the semantics of the translation are the same. The pre-translated instructions may be instructions of a first instruction set architecture and the post-translated instructions may be instructions of a second instruction set architecture. In addition, the translation template also records the uncertain optimization instructions and related information contained in the translation template. The translation template comprises a preset field, and the preset field can comprise two parts, one part is used for recording the uncertain optimization instruction contained in the translation template, and the other part is used for recording the related information of the uncertain optimization instruction, such as the optimization condition of the uncertain optimization instruction.
The translation template is pre-constructed, and the related information of the uncertain optimization instruction contained in the translation template can be maintained in the translation template when the translation template is constructed, so that the related information of the uncertain optimization instruction can be obtained through the matched translation template in the process of carrying out matched translation by utilizing the translation template, and the optimization efficiency can be improved without carrying out online analysis.
It will be appreciated that the translation templates described above are merely illustrative, and embodiments of the present invention are not limited to the specific content of the translation templates.
The determining the uncertain optimization instruction existing in the translated preamble basic block may include: if the matched translation template comprises a preset domain, determining an uncertain optimization instruction and related information contained in a precursor basic block translated based on the matched translation template through the preset domain.
In example one, in the process of translating the precursor basic block (e.g., basic block 1), each instruction sequence in basic block 1 may be matched with a translation template in the translation template library, so that the matched translation template shown in table 1 may be queried. The instruction sequence in the basic block 1 can be translated by using the matched translation template, and the related information of the uncertain optimization instruction can be obtained and recorded from the preset domain of the matched translation template.
The embodiment of the invention does not limit the position of the related information of the uncertain optimization instruction. Illustratively, the relevant information of the uncertain optimization instruction can be recorded in an information field of the basic block, a tail of the basic block, and the like, and can be obtained by indexing at any time. For example, for basic block 1, the relevant information of the uncertain optimization instruction in basic block 1 may be recorded in the information field of basic block 1. Each basic block has its own information field which can be used to record basic information of the basic block, such as basic block size, start address, etc. The embodiment of the invention also records the related information of the uncertain optimization instruction in the information field of the basic block without additionally creating a storage space.
In an alternative embodiment of the present invention, the uncertain optimization instruction may be a flag bit calculation instruction generated when an instruction sequence including a conditional jump instruction is translated, where the conditional jump instruction corresponds to two different exits, one of the exits points to a jump position corresponding to when a jump condition is satisfied, and the other of the exits points to a jump position corresponding to when the jump condition is not satisfied, and the two different exits respectively correspond to respective flag bit calculation instructions.
Taking an example one as an example, the Jcc instruction in the basic block 1 is taken as a conditional jump instruction, where the Jcc instruction corresponds to two different outlets, one outlet points to a corresponding jump position when the jump condition is met, and the other outlet points to a corresponding jump position when the jump condition is not met. When the "cmp+jcc" instruction sequence is translated into the conditional jump instruction Bcc, the flag calculation instruction "CMP EFLAGS" is generated. The conditional jump instruction Bcc corresponds to two different outlets, one outlet points to the corresponding jump position when the jump condition is met, the other outlet points to the corresponding jump position when the jump condition is not met, and the two different outlets respectively correspond to the respective zone bit calculation instructions.
Illustratively, two outlets corresponding to the conditional jump instruction Bcc are respectively denoted as outlet 1 and outlet 2, the outlet 1 points to a corresponding jump position when the jump condition is satisfied, and the outlet 2 points to a corresponding jump position when the jump condition is not satisfied. Outlet 1 and Outlet 2 correspond to respective flag bit calculation instructions "CMP EFLAGS", respectively.
Suppose that exit 1 points to the first instruction (e.g., or instruction) in basic block 2, exit 2 points to the first instruction (e.g., sbb instruction) in basic block 3. Both the basic block 2 and the basic block 3 are subsequent basic blocks of the basic block 1, the first instruction in the basic block 2 is a position to which the Bcc instruction jumps when the jump condition is satisfied, and the first instruction in the basic block 3 is a position to which the Bcc instruction jumps when the jump condition is not satisfied (i.e., a next instruction of the Bcc instruction).
Assuming that the optimization condition of the uncertain optimization instruction "CMP EFLAGS" at the exit 1 of the conditional jump instruction Bcc in the basic block 1 is satisfied in the process of translating the basic block 2, the uncertain optimization instruction "CMP EFLAGS" at the exit 1 of the conditional jump instruction Bcc in the basic block 1 can be optimized. Assuming that the optimization condition of the uncertain optimization instruction "CMP EFLAGS" at the exit 2 of the conditional jump instruction Bcc in the basic block 1 is determined not to be satisfied in the process of translating the basic block 3, the uncertain optimization instruction "CMP EFLAGS" at the exit 2 of the conditional jump instruction Bcc in the basic block 1 may be reserved without optimization.
It should be noted that, the embodiment of the present invention does not limit the type of the uncertain optimization instruction. The uncertain optimization instruction and the subsequent basic block have a dependency relationship, so that whether the uncertain optimization instruction can be optimized cannot be determined temporarily, whether the uncertain optimization instruction in the preceding basic block can be optimized can be judged in the process of translating the subsequent basic block, and then the optimization mode is determined and optimized.
In particular implementations, the flag bit (EFLAGS) calculation instruction generated by the instruction sequence of the "XX+JCC" type during translation can be used as an uncertain optimization instruction. The XX instruction refers to an instruction that generates an EFLAGS calculation instruction, such as a CMP instruction, a TEST instruction, etc. In addition, EFLAGS calculation instructions generated by ADD instructions, SUB instructions, etc. may also be used as uncertainty optimization instructions. It will be appreciated that in addition to these main semantics enumerated above, instructions whose other semantics may be covered by subsequent basic blocks may all be used as uncertain optimization instructions.
In an alternative embodiment of the present invention, the optimization conditions may include: the instructions in the subsequent basic blocks override the calculation results of the uncertain optimization instructions.
Example two, assume that the instruction sequence in a leading basic block (e.g., basic block 1) that includes a first instruction set architecture (e.g., X86 instruction set) is as follows:
IDIV A
SUB B,EDX
The instruction sequence comprises two instructions, and the meaning expressed by the instruction sequence is as follows: splicing two 32-bit numerical values of an X86 register EDX and an EAX together to form a 64-bit number, dividing the 64-bit number by A, putting the result into the EAX, and putting the remainder into the EDX; the values of B and EDX are subtracted and the result is put into EDX. Assume that the instruction sequence for translating the instruction sequence into a second instruction set architecture (e.g., the LoongArch instruction set) is as follows:
DIV EAX, EDX: EAX, A// EDX: EAX/A results EAX
MOD EDX, EDX: EAX, A// EDX: EAX/A remainder EDX
SUB EDX, B, EDX// B-EDX results EDX
Wherein, the uncertain optimization instruction is 'DIV EAX, EDX: EAX, A', and the optimization condition of the uncertain optimization instruction is 'subsequent basic block coverage EAX result'.
It should be noted that, in the embodiment of the present invention, the instruction sequence "cmp+jcc" is mainly described as an example, and other optimization processes that can generate the instruction sequence of the uncertain optimization instruction are similar and may be referred to each other.
If the instruction in the subsequent basic block will override the calculation result of the uncertain optimization instruction in the preceding basic block, it is stated that the subsequent basic block will not use the calculation result of the uncertain optimization instruction in the preceding basic block (e.g. EFLAGS information calculated by the "CMP EFLAGS" instruction), that is, for the subsequent basic block, the uncertain optimization instruction in the preceding basic block is a redundant instruction, and the optimization condition of the uncertain optimization instruction is satisfied, so that optimization can be performed.
In an alternative embodiment of the present invention, the optimizing the uncertain optimization instruction in the preamble basic block may include: the uncertain optimization instruction in the preamble basic block is set to a null instruction.
Instructions in subsequent basic blocks, if they would override the calculation of the uncertain optimization instructions in the preceding basic blocks, indicate that the uncertain optimization instructions are redundant instructions and therefore eliminate the uncertain optimization instructions, e.g. the uncertain optimization instructions may be set to null instructions (e.g. nop instructions). The nop instruction is a null operation, and the nop instruction does not perform any action so as to improve the efficiency of the translated program.
In an alternative embodiment of the present invention, the optimizing the uncertain optimization instruction in the preamble basic block may include: and when the re-translation overhead meets the preset condition, re-translating the uncertain optimized instruction and the subsequent instructions in the preamble basic block.
In a specific implementation, the optimizing manner of re-translation may be used in a case where the number of instructions to be optimized is large, for example, when optimizing the flag bit (EFLAGS) computing instruction, if the number of EFLAGS computing instructions is small (for example, less than the preset number), an optimizing manner modified into a nop instruction is preferably adopted; if the number of EFLAGS calculation instructions is large (e.g., greater than a predetermined number), then the optimization of the re-translation is preferred. Further, when the cost of re-translation meets the preset condition, for example, the cost caused by re-translation is smaller than the benefit caused by re-translation, the optimization mode of re-translation is preferably adopted.
The embodiment of the invention does not limit the method for calculating the expense and benefit of the re-translation. Illustratively, embodiments of the present invention may provide the following calculation: assuming that the number of instructions to be re-translated is M, the cost of translating one instruction is T, the number of optimized instructions is N, the benefit of optimizing one instruction is O, the cost caused by re-translation is MT, and the benefit caused by re-translation is NO. The number of M and N can be obtained in the translation and optimization process, and T and O can be set in a preset mode, or T and O can be set in a detection mode at the starting time of the translator.
Further, setting T and O by way of probing may include: at the starting time of the translator, calculating the time for translating a plurality of instructions in a timing mode, and obtaining the overhead T of single instruction translation after averaging; meanwhile, the translated instruction can be run and timed, compared with the optimized time, the optimized benefit is obtained, and the benefit O of optimizing one instruction is obtained after averaging.
In an embodiment of the present invention, the optimizing manner of the re-translation may include re-translating the uncertain optimized instruction and the subsequent instruction. Further, the optimizing manner of the re-translation may further include re-translating the entire basic block where the uncertain optimizing instruction is located. It is understood that re-translating refers to re-translating the original instruction (the instruction before optimization), such as re-translating the original instruction of the uncertain optimized instruction and the following instructions, or re-translating the original instruction of the whole basic block.
In the case that the cost of re-translating the entire basic block is less than re-translating the uncertain optimization instruction and its subsequent instructions, it may be an option to re-translate the entire basic block. The optimal mode of re-translation can be determined according to actual requirements.
In implementations, the manner in which the uncertain-optimized instruction and its successor are re-translated may be employed in most cases. However, there are times when the overhead of re-translating the entire basic block is less, as re-translating subsequent instructions requires searching the location of the original instruction and finding the location of the translated instruction that needs to be modified, which can incur additional overhead. It is preferable to re-translate the entire basic block when the number of instructions that need to be re-translated exceeds a predetermined proportion, such as more than 3/4 of the number of instructions in the basic block. The preset proportion can be set according to actual requirements.
Example three, assume that the instruction sequence in a leading basic block (e.g., basic block 1) that includes a first instruction set architecture (e.g., X86 instruction set) is as follows:
COMISS A,B
Jcc C
the instruction sequence includes two instructions, which will be referred to as "COMISS+JCC" instruction sequence for convenience of description. The COMISS instruction is used for comparing the sizes of two floating point operands and setting EFLAGS information; the Jcc instruction jumps according to the EFLAGS information. However, EFLAGS computation of the COMISS instruction requires a large number of operation instructions, and therefore the "COMISS+JCC" instruction sequence translates into a second instruction set architecture (e.g., loongArch instruction set) as follows:
Bcc A,B,C
COMISS_ZF A, B// calculate COMISS instruction ZF bit
COMISS_PF A, B// calculate COMISS instruction PF bit
COMISS_CF A, B// calculate COMISS instruction CF bits
Wherein, "comiss_zf a, B", "comiss_pf a, B" and "comiss_cf a, B" are all uncertain optimization instructions, and assuming that the optimization conditions of the three uncertain optimization instructions are all satisfied, the three instructions "comiss_zf a, B", "comiss_pf a, B" and "comiss_cf a, B" may be set as nop instructions (no operation). However, this will result in a large number of unwanted nop instructions, and therefore the optimal way of re-translation may be chosen at this time. Re-translating the basic block to obtain the following instruction: bcc C, a, B.
In an alternative embodiment of the present invention, the method may further include: and if the optimization condition is not met in the process of translating the subsequent basic blocks, retaining the uncertain optimization instructions in the preamble basic blocks.
In translating the subsequent basic block, if an instruction in the subsequent basic block needs to use (i.e. depend on) the calculation result of the uncertain optimization instruction in the preceding basic block, which indicates that the optimization condition of the uncertain optimization instruction is not satisfied, the uncertain optimization instruction in the preceding basic block needs to be reserved and cannot be optimized.
Referring to FIG. 3, a schematic diagram of an exemplary one of the translation and optimization processes in accordance with an embodiment of the present invention is shown. As shown in fig. 3, for the basic block (e.g., basic block 1) of the preamble, the instruction sequence before translation is "cmp+jcc", the instruction sequence after translation is "bcc+eflags", and the flag bit calculation instruction "CMP EFLAGS" generated by translating "cmp+jcc" into a Bcc instruction is an uncertain optimization instruction, where the relevant information of the uncertain optimization instruction may be recorded (step (1)). And when the subsequent basic blocks are translated and the basic blocks are linked, the corresponding optimization is completed. The Bcc instruction corresponds to two outlets (e.g., outlet 1 and outlet 2), each of which corresponds to an EFLAGS calculation instruction.
It should be noted that, the optimization operation of the preamble basic block according to the embodiment of the present invention may be completed during the linking. When the subsequent basic block is translated and the basic block is linked, the related information of the uncertain optimization instruction of the recorded preamble basic block can be analyzed to judge whether the optimization condition of the uncertain optimization instruction is met, if so, the position of the uncertain optimization instruction is queried, the optimization mode of the uncertain optimization instruction is selected, such as setting as a null instruction (nop instruction), re-translating the uncertain optimization instruction and the subsequent instruction, re-translating the whole basic block, and optimizing according to the selected optimization mode to obtain an optimized instruction sequence.
As shown in fig. 3, the exit 1 points to the corresponding jump position when the jump condition is satisfied, and the exit 2 points to the corresponding jump position when the jump condition is not satisfied. Outlet 1 points to the first instruction (e.g., or instruction) in basic block 2, and Outlet 2 points to the first instruction (e.g., sbb instruction) in basic block 3.
In translating the basic block 2, the first instruction (or instruction) OF the basic block 2 is an or operation on the given two operands, and generates EFLAGS information according to the result, so the or instruction itself calculates all EFLAGS information (step (3)), which includes CF, PF, AF, ZF, SF and OF. Thus, the or instruction itself calculates EFLAGS information that will overwrite the EFLAGS information calculated by the uncertain optimization instruction (EFLAGS calculation instruction) at the exit 1 in the preamble basic block (basic block 1), it can be determined that the optimization condition of the uncertain optimization instruction at the exit 1 in the basic block 1 is satisfied, and the uncertain optimization instruction therein can be eliminated, as set as a nop instruction (step (3)). For basic block 3, the first instruction is an sbb instruction, which is a "borrow subtraction" instruction that requires an operation based on two operands in the instruction and CF bits, and generates EFLAGS information based on the operation result, so the sbb instruction requires CF bits of EFLAGS information calculated using an uncertain optimization instruction (EFLAGS calculation instruction) at exit 2 in basic block 1 (step (4)), and therefore the optimization condition of an uncertain optimization instruction at exit 2 in basic block 1 is not satisfied, and an uncertain optimization instruction there needs to be retained (step (5)).
It should be noted that, the code of the "exit portion" at the end of the basic block in fig. 3 is used to solve the problem that, without the basic block link, the code can exit to the translator correctly to perform the search of the next basic block.
In the example shown in fig. 3, the first instruction in the basic block 2 is an or instruction, and the first instruction in the basic block 3 is an sbb instruction, which are all exemplary.
In summary, according to the binary translation method provided by the embodiment of the invention, through the cross-basic-block optimization algorithm, the relevant information of the instructions (uncertain optimization instructions) which cannot be determined temporarily in a single basic block can be recorded, and whether the uncertain optimization instructions can be optimized is dynamically confirmed in the subsequent translation process. In the embodiment of the invention, only the related information of the uncertain optimization instructions in the precursor basic blocks is recorded in the binary translation process, the follow-up basic blocks are not required to be translated in advance, and whether the uncertain optimization instructions can be optimized or not is dynamically confirmed in the follow-up translation process, and if so, the corresponding optimization actions are executed, so that the optimization of the precursor basic blocks is completed. The embodiment of the invention reduces the expenditure of the translator, and can accurately identify and complete the executable instruction optimization across basic blocks. Further, the invention can identify and implement more deep optimization through a basic block crossing optimization algorithm, can reduce the generation of redundant instructions (semantics) in the binary translation process, and can improve the running efficiency of the translated program.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
Referring to FIG. 4, there is shown a block diagram of an embodiment of a binary translation apparatus of the present invention, the apparatus comprising:
a translation determining module 401, configured to translate the preamble basic block and determine an uncertain optimization instruction existing in the translated preamble basic block; the uncertain optimization instruction indicates that the optimization condition of the instruction can be determined whether the optimization condition can be met or not in the process of translating the subsequent basic block;
an information recording module 402, configured to record information related to the uncertain optimization instruction; the related information comprises optimization conditions of the uncertain optimization instruction;
a translation optimization module 403, configured to optimize the uncertain optimization instruction in the preceding basic block if the optimization condition is determined to be satisfied during the process of translating the subsequent basic block.
Optionally, the uncertain optimization instruction is a flag bit calculation instruction generated when an instruction sequence including a conditional jump instruction is translated, the conditional jump instruction corresponds to two different exits, one exit points to a jump position corresponding to when a jump condition is met, the other exit points to a jump position corresponding to when the jump condition is not met, and the two different exits respectively correspond to respective flag bit calculation instructions.
Optionally, the optimization conditions include: the instructions in the subsequent basic blocks override the calculation results of the uncertain optimization instructions.
Optionally, the translation determining module includes:
the template matching sub-module is used for matching the instruction sequence in the preamble basic block with the translation templates in the translation template library to obtain matched translation templates; if the translation template contains an uncertain optimization instruction, the translation template comprises a preset domain, wherein the preset domain is used for recording the uncertain optimization instruction and related information contained in the translation template;
the template translation submodule is used for translating the instruction sequences in the precursor basic blocks based on the matched translation templates;
and the information determination submodule is used for determining uncertain optimization instructions and related information contained in the precursor basic blocks translated based on the matched translation templates through the preset domain if the matched translation templates comprise the preset domain.
Optionally, the translation optimization module is specifically configured to: the uncertain optimization instruction in the preamble basic block is set to a null instruction.
Optionally, the translation optimization module is specifically configured to: and when the re-translation overhead meets the preset condition, re-translating the uncertain optimized instruction and the subsequent instructions in the preamble basic block.
Optionally, the apparatus further comprises:
and the instruction reservation module is used for reserving the uncertain optimization instructions in the precursor basic block if the optimization conditions are determined not to be met in the process of translating the follow-up basic block.
According to the binary translation device provided by the embodiment of the invention, through the cross-basic-block optimization algorithm, the related information of the instructions (uncertain optimization instructions) which can not be determined temporarily in a single basic block is recorded, and whether the uncertain optimization instructions can be optimized is dynamically confirmed in the subsequent translation process. In the embodiment of the invention, only the related information of the uncertain optimization instructions in the precursor basic blocks is recorded in the binary translation process, the follow-up basic blocks are not required to be translated in advance, and whether the uncertain optimization instructions can be optimized or not is dynamically confirmed in the follow-up translation process, and if so, the corresponding optimization actions are executed, so that the optimization of the precursor basic blocks is completed. The embodiment of the invention reduces the expenditure of the translator, and can accurately identify and complete the executable instruction optimization across basic blocks. Further, the invention can identify and implement more deep optimization through a basic block crossing optimization algorithm, can reduce the generation of redundant instructions (semantics) in the binary translation process, and can improve the running efficiency of the translated program.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
Referring to fig. 5, a schematic structural diagram of an electronic device according to an embodiment of the present invention is shown. As shown in fig. 4, the electronic device includes: the device comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is configured to store at least one executable instruction that causes the processor to perform the steps of the binary translation method of the foregoing embodiment.
An embodiment of the present invention provides a non-transitory computer-readable storage medium, which when executed by a program or a processor of a terminal, enables the terminal to perform the steps of the binary translation method of the foregoing embodiment.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (7)
1. A binary translation method, the method comprising:
in the process of translating the precursor basic block, translating a combination of an operation instruction and a conditional jump instruction in a source instruction sequence of a first instruction set into a conditional jump instruction and a flag bit calculation instruction of a target instruction sequence of a second instruction set, wherein in the first instruction set, the operation instruction generates a flag bit in a flag bit register while generating an operation result, and in the second instruction set, the flag bit is generated by a single flag bit calculation instruction; and
in the process of translating the subsequent basic blocks, if the flag bit generated by the source instruction sequence in the subsequent basic blocks covers the flag bit generated by the operation instruction in the preceding basic blocks, optimizing the flag bit calculation instruction in the target instruction sequence corresponding to the preceding basic blocks.
2. The method of claim 1, wherein conditional jump instructions of the target instruction sequence correspond to two different exits, one of the exits pointing to a jump location corresponding to when a jump condition is satisfied and the other of the exits pointing to a jump location corresponding to when a jump condition is not satisfied, the two different exits corresponding to respective bit calculation instructions.
3. The method according to claim 1, wherein optimizing the flag bit calculation instruction in the target instruction sequence corresponding to the preamble basic block includes:
and setting the flag bit calculation instruction corresponding to the preamble basic block as a null instruction.
4. The method according to claim 1, wherein optimizing the flag calculation instruction of the target instruction sequence corresponding to the preamble basic block includes:
and when the re-translation overhead meets the preset condition, re-translating the flag bit calculation instruction corresponding to the preamble basic block and the subsequent instruction.
5. The method of claim 1, wherein the operation instructions in the source instruction sequence of the first instruction set are compare instructions.
6. An electronic device, comprising:
A processor; and
a memory having computer executable instructions stored thereon that, when executed by the processor, cause the processor to perform the binary translation method of any of claims 1-5.
7. A readable storage medium, characterized in that the readable storage medium has stored thereon a program or instructions which, when executed by a processor, implement the steps of the binary translation method according to any of claims 1 to 5.
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