CN101221496B - RISC processor device and data processing method thereof - Google Patents
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Abstract
The present invention discloses a reduced instruction set computer (RISC) processor device and the data processing method thereof. The device comprises a decoder, a physical register file and an operational unit, as well as a data path connected among the decoder, the physical register file and the operational unit, wherein, each physical register in the physical register file is extended to 72 bits, and the whole data path is uniformly expanded to 72 bits; the operational unit comprises an extended operational module which is used in instruction operation to modify the flag bit of the 72-bit register in the physical register file and to carry out new instruction operation according to the modified flag bit. The present invention expands the optimization space of virtual machines and achieves the objective of improving the performance of virtual machines.
Description
Technical field
The present invention relates to the computer processor technical field, particularly relate to a kind of Reduced Instruction Set Computer (RISC) processor device and data processing method thereof.
Background technology
Virtual machine is the notion that the sixties in 20th century, IBM Corporation proposed, and puts into effect.The main flow computing machine was a large scale computer at that time, and by large scale computer being divided into a plurality of virtual machines, (multiple different application or a plurality of user can share this scarce resource for Virtual Machine Monitor, separation VMM) to utilize virtual machine monitor.
But, along with the enhancing of hardware cost reduction and computing power, and the appearance of multiple task operating system (OS), virtual machine monitor slowly steps down from the stage of history, and microcomputer and personal computer (PC) are propagated its belief on a large scale.
Yet because virtual machine powerful and successfully be function and the equipment that the user only can visit and utilize the combination by instruction set just can form, recent years, virtual machine monitor becomes the focus of academia and industry member again.Virtual machine monitor provides a kind of virtual solution for the true restriction of modem computer systems, and it becomes a powerful instrument, and this instrument can be expanded the ability of modem computer systems greatly.
Current X86 framework has occupied leading status in a lot of application, much the application of large-scale server category all is the X86 framework.Reduced Instruction Set Computer (Reduced Instruction Set Computing, RISC) realize just becoming necessary task with the compatibility of X86 framework for the application of operation service class widely by the microprocessor of framework.In addition, in the computing machine of existing X86 framework, application program is variation more, and a lot of business softwares all are based on the X86 framework, so risc microcontroller wants to move more widely diversified application, also are starved of the compatibility of realization to X86.
MIPS has the virtual machine platform of much increasing income at present as a very big branch of RISC, can realize that MIPS is to the support of X86 heterogeneous structure of platform.
On the MIPS framework with the compatible X86 framework of virtual machine need consider a lot of aspect, wherein be exactly to the use of flag register (EFLAGS) zone bit on the one hand in the X86 framework.
The EFLAGS zone bit computing of totally 6 bits (Bit) is supported in the instruction of X86 fixed-point arithmetic, and promptly a lot of operational orders also will produce zone bit except producing data value, and transfer instruction as jump condition, realizes ordering calculation to zone bit.
Flag register among the X86 (EFLAGS) mainly comprises following three partial contents:
One, Status Flag (Status Flags) comprises totally six of CF (carry flag), PF (parity bit), AF (auxiliary carry), ZF (zero flag), SF (non-minus flag) and OF (overflowing);
Two, DF (Directional Sign) sign is used for controlling the direction that string operation is instructed;
Three, other system sign and I/O privileged domain (IOPL territory), these signs comprise the single-step mode sign, interrupt enabling, I/O priority etc., and user program can not be revised these signs.
Content about second and third part of flag register has had relevant hardware to realize among the MIPS64, but realizes for the content of first is not corresponding.
Also have one 16 floating-point flag register among the X86, form a sign (TAG), totally 8 signs (TAG) for wherein per two.The state of the corresponding flating point register of each sign (TAG), 00 expression valid, 01 expression zero, 10 expression special, 11 expression empty.Because the flating point register among the X86 is organized in the mode of stack, the floating-point flag register is mainly used in when detecting the floating-point visit, and the stack overflow exception can or can not take place.
In the prior art, the content of flag register first, promptly the MIPS of Status Flag (Status Flags) and floating-point flag register realizes to the isomery of X86, does not all have hardware to realize, and the virtual machine isomery of software level realizes producing very big expense, and performance is caused very big influence.
Summary of the invention
Problem to be solved by this invention is to provide a kind of Reduced Instruction Set Computer (RISC) processor device and data processing method thereof.The optimization space that it enlarges virtual machine reaches the purpose that improves the virtual machine performance.
Be a kind of risc processor device of realizing that the present invention provides, comprise code translator, physical register heap and arithmetic unit, and code translator, the data path that connects between physical register heap and the arithmetic unit, described physical register heap comprises general-purpose register after the expansion and the flating point register after the expansion, and it is 72 that each physical register wherein is expanded, and described data path unification is extended for 72;
Described arithmetic unit, comprise the extended arithmetic module, be used for being in X86 virtual machine mode of operation following time, in ordering calculation when processor, zone bit to 72 physical registers in the physical register heap is made amendment, and carries out new ordering calculation according to the zone bit of revising.
Flating point register after general-purpose register after the described expansion and the expansion comprises 64 data bit part and 8 zone bit part respectively.
The the 64th to 69 of general-purpose register after the described expansion totally 6 zone bits are represented CF position, PF position, AF position, ZF position, SF position and OF position from low to high respectively.
The 64th the TAG zone bit as this flating point register of the flating point register after the described expansion represented the state of this flating point register, and the stack overflow exception can or can not take place when being used to detect the floating-point visit.
Described TAG position is 0, and this is sky then to represent floating point stack, and promptly the numerical value in the flating point register is invalid; If be 1, represent that then the numerical value in the flating point register is effective.
Described extended arithmetic module, comprise general-purpose register extended arithmetic module, be used for being in X86 virtual machine mode of operation following time when processor, utilize the general-purpose register after the described expansion to carry out computing, and the data division of operation result and sign part are write back in the target general-purpose register after expansion together.
Described code translator comprises up-to-date zone bit pointer, is used in reference to the general-purpose register that combines to up-to-date zone bit.
Described extended arithmetic module comprises flating point register extended arithmetic module, is used for being in X86 virtual machine mode of operation following time when processor, utilizes the flating point register after the described expansion to carry out computing, and rewrites the TAG position of flating point register according to operation result.
For realizing that the object of the invention also provides a kind of data processing method of risc processor device, comprises the following steps:
Steps A, when the X86 virtual machine mode of operation of risc processor was set, general-purpose register and flating point register in the expansion physical register heap were 72, simultaneously the data path unification are extended for 72;
Step B in ordering calculation, makes amendment to the zone bit of 72 physical registers in the physical register heap, and carries out new ordering calculation according to the zone bit of revising.
Among the described step B, for general-purpose register, comprise the following steps:
Step B1, when the general-purpose register after the expansion carried out computing, result data part and sign part that computing is obtained write back to the target general-purpose register together;
Step B2 according to ordering calculation, revises up-to-date zone bit pointer, the general-purpose register that the up-to-date zone bit pointed of code translator combines with up-to-date zone bit.
Also comprise the following steps: after the described step B2
Step B3 if a new ordering calculation needs the service marking position as source operand, then uses the source operand of the general-purpose register of up-to-date zone bit pointed as this instruction.
Among the described step B2, revise up-to-date zone bit pointer, comprise the following steps:
1) if need change up-to-date zone bit during ordering calculation, then up-to-date zone bit pointer value is changed into the destination register that points to this instruction;
2) if do not need to change up-to-date zone bit during new ordering calculation, but but the physical register of up-to-date zone bit pointed as destination operand, then need the value of the zone bit in the original physical register is copied in the new physical register, as the general-purpose register of up-to-date zone bit pointed;
3) if the whole zone bits of modifying of order are then revised 6 zone bits in the general-purpose register, again with the new general-purpose register of up-to-date zone bit pointed;
4), then adopt the method for splicing that the multidigit zone bit is stitched together if wherein or the multidigit in the 6 bit flag positions only revised in instruction.
Among the described step B, for flating point register, comprise the following steps:
Step B1 ' if when floating-point operation instruction uses flating point register in the floating point stack to carry out computing, then needs to judge earlier the state of TAG zone bit, if the TAG position is 0 to be that data are invalid, then causes the floating point stack overflow exception;
Step B2 ' is 1 promptly effectively if the state of TAG zone bit is judged in floating-point operation instruction, then normally carries out computing, and the TAG position with the target flating point register after carrying out is 1;
Described step B2 ' also comprises the following steps: afterwards
Step B3 ' uses the instruction SETTAG to TAG set to make that corresponding floating point stack discipline is effective or invalid.
The invention has the beneficial effects as follows: Reduced Instruction Set Computer of the present invention (RISC) processor device and data processing method thereof, zone bit and floating point stack to X86 on the MIPS framework are done the necessary hardware support, on risc processor, realize the zone bit computing of flag register 6 bits and prevent that floating point stack from overflowing, realize compatibility with x86 instruction set, to enlarge the optimization space of virtual machine, reach the purpose that improves the virtual machine performance.
Description of drawings
Fig. 1 is a risc processor apparatus structure synoptic diagram of the present invention;
Fig. 2 is 72 bit registers that expand to of 64 physical registers of the embodiment of the invention, as the support synoptic diagram of general-purpose register zone bit (EFLAGS);
Fig. 3 is 72 bit registers that expand to of 64 physical registers of the embodiment of the invention, as the support synoptic diagram of flating point register TAG zone bit;
Fig. 4 is a risc processor device data processing method process flow diagram of the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, a kind of Reduced Instruction Set Computer (RISC) processor device of the present invention and data processing method thereof are further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
In embodiments of the present invention, MIPS64 instruction set with Reduced Instruction Set Computer (RISC) is an example, and the data processing method of Reduced Instruction Set Computer of the present invention (RISC) processor device is described, but should be noted that, this is not a limitation of the present invention, and the present invention is equally applicable to the situation of other Reduced Instruction Set Computers (RISC).
For realizing that the present invention provides a kind of Reduced Instruction Set Computer (RISC) processor device, as shown in Figure 1, comprise code translator 1, physical register heap 2 and arithmetic unit 3, and code translator 1, the data path (data bus) 4 that connects between physical register heap 2 and the arithmetic unit 3.
Described physical register heap 2 comprises general-purpose register 21 and flating point register 22.
In the embodiment of the invention, each physical register in the physical register heap 2 is expanded to 72, comprise 64 data bit part and 8 zone bit part; Simultaneously, whole data path 4 (data bus) comprises that unifications such as launching path is extended for 72.
The the 64th to 69 of general-purpose register 21 after the expansion totally 6 zone bits are represented CF position, PF position, AF position, ZF position, SF position and OF position from low to high respectively, as shown in Figure 3.
The 64th the TAG zone bit as this flating point register 22 of the flating point register 22 after the expansion represented the state of this flating point register 22, as shown in Figure 4.The stack overflow exception can or can not take place in this TAG zone bit with the flating point register 22 of X86 floating point stack item mapping when being used to detect the floating-point visit, the TAG position of other flating point register is inoperative.
Because the floating point stack in the X 86 processor has only 8, thus mapping 0-7 number totally 8 flating point registers be corresponding entry in the floating point stack, the TAG position of other flating point registers is inoperative.
As a kind of embodiment, if the TAG position is 0, then expression empty (empty) is promptly invalid; If be 1, then expression effective (valid).
Described arithmetic unit 3, comprise extended arithmetic module 31, be used for being in X86 virtual machine mode of operation following time, in ordering calculation when processor, zone bit to 72 bit registers in the physical register heap 2 is made amendment, and carries out new ordering calculation according to the zone bit of revising.
Described extended arithmetic module 31 comprises general-purpose register extended arithmetic module 311 and flating point register extended arithmetic module 312, wherein:
Described general-purpose register extended arithmetic module 311, be used for being in X86 virtual machine mode of operation following time when processor, utilize the general-purpose register 21 after the described expansion to carry out computing, and the result data part that computing is obtained and sign part write back in the general-purpose register 21 after expansion together.
Described flating point register extended arithmetic module 312, be used for being in X86 virtual machine mode of operation following time when processor, utilize the flating point register 22 after the described expansion and the TAG position of flating point register 22 to carry out computing, and rewrite the TAG position of flating point register 22 according to operation result.
Described code translator 1 comprises up-to-date zone bit pointer Reflag11, is used in reference to the general-purpose register 21 that combines to up-to-date zone bit.
Described up-to-date zone bit, be meant ordering calculation after, last reformed zone bit; The general-purpose register 21 that described and up-to-date zone bit combines, be meant ordering calculation after, the general-purpose register 21 at last reformed zone bit place.For example, article one, add instruction ADD, use the value addition in first general-purpose register and second general-purpose register, the result is put in the 3rd general register, and change the zone bit of the 3rd general register according to the ordering calculation result, the zone bit of then reformed the 3rd general register is up-to-date zone bit, and the 3rd general register is the general-purpose register that combines with up-to-date zone bit, and this up-to-date zone bit pointer Reflag11 points to the 3rd general register.
Describe the data processing method of Reduced Instruction Set Computer of the present invention (RISC) processor device below in detail, comprise the following steps:
Step S100, when the X86 virtual machine mode of operation of risc processor was set, the general-purpose register 21 and the flating point register 22 that are provided with in the physical register heap 2 were 72 physical registers, comprise 64 data bit and 8 zone bit.
72 physical register heap 2 comprises 64 data bit and 8 zone bit.
The the 64th to 69 of general-purpose register 21 after the expansion totally 6 zone bits are represented CF position, PF position, AF position, ZF position, SF position and OF position from low to high respectively, as shown in Figure 3.
The 64th the TAG zone bit as this flating point register 22 of the flating point register 22 after the expansion represented the state of this flating point register 22, as shown in Figure 4.The stack overflow exception can or can not take place in this TAG zone bit with the flating point register 22 of X86 floating point stack item mapping when being used to detect the floating-point visit, the TAG position of other flating point register is inoperative.As a kind of embodiment, if the TAG position is 0, then expression empty (empty) is promptly invalid; If be 1, then expression effective (valid).
Step S200 in ordering calculation, makes amendment to the zone bit of 72 bit registers in the physical register heap 2, and carries out new ordering calculation according to the zone bit of revising.
Among the step S200, for general-purpose register 21, comprise the following steps:
Step S210, when the general-purpose register 21 after the expansion carried out computing, result data part and sign part that computing is obtained write back to target general-purpose register 21 together;
Step S220 according to ordering calculation, revises up-to-date zone bit pointer Reflag11, and the up-to-date zone bit pointer Reflag11 of code translator 1 points to the general-purpose register 21 that combines with up-to-date zone bit;
According to different instructions, up-to-date zone bit pointer Reflag11 has different amending methods:
A) if need change up-to-date zone bit during ordering calculation, then up-to-date zone bit pointer Reflag11 value is changed into the destination register that points to this instruction;
B) if do not need to change up-to-date zone bit during new ordering calculation, but but the physical register that up-to-date zone bit pointer Reflag11 is pointed to is as destination operand, then need the value of the zone bit in the original physical register is copied in the new physical register, as the general-purpose register 21 of up-to-date zone bit pointer Reflags11 sensing;
C), more up-to-date zone bit pointer Reflags11 is pointed to new general-purpose register 21 if the whole zone bits of modifying of order are then revised 6 zone bits in the general-purpose register 21;
D) if wherein or the multidigit in the 6 bit flag positions only revised in instruction, then adopt the method for splicing that the multidigit zone bit is stitched together, for example OF, CF, SF, ZF and PF sign are only revised in the instruction of and logical and, so just revise these 5 in destination register, the AF zone bit in the register that the pointer Reflag of up-to-date zone bit is pointed to copies to that splicing gets final product in the new destination register again.
Step S230, if a new ordering calculation needs the service marking position as source operand, the general-purpose register 21 of sensing that then uses up-to-date zone bit pointer Reflag11 is as the source operand of this instruction.
For the instruction of carrying out redirect and computing according to the zone bit of general-purpose register 21, when carrying out, can directly read arithmetic unit 3 most-significant byte in up-to-date zone bit pointer Reflag11 72 extended registers pointed, and the value that obtains zone bit is as the source; Obtain the instruction of the zone bit of general-purpose register 21 for direct computing, the zone bit that computing is obtained is written in the expansion most-significant byte of destination register.
For example, in the embodiment of the invention, according to the zone bit of general-purpose register carry out computing and directly computing obtain the value of the zone bit of general-purpose register, for example add instruction, it carries out the add operation of MIPS instruction set, but when calculating addition results and depositing destination register in, also will be according to the high 6 bit flag place values of result's value modifying target register;
For example, carry out branch's jump instruction according to one in the zone bit of general-purpose register or multidigit, then or several according to zone bit carries out or redirect.
Among the step S200, for flating point register 22, comprise the following steps:
Step S210 ' if when floating-point operation instruction uses flating point register in the floating point stack to carry out computing, then needs to judge earlier the state of TAG zone bit, if the TAG position is 0 to be that data are invalid, then causes the floating point stack overflow exception;
Step S220 ' is 1 promptly effectively if the state of TAG zone bit is judged in floating-point operation instruction, then normally carries out computing, and the TAG position with the target flating point register after carrying out is 1;
Described step S220 ' can also comprise the following steps: afterwards
Step S230 ' uses the instruction SETTAG to TAG set to make that corresponding floating point stack discipline is effective or invalid.
As a kind of embodiment, SETTAG order format is as follows:
SETTAG ft?imm
The TAG position that this instruction is provided with flating point register ft is the imm value, represents that when imm is 0 the numerical value in the corresponding flating point register is invalid, represents that when imm is 1 the numerical value in the corresponding flating point register is effective.
Because the floating point stack in the X 86 processor has only 8, so ft between 0 to 7, if sequence number is used this instruction greater than 8 flating point register, then cuts little ice.
If there is not the expansion of register, existing structure is if realize the zone bit (EFLAGS) of physical register so, every instruction that calculates the zone bit of physical register all will be translated into a lot of bars and instruct and realize, comprising: at first calculate the result, carry out various computings according to result's value again, value in the hope of each zone bit, and this value of statistical indicant preserved (perhaps be kept in the register, perhaps be kept in the internal memory, if be kept in the register, other instruction is when using this register so, this value need be deposited in the internal memory, from internal memory, recover again when re-using), doing like this to have increased a lot of unnecessary spending.And Reduced Instruction Set Computer of the present invention (RISC) processor device and data processing method thereof are done the necessary hardware support to the physical register of X86 on the MIPS framework, to enlarge the optimization space of virtual machine, reach the purpose that improves the virtual machine performance.
In conjunction with the drawings to the description of the specific embodiment of the invention, others of the present invention and feature are conspicuous to those skilled in the art.
Reduced Instruction Set Computer of the present invention (RISC) processor device and data processing method thereof, flag register (EFLAGS) to X86 on the MIPS framework is done the necessary hardware support, to enlarge the optimization space of virtual machine, reach the purpose that improves the virtual machine performance.
More than specific embodiments of the invention are described and illustrate it is exemplary that these embodiment should be considered to it, and be not used in and limit the invention, the present invention should make an explanation according to appended claim.
Claims (13)
1. a risc processor device comprises code translator, physical register heap and arithmetic unit, and code translator, and the data path that connects between physical register heap and the arithmetic unit is characterized in that:
Described physical register heap comprises general-purpose register after the expansion and the flating point register after the expansion, and it is 72 that each physical register wherein is expanded;
Described data path unification is extended for 72;
Described arithmetic unit, comprise the extended arithmetic module, be used for being in X86 virtual machine mode of operation following time, in ordering calculation when processor, zone bit to 72 physical registers in the physical register heap is made amendment, and carries out new ordering calculation according to the zone bit of revising;
Wherein, described extended arithmetic module, comprise general-purpose register extended arithmetic module, be used for being in X86 virtual machine mode of operation following time when processor, utilize the general-purpose register after the described expansion to carry out computing, and the data division of operation result and sign part are write back in the target general-purpose register after expansion together.
2. risc processor device according to claim 1 is characterized in that, the flating point register after general-purpose register after the described expansion and the expansion comprises 64 data bit part and 8 zone bit part respectively.
3. risc processor device according to claim 2 is characterized in that, the 64th to 69 of the general-purpose register after the described expansion totally 6 zone bits are represented CF position, PF position, AF position, ZF position, SF position and OF position from low to high respectively.
4. risc processor device according to claim 2, it is characterized in that, the 64th the TAG zone bit as this flating point register of the flating point register after the described expansion represented the state of this flating point register, and the stack overflow exception can or can not take place when being used to detect the floating-point visit.
5. risc processor device according to claim 4 is characterized in that, described TAG position is 0, and this is sky then to represent floating point stack, and promptly the numerical value in the flating point register is invalid; If be 1, represent that then the numerical value in the flating point register is effective.
6. risc processor device according to claim 1 is characterized in that, described code translator comprises up-to-date zone bit pointer, is used in reference to the general-purpose register that combines to up-to-date zone bit.
7. risc processor device according to claim 1, it is characterized in that, described extended arithmetic module, comprise flating point register extended arithmetic module, be used for being in X86 virtual machine mode of operation following time when processor, utilize the flating point register after the described expansion to carry out computing, and rewrite the TAG position of flating point register according to operation result.
8. the data processing method of a risc processor device is characterized in that, comprises the following steps:
Steps A, when the X86 virtual machine mode of operation of risc processor was set, general-purpose register and flating point register in the expansion physical register heap were 72, simultaneously the data path unification are extended for 72;
Step B in ordering calculation, makes amendment to the zone bit of 72 physical registers in the physical register heap, and carries out new ordering calculation according to the zone bit of revising;
Wherein, when the general-purpose register after the expansion carried out computing, result data part and sign part that computing is obtained write back to the target general-purpose register together.
9. the data processing method of risc processor device according to claim 8 is characterized in that, among the described step B, for general-purpose register, comprises the following steps:
Step B1 according to ordering calculation, revises up-to-date zone bit pointer, the general-purpose register that the up-to-date zone bit pointed of code translator combines with up-to-date zone bit.
10. the data processing method of risc processor device according to claim 9 is characterized in that, also comprises the following steps: after the described step B1
Step B2 if a new ordering calculation needs the service marking position as source operand, then uses the source operand of the general-purpose register of up-to-date zone bit pointed as this instruction.
11. the data processing method according to claim 9 or 10 described risc processor devices is characterized in that, among the described step B1, revises up-to-date zone bit pointer, comprises the following steps:
1) if need change up-to-date zone bit during ordering calculation, then up-to-date zone bit pointer value is changed into the destination register that points to this instruction;
2) if do not need to change up-to-date zone bit during new ordering calculation, but but the physical register of up-to-date zone bit pointed as destination operand, then need the value of the zone bit in the original physical register is copied in the new physical register, as the general-purpose register of up-to-date zone bit pointed;
3) if the whole zone bits of modifying of order are then revised 6 zone bits in the general-purpose register, again with the new general-purpose register of up-to-date zone bit pointed;
4), then adopt the method for splicing that the multidigit zone bit is stitched together if wherein or the multidigit in the 6 bit flag positions only revised in instruction.
12. the data processing method of risc processor device according to claim 8 is characterized in that, among the described step B, for flating point register, comprises the following steps:
Step B1 ' if when floating-point operation instruction uses flating point register in the floating point stack to carry out computing, then needs to judge earlier the state of TAG zone bit, if the TAG position is 0 to be that data are invalid, then causes the floating point stack overflow exception;
Step B2 ' is 1 promptly effectively if the state of TAG zone bit is judged in floating-point operation instruction, then normally carries out computing, and the TAG position with the target flating point register after carrying out is 1.
13. the data processing method of risc processor device according to claim 12 is characterized in that, also comprises the following steps: behind the described step B2 '
Step B3 ' uses the instruction SETTAG to TAG set to make that corresponding floating point stack discipline is effective or invalid.
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| US5598553A (en) * | 1994-03-08 | 1997-01-28 | Exponential Technology, Inc. | Program watchpoint checking using paging with sub-page validity |
| CN1296815C (en) * | 2003-10-21 | 2007-01-24 | 中国科学院计算技术研究所 | Marker digit optimizing method in binary system translation |
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