CN116841458A

CN116841458A - Memory read-write control method, system, terminal and storage medium

Info

Publication number: CN116841458A
Application number: CN202310504702.2A
Authority: CN
Inventors: 张旭佑
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2023-05-06
Filing date: 2023-05-06
Publication date: 2023-10-03

Abstract

The invention relates to the technical field of storage, and particularly provides a memory read-write control method, a system, a terminal and a storage medium, wherein the method comprises the following steps: caching the request of the thread in the control device; monitoring the cached request quantity of the thread; monitoring the time length from the current time to the previous execution request time; judging the threshold value of the quantity and the duration to obtain a threshold value judging result; analyzing the threshold judgment result, and forwarding the cached request to the memory if the threshold judgment result meets a preset trigger condition. The invention can avoid delay caused by buffering requests of the threads, and can also avoid the situation that the DDR control right is occupied too long, the waiting instruction is read or written too long or the efficiency is reduced or the state is blocked due to too many single threads.

Description

Memory read-write control method, system, terminal and storage medium

Technical Field

The invention belongs to the technical field of storage, and particularly relates to a memory read-write control method, a memory read-write control system, a memory read-write control terminal and a memory medium.

Background

Ddr=double Data Rate Double Rate, DDR sdram=double Rate synchronous dynamic random access memory, commonly referred to as DDR. DDR is a common buffer device, which has the advantage of large capacity, but is not as large as a hard disk, but is enough to hold the buffer data required by various computing devices (CPU/SOC/ASIC, etc.).

For each single thread, if the data demand is small, the DDR read/write command is frequently switched every time a small amount of data is read or written, resulting in reduced performance. Some techniques therefore set a threshold (burst) size for threads, collect read or write commands for a single thread, and perform a large number of read or write operations at a time after reaching the burst set number.

When multiple threads read and write the same DDR module at the same time on an application, when burst setting of a thread is too large, a certain time is required for a certain thread to reach burst when a cache request is made, so that DDR control authority is occupied for too long, and the execution efficiency of other threads is affected. However, the burst setting of each thread is too small, which may cause continuous switching of read/write commands in a short time for DDR, which may not only reduce DDR efficiency, but also cause immediate read after writing to the same DDR location in a short time, resulting in not writing to DDR and further reading erroneous data.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides a memory read-write control method, a system, a terminal and a storage medium, which are used for solving the problems that a single thread occupies the DDR control authority for too long or the DDR frequently switches read-write instructions to cause data confusion in the method for setting a quantity of threshold buffer requests in a DDR controller.

In a first aspect, the present invention provides a memory read-write control method, including:

caching the request of the thread in the control device;

monitoring the cached request quantity of the thread;

monitoring the time length from the current time to the previous execution request time;

judging the threshold value of the quantity and the duration to obtain a threshold value judging result;

analyzing the threshold judgment result, and forwarding the cached request to the memory if the threshold judgment result meets a preset trigger condition.

In an alternative embodiment, buffering requests for threads in a control device includes:

allocating unique request cache addresses and data cache addresses for threads;

caching the request received from the thread to a request cache address;

and if the request is a write request, caching the data to be written of the write request to a data cache address.

In an alternative embodiment, the method further comprises:

analyzing the cached request type;

if the request type is a write request, collecting the data volume of all cached data to be written as the data volume of write requirements;

if the request type is a read request, analyzing the data volume of the target data, and accumulating the data volumes of all the target data of the read request to obtain the data volume of the read request;

and comparing the write demand data quantity or the read demand data quantity with the corresponding threshold value, and forwarding the corresponding cached request when the corresponding threshold value is reached.

In an alternative embodiment, monitoring the duration of the current time from the time of the previous execution request includes:

the control timer starts timing each time the request is forwarded to the memory;

zeroing the timing of the timer each time a request is started to be forwarded to the memory;

and the time counted by the acquisition timer is output as the duration.

In an alternative embodiment, the threshold value judgment of the number and the duration is performed to obtain a threshold value judgment result, which includes:

presetting a time threshold and a quantity threshold;

and comparing the number with a number threshold, comparing the duration with a time threshold, and outputting a comparison result as a threshold judgment result.

In an alternative embodiment, analyzing the threshold judgment result, if the threshold judgment result meets a preset trigger condition, forwarding the cached request to the memory, including:

and if the number reaches a number threshold or the duration reaches a time threshold, forwarding the cached request to a memory.

In an alternative embodiment, the method further comprises:

if the read request and the write request sent by the same thread are received, the read request and the write request are respectively cached, and the cached write request is preferably forwarded.

In an alternative embodiment, after forwarding the cached request to the memory, the method further comprises:

if the request is a read request, caching the data returned from the memory;

and sending the cached data to the thread after confirming that the memory has returned all the required data of the read request.

In a second aspect, the present invention provides a memory read-write control system, including:

the request caching module is used for caching requests of threads in the control device;

the first monitoring module is used for monitoring the cached request quantity of the threads;

the second monitoring module is used for monitoring the duration of the current moment from the previous execution request moment;

the threshold judging module is used for judging the threshold of the quantity and the duration to obtain a threshold judging result;

and the request forwarding module is used for analyzing the threshold judgment result, and forwarding the cached request to the memory if the threshold judgment result meets the preset trigger condition.

In an alternative embodiment, the request cache module includes:

the cache allocation unit is used for allocating unique request cache addresses and data cache addresses for the threads;

a request caching unit, configured to cache a request received from the thread to a request cache address;

and the data caching unit is used for caching the data to be written of the write request to the data caching address if the request is the write request.

In an alternative embodiment, the system further comprises:

the type analyzing unit is used for analyzing the cached request type;

the write request monitoring unit is used for acquiring the data volume of all cached data to be written as the write demand data volume if the request type is a write request;

the read request monitoring unit is used for analyzing the data volume of the target data if the request type is a read request, and accumulating the data volumes of all the read request target data to obtain the read demand data volume;

the demand triggering unit is used for comparing the writing demand data quantity or the reading demand data quantity with the corresponding threshold value and forwarding the corresponding cached request when the corresponding threshold value is reached.

In an alternative embodiment, the second monitoring module includes:

a start control unit for controlling the timer to start timing each time the request is forwarded to the memory;

a zeroing control unit for zeroing the timing of the timer each time a request starts to be forwarded to the memory;

and the duration acquisition unit is used for acquiring the time counted by the timer as the duration output.

In an alternative embodiment, the threshold determination module includes:

a threshold setting unit for presetting a time threshold and a number threshold;

and the threshold comparison unit is used for comparing the number with a number threshold, comparing the duration with a time threshold and outputting a comparison result as a threshold judgment result.

In an alternative embodiment, the request forwarding module includes:

and the execution triggering unit is used for forwarding the cached request to the memory if the number reaches a number threshold or the duration reaches a time threshold.

In an alternative embodiment, the system further comprises:

and the sequence setting module is used for respectively caching the read request and the write request if the read request and the write request sent by the same thread are received, and preferably forwarding the cached write request.

In an alternative embodiment, the system further comprises:

the data receiving module is used for caching the data returned from the memory if the request is a read request;

and the data forwarding module is used for confirming that the memory returns the required data of all the read requests and sending the cached data to the thread.

In a third aspect, a terminal is provided, including:

a processor, a memory, wherein,

the memory is used for storing a computer program,

the processor is configured to call and run the computer program from the memory, so that the terminal performs the method of the terminal as described above.

In a fourth aspect, there is provided a computer storage medium having instructions stored therein which, when run on a computer, cause the computer to perform the method of the above aspects.

The memory read-write control method, system, terminal and storage medium provided by the invention have the beneficial effects that requests of threads and related data can be cached, and the cached requests are forwarded based on two factors of caching time and data volume.

In addition, the invention has reliable design principle, simple structure and very wide application prospect.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

FIG. 1 is a schematic flow chart of a method of one embodiment of the invention.

Fig. 2 is a schematic architectural diagram of a carrier for carrying out the method of an embodiment of the present invention.

Fig. 3 is another schematic flow chart of a method of one embodiment of the invention.

Fig. 4 is a schematic architectural diagram of a buffer module of an execution carrier of a method of an embodiment of the present invention.

FIG. 5 is a schematic diagram of the read and write instruction execution sequence of a method of one embodiment of the invention.

Fig. 6 is a schematic block diagram of a system of one embodiment of the present invention.

Fig. 7 is a schematic structural diagram of a terminal according to an embodiment of the present invention.

Detailed Description

In order to make the technical solution of the present invention better understood by those skilled in the art, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

The following explains key terms appearing in the present invention.

Thread (english) is the smallest unit that an operating system can perform operation scheduling. It is included in the process and is the actual unit of operation in the process. One thread refers to a single sequential control flow in a process, and multiple threads can be concurrent in one process, and each thread performs different tasks in parallel. In Unix System V and SunOS, lightweight processes (lightweight processes) are also referred to, but lightweight processes refer more to core threads (kernel threads) and user threads (user threads) are referred to as threads.

The memory read-write control method provided by the embodiment of the invention is executed by the computer equipment, and correspondingly, the memory read-write control system is operated in the computer equipment.

FIG. 1 is a schematic flow chart of a method of one embodiment of the invention. The execution body of fig. 1 may be a memory read-write control system. The order of the steps in the flow chart may be changed and some may be omitted according to different needs.

As shown in fig. 1, the method includes:

step 110, caching the request of the thread in the control device;

step 120, monitoring the cached request number of the thread;

step 130, monitoring the duration of the current time from the previous execution request time;

step 140, judging the threshold value of the quantity and the duration to obtain a threshold value judging result;

and 150, analyzing the threshold judgment result, and forwarding the cached request to the memory if the threshold judgment result meets the preset trigger condition.

In order to facilitate understanding of the present invention, the memory read-write control method provided by the present invention is further described below with reference to a process of controlling memory read-write in the embodiment by using the principle of the memory read-write control method of the present invention.

Specifically, referring to fig. 2, the execution carrier may select various control chips with memory functions, for example, FPGA FPGA (Field Programmable Gate Array) is a product further developed on the basis of programmable devices such as PAL (programmable array logic), GAL (general array logic) and the like. The programmable device is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), which not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable device. One side IO interface of the FPGA is connected with the thread end, and the other side IO interface is connected with the DDR. All the DDR read-write instructions of the thread are transmitted to a DDR buffer module, and then the DDR read-write instructions are uniformly transmitted to the DDR by the DDR buffer module, and the data read back from the DDR are sequentially transmitted back to each thread.

Referring to fig. 3, the memory read-write control method includes:

s1, caching the thread request in a control device.

Allocating unique request cache addresses and data cache addresses for threads; caching the request received from the thread to a request cache address; and if the request is a write request, caching the data to be written of the write request to a data cache address.

Specifically, if there are multiple threads, a memory block, i.e. a memory area, is allocated to each thread in the cache module, for storing the request and the accompanying data of the corresponding thread.

As shown in FIG. 4, the buffer module inputs the write command, write data and read command of each thread into mux (multiplexer), the mux arranges the write command, write data and read command sequence of each thread, and sends them into buffer, and then determines the timing of sending the read/write command to DDR controller based on the execution principle shown in FIG. 5. The data read back from DDR is buffered and then distributed to each thread through the read data demux (demultiplexer).

If the read request and the write request sent by the same thread are received, the read request and the write request are respectively cached, and the cached write request is preferably forwarded. If the read instruction or the write instruction buffer has data, the instruction is sent, and if the read instruction and the write instruction are simultaneously read and written, the write instruction is given priority.

If a thread does not have a request for a long time, the allocated cache address is retired.

S2, monitoring the cached request quantity of the thread.

And monitoring the cached request quantity, taking the request quantity as a control index, namely monitoring the cached request quantity, and forwarding the requests in batches if the request quantity reaches a set threshold value.

In order to avoid that the data amount of a request of a certain thread is large and the DDR is occupied for a long time, the number of the requests is further used as a monitoring index. The specific method comprises the following steps:

analyzing the cached request type; if the request type is a write request, collecting the data volume of all cached data to be written as the required data volume; if the request type is a read request, analyzing the data volume of the target data, and accumulating the data volumes of all the read request target data to obtain the required data volume.

When the required data volume of the read request is monitored, the data volume is calculated according to the information such as the address of the target data.

And S3, monitoring the time length from the current time to the previous execution request time.

The control timer starts timing each time the request is forwarded to the memory; zeroing the timing of the timer each time a request is started to be forwarded to the memory; and the time counted by the acquisition timer is output as the duration.

S4, judging the threshold values of the quantity and the duration to obtain a threshold value judging result.

Presetting a time threshold and a quantity threshold; and comparing the number with a number threshold, comparing the duration with a time threshold, and outputting a comparison result as a threshold judgment result.

S5, analyzing a threshold judgment result, and forwarding the cached request to the memory if the threshold judgment result meets a preset trigger condition.

If the request is a read request, caching the data returned from the memory; and sending the cached data to the thread after confirming that the memory has returned all the required data of the read request.

Specifically, in the actual control process, the embodiment of the present invention will be described by taking the following control flow as an example:

when the read instruction or the write instruction is idle, whether the data exists in the buffer of the read instruction or the write instruction, if the data exists, the instruction is sent, and if the read instruction and the write instruction exist simultaneously, the write instruction is given priority.

For example, a write (read) instruction dispatch state is entered, in which a timer is simultaneously started; entering a write (read) instruction dispatch completion state if the set burst number is full within a set time range, for example, 1 ms; if the set time 1ms is reached, the set burst number has not been sent, and the write (read) instruction dispatch completion state is entered (because there is a possibility that not so many instructions need to be dispatched at all, but if waiting at all, this will result in a decrease in efficiency, or a stuck in this state will not continue to operate). In the completion state of the write (read) instruction dispatch, it is determined whether the read (write) instruction buffers data, if so, the read (write) state is entered, otherwise, the idle state is entered.

In some embodiments, the memory read/write control system 600 may include a plurality of functional modules composed of computer program segments. The computer program of each program segment in the memory read/write control system 600 may be stored in a memory of a computer device and executed by at least one processor to perform the functions of memory read/write control (described in detail with reference to fig. 1).

In this embodiment, the memory read/write control system 600 may be divided into a plurality of functional modules according to the functions performed by the system, as shown in fig. 6. The functional module may include: a request caching module 610, a first monitoring module 620, a second monitoring module 630, a threshold determination module 640, and a request forwarding module 650. The module referred to in the present invention refers to a series of computer program segments capable of being executed by at least one processor and of performing a fixed function, stored in a memory. In the present embodiment, the functions of the respective modules will be described in detail in the following embodiments.

A request caching module 610, configured to cache a request of a thread in a control device;

a first monitoring module 620, configured to monitor the cached request number of the threads;

a second monitoring module 630, configured to monitor a duration of the current time from a time of a previous execution request;

a threshold value judging module 640, configured to judge the threshold values of the number and the duration, and obtain a threshold value judging result;

the request forwarding module 650 is configured to parse the threshold judgment result, and forward the buffered request to the memory if the threshold judgment result meets a preset trigger condition.

Optionally, as an embodiment of the present invention, the request caching module includes:

Optionally, as an embodiment of the present invention, the system further includes:

the type analyzing unit is used for analyzing the cached request type;

Optionally, as an embodiment of the present invention, the second monitoring module includes:

Optionally, as an embodiment of the present invention, the threshold determining module includes:

Optionally, as an embodiment of the present invention, the request forwarding module includes:

The system has the following beneficial effects:

each group of threads can send instructions directly without self buffering and burst, and through the module of the invention, DDR bandwidth is used efficiently for DDR as well as burst reading or writing, and the threads can immediately respond to the self instruction requirement, so that delay caused by self buffering is avoided.

The problem that the efficiency of other threads is reduced due to the fact that DDR control rights are occupied too long as the number of single threads is too large is avoided.

Limiting the read or write command time using a specific timer prevents waiting for a read or write command too long or causing a decrease in efficiency, or status sticking.

Fig. 7 is a schematic structural diagram of a terminal 700 according to an embodiment of the present invention, where the terminal 700 may be used to execute a memory read-write control method according to an embodiment of the present invention.

The terminal 700 may include: processor 710, memory 720, and communication module 730. The components may communicate via one or more buses, and it will be appreciated by those skilled in the art that the configuration of the server as shown in the drawings is not limiting of the invention, as it may be a bus-like structure, a star-like structure, or include more or fewer components than shown, or may be a combination of certain components or a different arrangement of components.

The memory 720 may be used to store instructions for execution by the processor 710, and the memory 720 may be implemented by any type of volatile or non-volatile memory terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk. The execution of the instructions in memory 720, when executed by processor 710, enables terminal 700 to perform some or all of the steps in the method embodiments described below.

The processor 710 is a control center of the memory terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by running or executing software programs and/or modules stored in the memory 720, and invoking data stored in the memory. The processor may be comprised of an integrated circuit (Integrated Circuit, simply referred to as an IC), for example, a single packaged IC, or may be comprised of a plurality of packaged ICs connected to the same function or different functions. For example, the processor 710 may include only a central processing unit (Central Processing Unit, simply CPU). In the embodiment of the invention, the CPU can be a single operation core or can comprise multiple operation cores.

And a communication module 730, configured to establish a communication channel, so that the storage terminal can communicate with other terminals. Receiving user data sent by other terminals or sending the user data to other terminals.

The present invention also provides a computer storage medium in which a program may be stored, which program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (random access memory, RAM), or the like.

Therefore, the invention can buffer the requests of the threads and related data, and forward the buffered requests based on two factors of buffer time and data volume, and can avoid delay caused by buffering the requests of the threads, and avoid too long occupation of DDR control right caused by too many single threads, too long waiting for reading or writing instructions or reduced efficiency or blocked state.

It will be apparent to those skilled in the art that the techniques of embodiments of the present invention may be implemented in software plus a necessary general purpose hardware platform. Based on such understanding, the technical solution in the embodiments of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium such as a U-disc, a mobile hard disc, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk or an optical disk, etc. various media capable of storing program codes, including several instructions for causing a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, etc.) to execute all or part of the steps of the method described in the embodiments of the present invention.

The same or similar parts between the various embodiments in this specification are referred to each other. In particular, for the terminal embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and reference should be made to the description in the method embodiment for relevant points.

In the several embodiments provided by the present invention, it should be understood that the disclosed systems and methods may be implemented in other ways. For example, the system embodiments described above are merely illustrative, e.g., the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with respect to each other may be through some interface, indirect coupling or communication connection of systems or modules, electrical, mechanical, or other form.

The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module.

Although the present invention has been described in detail by way of preferred embodiments with reference to the accompanying drawings, the present invention is not limited thereto. Various equivalent modifications and substitutions may be made in the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and it is intended that all such modifications and substitutions be within the scope of the present invention/be within the scope of the present invention as defined by the appended claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A memory read-write control method, characterized by comprising:

caching the request of the thread in the control device;

monitoring the cached request quantity of the thread;

2. The method of claim 1, wherein buffering requests for threads in the control device comprises:

allocating unique request cache addresses and data cache addresses for threads;

caching the request received from the thread to a request cache address;

3. The method according to claim 1, wherein the method further comprises:

analyzing the cached request type;

4. The method of claim 1, wherein monitoring the duration of the current time from the time of the previous execution request comprises:

and the time counted by the acquisition timer is output as the duration.

5. The method of claim 1, wherein the threshold determination of the number and the duration results in a threshold determination result, comprising:

presetting a time threshold and a quantity threshold;

6. The method according to claim 1, wherein the method further comprises:

7. The method of claim 1, wherein after forwarding the cached request to the memory, the method further comprises:

if the request is a read request, caching the data returned from the memory;

8. A memory read-write control method, characterized by comprising:

9. A terminal, comprising:

a memory for storing a memory read-write control program;

a processor for implementing the steps of the memory read-write control method according to any one of claims 1 to 7 when executing the memory read-write control program.

10. A computer readable storage medium storing a computer program, characterized in that the readable storage medium has stored thereon a memory read-write control program which, when executed by a processor, implements the steps of the memory read-write control method according to any one of claims 1 to 7.