CN114450788A - 用于电子构件的接触装置以及用于制造电子构件的方法 - Google Patents

用于电子构件的接触装置以及用于制造电子构件的方法 Download PDF

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CN114450788A
CN114450788A CN202080070731.7A CN202080070731A CN114450788A CN 114450788 A CN114450788 A CN 114450788A CN 202080070731 A CN202080070731 A CN 202080070731A CN 114450788 A CN114450788 A CN 114450788A
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wiring substrate
contact
metal
recess
upper side
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D·巴冈
C·拉梅尔
J·卢特纳
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Vitesco Technologies GmbH
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Abstract

本发明涉及一种用于电子构件的接触装置（1），其具有：‑至少一个键合带（20），该键合带用于与布线基底（2）的触点连接面（8）进行连接，和‑布线基底（2），该布线基底带有上侧面（4）和下侧面（6），其中，至少在布线基底（2）的上侧面（4）上设置有用于与键合带（20）进行接触的至少一个触点连接面（8），其中，触点连接面（8）布置在布线基底（2）的体积中的至少一个被金属填充的凹缺（10）上。

Description

用于电子构件的接触装置以及用于制造电子构件的方法
技术领域
本发明涉及一种用于电子构件的接触装置。本发明此外涉及用于制造电子构件的方法。
背景技术
从US 2012/0133052 A1、US 7,164,572 B1、EP 1 560 267 A1以及US 2017/0221814 A1已知用于电接触多层的基底的方法。
为了接触半导体构件的半导体元件、尤其为了接触功率半导体元件，部分地使用键合带，该键合带相比于键合线具有特别高的导电性能。为了布线基底的彼此间的接触、例如PCB与PCB的接触或者引脚框架之间的接触，也经常使用键合带。这类的键合带具有近似矩形的横截面，并且此外具有明显超过该键合带的厚度的宽度。这类的键合带能够例如借助于激光焊接而与布线基底的、例如PCB的触点连接面相连接。在此，典型地由铜构造而成的在基底上的触点连接面必须相对较厚，以便吸收必需的过程能量并且阻止布线基底的早期损坏。然而，布线基底的较厚的铜层总体上提高了用于布线基底的成本。此外，在厚的铜层的情况下必须设置印刷电路板上的更大的间距，从而使得在印刷电路板上实施特定的布局变得困难。
发明内容
本发明的任务是，提出一种用于电子构件的接触装置，该接触装置能够以特别简单且成本低廉的方式实现布线基底的触点连接面与键合带的接触。此外，应该提出一种用于制造具有这类的接触装置的电子构件的方法。
该任务通过独立权利要求的主题得以解决。有利的实施方式和改进方案是从属权利要求的主题。
按照本发明的一个方面，提出了一种用于电子构件的接触装置，该接触装置具有用于与布线基底的触点连接面相连接的至少一个键合带。此外，接触装置具有布线基底，该布线基底具有上侧面和下侧面，其中，至少在布线基底的上侧面上设置有用于与键合带接触的触点连接面，其中，该触点连接面布置在布线基底的体积中的至少一个被金属填充的凹缺上。
接触装置具有的优点是，在触点连接面下方的至少一个被金属填充的凹缺仅仅局部地且因此特别高效地提高了对焊接能量进行吸收的金属厚度。由此，在触点连接面下方存在足够的金属、尤其铜可供使用，以便吸收过程能量，其中，然而除此之外不必强化布线基底的导体电路厚度。这类的接触装置因此能够实现使用对于带状键合（Ribbonbonding）所需的过程能量并且此外由于仅仅局部地提高的金属量而能够成本低廉地制造。
“键合带”在当前的相互关系中尤其理解为金属带，该金属带设置用于与触点连接面尤其材料锁合地连接，并且该金属带的宽度是其高度的至少4倍大、例如至少8倍大。在此，该宽度在接触装置的装配后的状态中是在该键合带的延伸的状态中平行于触点连接面且垂直于该键合带的主延伸方向的尺寸，该高度是沿接触装置的面法线的方向。
按照本发明的一种实施方式，凹缺尤其朝远离触点连接面的方向逐渐缩小。凹缺例如在纵向剖视图中典型地锥形地构造，其中，其最大的直径紧挨着构造在触点连接面下方。概念“锥形地”在此也包括具有截锥形的纵向剖视图的凹缺。
在此，“纵向剖视图”理解为垂直于布线基底的上侧面穿过凹缺的剖面。“凹缺的最大的直径紧挨着构造在触点连接面下方”意味着，通过凹缺构成的锥体或者说截锥体的尖部远离布线基底的上侧面朝基底的下侧面的方向指向。
凹缺的这类的几何形状通过作为凹缺的制造方法的激光钻孔来引起。如已经得到证实的那样，激光钻孔是用于制造这类的凹缺的特别高效的可行方案。被激光钻孔的凹缺然而也能够具有与（典型的）锥形不同的几何形状并且能够是大概柱形的或者几乎球形的。
按照一种实施方式，布线基底多层地构造，并且在触点连接面下方将多个彼此上下地布置的、被金属填充的凹缺如此布置在布线基底的体积中，使得它们彼此连接。
这类的布线基底通过逐步地构造多个层来制造，并且一方面能够实现在多个层中的也更为复杂的重新布线，另一方面能够实现制造相对较厚的金属填充，以便吸收高的过程能量。
按照一种实施方式，在触点连接面下方将多个彼此并排地布置的、被金属填充的凹缺如此布置在布线基底的体积中，使得它们彼此连接。
对于这类的接触装置而言，相对较宽的、也就是说不仅圆环形的而且还被加宽的触点连接面可供使用，这尤其对于带式键合（Bandbonden）而言是有利的。对于触点连接面而言，能够在整个宽度的范围内将触点连接面下方的被金属填充的凹缺设置用于吸收过程能量。彼此并排地布置的、被金属填充的凹缺的数目在此依赖于触点连接面的宽度，该宽度又依赖于所使用的键合带的宽度。
至少一个凹缺的金属填充尤其具有铜或者由铜构成。
按照一种实施方式，被金属填充的凹缺的上侧面与布线基底的包围着该凹缺的上侧面齐平地构造。
在另一种实施方式中，接触装置具有金属层，该金属层包括触点连接面并且至少遮盖被金属填充的凹缺的上侧面。在该实施方式中设置了，金属层用触点连接面作为单独的层施敷在布线基底的上侧面上并且因此作为单独的层设置在被金属填充的凹缺上。
按照一种实施方式，键合带与至少一个触点连接面借助于激光焊接连接进行连接。激光焊接通常用作带状键合中的连接技术。
被金属填充的凹缺能够适宜地在其与触点连接面对置的侧面上被电绝缘层遮盖，该电绝缘层在一种改进方案中由布线基底的承载材料构成。按照一种实施方式，布线基底的下侧面通过电绝缘层、也就是说完全地闭合的电绝缘层构成。
当在布线基底的下侧面上应该安装用于运走热量的金属的冷却体时，这类的实施方式尤其在功率半导体构件中是有利的。在这种实施方式中，金属的凹缺没有完全地穿过布线基底。
按照本发明的一个方面，提出了一种带有所说明的接触装置的半导体构件，其中，在布线基底的上侧面上布置半导体元件，该半导体元件带有至少一个触点连接面，所述触点连接面借助于至少一个键合带与布线基底的触点连接面相连接。
半导体元件尤其能够是功率半导体元件。布线基底例如是印刷电路板，尤其是打印的印刷电路板（PCB，printed circuit board）、例如是多层的印刷电路板。在这种情况下，半导体构件能够是印刷电路板装置。
按照另一方面，提出了一种电子构件，该电子构件包括布线基底和至少一个另外的布线基底，其中，所述另外的布线基底的触点连接面借助于至少一个键合带与所述布线基底的触点连接面相连接。
按照本发明的一个方面，提出了一种用于制造电子构件的方法，该方法包括：提供具有上侧面和下侧面的布线基底，其中，布线基底具有由电绝缘的材料构成的基层（Matrix）以及嵌入其中的导体电路结构。此外，该方法具有：从上侧面出发借助于激光钻孔将凹缺引入到布线基底中、以及将金属填充引入到凹缺中。
此外，该方法包括：将触点连接面施敷到金属填充的上侧面上、以及将半导体元件的或者另外的布线基底的触点连接面与布线基底的触点连接面借助于键合带连接起来。
该方法具有结合接触装置已经说明的优点。
按照一种实施方式，多次彼此相继地执行：提供布线基底、从上侧面出发借助于激光钻孔将凹缺引入到布线基底中、以及将金属填充引入到凹缺中的步骤，以用于形成多层的布线基底。
在以这种方式构造了多层的布线基底之后，能够将至少一个半导体元件置放到最上方的层上。触点连接面同样施敷到最上方的层上。
对凹缺的引入尤其借助于激光钻孔或者机械钻孔来实现。
尤其借助于激光焊接将半导体元件的触点连接面借助于键合带与布线基底的触点连接面连接起来。
附图说明
本发明的实施方式在下文中根据示意性的附图被示例性地说明。其中：
图1示出了按照本发明的第一实施方式的接触装置的截面示图；
图2示出了按照图1的接触装置的俯视图；
图3示出了按照本发明的第二实施方式的接触装置的剖视图；
图4示出了按照本发明的第三实施方式的接触装置的剖视图；
图5示出了按照本发明的第四实施方式的接触装置的剖视图；
图6示出了按照本发明的第五实施方式的接触装置的剖视图；并且
图7-11示出了用于制造按照本发明的实施方式的接触装置的方法的步骤。
具体实施方式
图1示出了一种接触装置，该接触装置用于半导体构件、然而尤其不仅用于功率半导体构件并且/或者用于包括至少两个彼此连接的布线基底的电子构件。接触装置1包括布线基底2，该布线基底带有上侧面4和与该上侧面4对置的下侧面6。在该布线基底2的上侧面4上布置有至少一个触点连接面8，该触点连接面借助于至少一个键合带20进行电接触。
触点连接面8布置在被金属填充的凹缺10上，该凹缺构造在布线基底20中。被金属填充的凹缺10在图1所示出的第一实施方式中具有锥形，其中，锥体的尖部12远离上侧面4朝着下侧面6的方向指向，从而锥体的基面构成布线基底2的上侧面4的一部分。在该基面上构造有触点连接面8。
图2示出了按照图1的接触装置1的俯视图。在该视图中能够看出的是，键合带20具有相对较大的宽度b1、b2，在该视图中示出了这些键合带中的两个彼此并排地键合到触点连接面8上的键合带。在此，该宽度b1、b2尤其比键合带20的厚度d大多倍。
触点连接面8在本实施方式中具有矩形。为了在该触点连接面的整个宽度的范围内吸收键合时出现的热量，将多个凹缺10彼此并排地布置在触点连接面8下方。以这种方式能够在键合多个被彼此并排地键合的键合带时吸收该热量，其中也能够设置三个或者更多个键合带。
图3示出了按照第二实施方式的接触装置1。该第二实施方式与在图1中所示出的实施方式区别在于，在布线基底2中设置至少一个导电层14。在所示出的实施方式中，并非导电层14而是电绝缘的材料在布线基底2的下侧面6上裸露出来。
在图3中所示出的实施方式中，被金属填充的凹缺10伸展直到导电层14上并且与之接触。以这种方式导电层14同样用于运走并且分开热量。然而，依赖于布线基底2的布局也能够有利的是，在被金属填充的凹缺10与导电层14之间避免电接触。在这种情况下被金属填充的凹缺10在导电层14的上方终止。
图4示出了按照第三实施方式的接触装置1。该第三实施方式与在图3中所示出的第二实施方式区别在于，布线基底2具有多个布线层16。为了能够特别高效地运走热量，被金属填充的凹缺10布置在每个布线层16中更确切地说如此布置，使得该凹缺以堆叠的方式处于触点连接面8下方。以这种方式能够使得热量被触点连接面8吸收并且通过多个层运走和分配。
图5示出了接触装置1的第四实施方式，该第四实施方式与在图4中所示出的实施方式区别在于，被金属填充的凹缺18不是锥形的，而是柱形的。被金属填充的凹缺18的这样的几何形状尤其能够通过机械钻孔来制造。
图6示出了按照本发明的第五实施方式的接触装置1。按照该实施方式，布线基底2由多个层16、16`构成，它们分别具有不同的被金属填充的凹缺10、18。在此，这些被金属填充的凹缺10、18能够不仅用于电接触而且也用于运走热量。
在图6中所示出的实施方式中，被金属填充的凹缺10在布线基底2的下侧面6处裸露出来。这在下述情况下可能是有问题的，即：布线基底2应该紧挨着施敷到冷却体上，而不与之电接触。在这种情况下能够在布线基底2与冷却体之间引入绝缘层。
在图4至6中处于更深处的凹缺10、18能够如所示出的那样用金属来填充，然而它们也能够不进行填充。
图7-11示出了用于制造用于接触装置1的布线基底2的方法的步骤。
图7示出了布线基底2，其带有上侧面4和与该上侧面对置的下侧面6，其中，从上侧面4出发将凹缺22引入到布线基底中。所述凹缺22的引入借助于激光钻孔来进行，这通过箭头24表示。激光钻孔的方法典型地然而并非强制地导致凹缺22的锥形的或者说截锥形的几何形状。
图8示出了在将金属填充引入到凹缺22中之后以用于形成被金属填充的凹缺10的布线基底2。
图9示出了在将另一个层2`施敷到布线基底2的上侧面4上之后的布线基底2。
图10示出了从上侧面4`出发借助于激光钻孔将凹缺22引入到另外的层2`中。此外，在图10中用虚线示出表示了内部的触点连接面80、即所谓的内层衬垫（Innenlagenpad）。这类的内部的触点连接面80同样能够集成到布线基底2中。
图11示出了在将金属的触点连接面8施敷到被金属填充的凹缺10`、10上之后的布线基底2、2`。
利用根据图7-11所说明的方法能够制造多层的布线基底2，正如该布线基底也在图4-6中所示出的那样。

Claims (15)

1. 用于电子构件的接触装置（1），其具有
- 至少一个键合带（20），该键合带用于与布线基底（2）的触点连接面（8）进行连接，和
- 布线基底（2），该布线基底带有上侧面（4）和下侧面（6），其中，至少在所述布线基底（2）的上侧面（4）上设置有用于与所述键合带（20）进行接触的至少一个触点连接面（8），
其中，所述触点连接面（8）布置在所述布线基底（2）的体积中的至少一个被金属填充的凹缺（10）上。
2.根据权利要求1所述的接触装置（1），其中，所述被金属填充的凹缺（10）在其与所述触点连接面（8）对置的侧面上被电绝缘层遮盖。
3.根据权利要求1或者2所述的接触装置（1），其中，所述凹缺（2）逐渐缩小，从而该凹缺尤其在纵向剖视图中锥形地构造，其中，该凹缺的最大的直径紧挨着构造在所述触点连接面（8）下方。
4.根据上述权利要求中任一项所述的接触装置（1），其中，所述布线基底（2）多层地构造，并且在所述触点连接面（8）下方将多个彼此上下地布置的、被金属填充的凹缺（10）如此布置在所述布线基底（2）的体积中，从而使得它们彼此连接。
5.根据上述权利要求中任一项所述的接触装置（1），其中，在所述触点连接面（8）下方将多个彼此并排地布置的、被金属填充的凹缺（10）如此布置在所述布线基底（2）的体积中，从而使得它们彼此连接。
6.根据上述权利要求中任一项所述的接触装置（1），其中，至少一个凹缺（10）的金属填充具有铜或者由铜构成。
7.根据上述权利要求中任一项所述的接触装置（1），其中，所述被金属填充的凹缺（10）的上侧面与所述布线基底（2）的包围着所述凹缺的上侧面（4）齐平地构造，并且/或者具有所述触点连接面（8）的金属层至少遮盖所述被金属填充的凹缺（10）的上侧面。
8.根据上述权利要求中任一项所述的接触装置（1），其中，所述键合带（20）与所述至少一个触点连接面（8）借助于激光焊接连接进行连接。
9.根据上述权利要求中任一项所述的接触装置（1），其中，所述布线基底（2）的下侧面（6）通过电绝缘层来构成。
10.具有根据上述权利要求中任一项所述的接触装置（1）的半导体构件，
其中，在布线基底（2）的上侧面（4）上布置有至少一个半导体元件，该半导体元件带有至少一个触点连接面，所述触点连接面借助于至少一个键合带（20）与所述布线基底（2）的触点连接面（8）相连接。
11.根据权利要求10所述的半导体构件，
其中，所述至少一个半导体元件构造为功率半导体元件。
12.具有根据权利要求1至9中任一项所述的接触装置（1）的电子构件，
其包括布线基底（2）和至少一个另外的布线基底，其中，所述另外的布线基底的触点连接面借助于至少一个键合带（20）与所述布线基底（2）的触点连接面（8）相连接。
13.用于制造根据权利要求10至12中任一项所述的电子构件的方法，所述方法具有下述步骤：
- 提供带有上侧面（4）和下侧面（6）的布线基底（2），其中，所述布线基底（2）具有由电绝缘的材料构成的基层以及嵌入其中的导体电路结构；
- 借助于激光钻孔或者机械钻孔从所述上侧面（4）出发将凹缺（22）引入到所述布线基底（2）中；
- 将金属填充引入到所述凹缺（22）中以用于形成被金属填充的凹缺（10）；
- 将触点连接面（8）施敷到所述金属填充的上侧面上；
- 将半导体元件的或者另外的布线基底的触点连接面与所述触点连接面（8）借助于至少一个键合带（20）连接起来。
14.根据权利要求13所述的方法，
其中，多次执行提供布线基底（2）、借助于激光钻孔或者机械钻孔从所述上侧面（4）出发将凹缺（22）引入到所述布线基底（2）中、以及将金属填充引入到所述凹缺（22）中的步骤，以用于形成多层的布线基底（2）。
15.根据权利要求13至14中任一项所述的方法，
其中，借助于激光焊接来实现将半导体元件的或者另外的布线基底的触点连接面与所述触点连接面（8）借助于所述键合带（20）连接起来。
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Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213422A (ja) * 1995-02-07 1996-08-20 Mitsubishi Electric Corp 半導体装置およびそのボンディングパッド構造
CA2455024A1 (en) * 2003-01-30 2004-07-30 Endicott Interconnect Technologies, Inc. Stacked chip electronic package having laminate carrier and method of making same
JP2004281966A (ja) * 2003-03-19 2004-10-07 Ricoh Co Ltd 半導体装置及び半導体装置の製造方法
JP4170137B2 (ja) * 2003-04-24 2008-10-22 新光電気工業株式会社 配線基板及び電子部品実装構造
EP1560267A1 (en) 2004-01-29 2005-08-03 Kingston Technology Corporation Integrated multi-chip chip scale package
KR100664500B1 (ko) * 2005-08-09 2007-01-04 삼성전자주식회사 돌기부를 갖는 메탈 랜드를 구비하는 인쇄회로기판 및 그의제조방법
US7164572B1 (en) 2005-09-15 2007-01-16 Medtronic, Inc. Multi-path, mono-polar co-fired hermetic electrical feedthroughs and methods of fabrication therfor
DE102006033222B4 (de) * 2006-07-18 2014-04-30 Epcos Ag Modul mit flachem Aufbau und Verfahren zur Bestückung
DE102006037118B3 (de) * 2006-08-07 2008-03-13 Infineon Technologies Ag Halbleiterschaltmodul für Bordnetze mit mehreren Halbleiterchips, Verwendung eines solchen Halbleiterschaltmoduls und Verfahren zur Herstellung desselben
US20090032946A1 (en) * 2007-08-01 2009-02-05 Soo Gil Park Integrated circuit
US20100085130A1 (en) * 2008-10-03 2010-04-08 Toyota Motor Engineering & Manufacturing North America, Inc. Manufacturable tunable matching network for wire and ribbon bond compensation
TW201030916A (en) * 2009-02-11 2010-08-16 Advanced Semiconductor Eng Pad and package structure using the same
KR101564070B1 (ko) * 2009-05-01 2015-10-29 삼성전자주식회사 인쇄 회로 기판 및 이를 이용한 반도체 패키지
US8692364B2 (en) 2009-08-07 2014-04-08 Nec Corporation Semiconductor device and method for manufacturing the same
US9349706B2 (en) * 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
JP6133854B2 (ja) * 2012-05-30 2017-05-24 京セラ株式会社 配線基板および電子装置
KR101420499B1 (ko) * 2012-07-26 2014-07-16 삼성전기주식회사 적층형 코어리스 인쇄회로기판 및 그 제조 방법
US10510656B2 (en) 2014-07-30 2019-12-17 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device
JP2016142615A (ja) 2015-02-02 2016-08-08 学校法人北里研究所 電磁波検出装置、電磁波検出方法及び電磁波検出装置の製造方法
JP6505521B2 (ja) * 2015-06-26 2019-04-24 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
WO2017171813A1 (en) * 2016-03-31 2017-10-05 Intel Corporation Electromagnetic interference shielding for semiconductor packages using bond wires
KR102442620B1 (ko) * 2018-01-02 2022-09-13 삼성전자 주식회사 반도체 메모리 패키지
KR102597994B1 (ko) * 2018-12-06 2023-11-06 삼성전자주식회사 배선 구조체 및 이의 형성 방법

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