CN114446806A - 裸片到裸片的互连电路中半导体组件、集成电路封装方法 - Google Patents

裸片到裸片的互连电路中半导体组件、集成电路封装方法 Download PDF

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Publication number
CN114446806A
CN114446806A CN202111630031.1A CN202111630031A CN114446806A CN 114446806 A CN114446806 A CN 114446806A CN 202111630031 A CN202111630031 A CN 202111630031A CN 114446806 A CN114446806 A CN 114446806A
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CN
China
Prior art keywords
module
die
packaging
solder balls
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111630031.1A
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English (en)
Chinese (zh)
Inventor
冯杰
夏君
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Pango Microsystems Co Ltd
Original Assignee
Shenzhen Pango Microsystems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Pango Microsystems Co Ltd filed Critical Shenzhen Pango Microsystems Co Ltd
Priority to CN202111630031.1A priority Critical patent/CN114446806A/zh
Publication of CN114446806A publication Critical patent/CN114446806A/zh
Priority to PCT/CN2022/109428 priority patent/WO2023124068A1/fr
Priority to JP2024525520A priority patent/JP2024536616A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN202111630031.1A 2021-12-28 2021-12-28 裸片到裸片的互连电路中半导体组件、集成电路封装方法 Pending CN114446806A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202111630031.1A CN114446806A (zh) 2021-12-28 2021-12-28 裸片到裸片的互连电路中半导体组件、集成电路封装方法
PCT/CN2022/109428 WO2023124068A1 (fr) 2021-12-28 2022-08-01 Procédé d'encapsulation pour composant à semi-conducteur et circuit intégré dans un circuit d'interconnexion entre puces
JP2024525520A JP2024536616A (ja) 2021-12-28 2022-08-01 ダイツーダイの相互接続回路における半導体アセンブリ、集積回路のパッケージ方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111630031.1A CN114446806A (zh) 2021-12-28 2021-12-28 裸片到裸片的互连电路中半导体组件、集成电路封装方法

Publications (1)

Publication Number Publication Date
CN114446806A true CN114446806A (zh) 2022-05-06

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ID=81365272

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111630031.1A Pending CN114446806A (zh) 2021-12-28 2021-12-28 裸片到裸片的互连电路中半导体组件、集成电路封装方法

Country Status (3)

Country Link
JP (1) JP2024536616A (fr)
CN (1) CN114446806A (fr)
WO (1) WO2023124068A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023124068A1 (fr) * 2021-12-28 2023-07-06 深圳市紫光同创电子有限公司 Procédé d'encapsulation pour composant à semi-conducteur et circuit intégré dans un circuit d'interconnexion entre puces

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117236263B (zh) * 2023-11-15 2024-02-06 之江实验室 一种多芯粒互联仿真方法、装置、存储介质及电子设备

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8698323B2 (en) * 2012-06-18 2014-04-15 Invensas Corporation Microelectronic assembly tolerant to misplacement of microelectronic elements therein
KR101684787B1 (ko) * 2015-02-13 2016-12-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 반도체 패키지 디바이스 및 그 형성 방법
US9882562B1 (en) * 2016-12-07 2018-01-30 Xilinx, Inc. Rotated integrated circuit die and chip packages having the same
US11182532B2 (en) * 2019-07-15 2021-11-23 Taiwan Semiconductor Manufacturing Co., Ltd. Hierarchical density uniformization for semiconductor feature surface planarization
DE102020131125A1 (de) * 2020-04-29 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterpaket und Verfahren zum Herstellen desselben
DE102020130996A1 (de) * 2020-05-01 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-package und verfahren zu dessen herstellung
CN114446806A (zh) * 2021-12-28 2022-05-06 深圳市紫光同创电子有限公司 裸片到裸片的互连电路中半导体组件、集成电路封装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023124068A1 (fr) * 2021-12-28 2023-07-06 深圳市紫光同创电子有限公司 Procédé d'encapsulation pour composant à semi-conducteur et circuit intégré dans un circuit d'interconnexion entre puces

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Publication number Publication date
WO2023124068A1 (fr) 2023-07-06
JP2024536616A (ja) 2024-10-04

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