CN114446806A - Semiconductor assembly in die-to-die interconnection circuit and packaging method of integrated circuit - Google Patents
Semiconductor assembly in die-to-die interconnection circuit and packaging method of integrated circuit Download PDFInfo
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- CN114446806A CN114446806A CN202111630031.1A CN202111630031A CN114446806A CN 114446806 A CN114446806 A CN 114446806A CN 202111630031 A CN202111630031 A CN 202111630031A CN 114446806 A CN114446806 A CN 114446806A
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- module
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
Abstract
The invention provides a method for packaging a semiconductor assembly and an integrated circuit in an interconnection circuit from a bare chip to the bare chip, which comprises the following steps: for any module in the hardmac in the target interconnection circuit, if the module is packaged by COWOS or FOP, the module uses the microbumps in the packaging process, and the spherical center distance between any two adjacent microbumps in the horizontal direction is not less than 40 um. According to the packaging method of the semiconductor assembly and the integrated circuit in the interconnection circuit from the bare chip to the bare chip, disclosed by the invention, for the same IP, COWOS or FOP packaging can be realized on the IP on the premise of not changing an IP structure, one process only needs to make a die-die interconnection IP to meet different packaging modes, and the development progress and the development cost of a chip are reduced.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a packaging method of a semiconductor component and an integrated circuit in an interconnection circuit from a bare chip to the bare chip.
Background
With the coming of the aftermath era, the Chiplet becomes an increasingly important and extensive solution, the concept of the Chiplet is simple, namely, the reuse of the silicon chip level, from the system end, the complex functions are firstly decomposed, then a plurality of bare chips which have single specific functions and can be mutually modularly assembled are developed, the functions of data storage, calculation, signal processing, data stream management and the like are realized, and finally a chip network of the Chiplet is established on the basis of the functions.
Generally, the interconnection circuit is composed of an integrated circuit and/or a semiconductor device, a specific connection mode can be determined according to actual requirements, specific components and elements contained in the interconnection circuit are different in different actual conditions, and one interconnection circuit can be called as an IP. A Chip generally adopts multiple-Chip modules (MCM for short), fan-out packages (FOP for short), Chip on wafer packages (COWOS for short), and other packaging methods, where the connection width, the distance between lines, the size of a bump or a micro-bump, and the distance between two adjacent bump centers required by different packaging methods are different, so that multiple die-die interconnection IPs are required to meet the requirements of different packaging methods, and the development progress and development cost of the Chip are affected.
Disclosure of Invention
The invention provides a packaging method of a semiconductor assembly and an integrated circuit in an interconnection circuit from a bare chip to the bare chip, and mainly aims to realize multiple different packaging modes on one interconnection circuit, improve the development progress of a chip and reduce the development cost.
The embodiment of the invention provides a method for packaging a semiconductor assembly and an integrated circuit in an interconnection circuit from a bare chip to the bare chip, which comprises the following steps:
for any module in the hardmac in the target interconnection circuit, if the module is packaged by COWOS or FOP, the module uses the microbumps in the packaging process, and the spherical center distance between any two adjacent microbumps in the horizontal direction is not less than 40 um.
Preferably, the distance between the centers of any two adjacent micro bumps in the vertical direction is 80 um.
Preferably, any one of the modules transmits 52 signals, including 2 differential clock signals.
Preferably, a single data rate transmission mode is used, with a transmission rate of 2.5 Gbps.
Preferably, if any module uses an MCM packaging mode, any module transmits 26 signals, on the basis of any module COWOS or FOP packaging, a plurality of solder balls are disposed on any module, the solder balls are disposed on corresponding micro bumps, and the solder balls are connected to the micro bumps representing the signals in the corresponding micro bumps through rewiring, and the sum of the number of the solder balls and the number of the micro bumps remaining in any module to represent the signals is 26, and the distance between the centers of any two solder balls is 160 um.
Preferably, the solder ball is a flip-chip solder ball.
Preferably, there are 2 differential clock signals in any of the modules.
Preferably, a double data rate transmission mode is used, with a transmission rate of 5 Gbps.
Preferably, any of the modules is formed of semiconductor components and/or integrated circuits.
According to the packaging method of the semiconductor assembly and the integrated circuit in the interconnection circuit from the bare chip to the bare chip, for the same IP, COWOS or FOP packaging can be achieved on the IP on the premise that the IP structure is not changed, one process only needs to make a die-die interconnection IP to meet different packaging modes, and the development progress and the development cost of a chip are reduced.
Drawings
FIG. 1 is a schematic diagram of a die-to-die interconnect circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an embodiment of the present invention employing COWOS or FOP packaging;
FIG. 3 is a schematic diagram of an embodiment of the present invention in which MCM packaging is used;
fig. 4 is a schematic diagram of Bump pitch when an MCM packaging method is adopted in the embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is a schematic diagram of a die-to-die interconnect circuit structure according to an embodiment of the present invention, where as shown in fig. 1, in an embodiment of the present invention, a die includes multiple IPs, an IP structure includes a digital control module and a hard core, the hard core includes a transmitting module, an IO calibration module and a receiving module, and the transmitting module, the IO calibration module and the receiving module are respectively connected to the digital control module and can communicate with the digital module. Generally, a digital control module is developed and integrated by a chip design project, and the embodiment of the invention mainly aims at a packaging mode of a hard core.
In the embodiment of the present invention, the digital control module and the hard core may be a circuit formed by a semiconductor device alone, may be an integrated circuit die, or may be a combination of a semiconductor device and an integrated circuit die.
Fig. 2 is a schematic diagram of an embodiment of the present invention that uses a COWOS or FOP package, and as shown in fig. 2, the method includes:
for any module in the hardmac in the target interconnection circuit, if the module is packaged by COWOS or FOP, the module uses the microbumps in the packaging process, and the spherical center distance between any two adjacent microbumps in the horizontal direction is not less than 40 um.
In the embodiment of the present invention, a receiving module and a sending module are taken as any one of the modules for explanation, and the diagram shows a schematic diagram of the sending module and the receiving module adopting a COWOS package or an FOP package, where a bump used in soldering on the sending module and the receiving module is a micro bump, the micro bump is a circle in the diagram, and has 4 meanings, which respectively represent a power end, a ground end, a signal end and a clock signal end, where the micro bump is a micro-bump, and a distance between spherical centers of any two adjacent micro bumps in a horizontal direction is 40um at a minimum, that is, the micro-bump pitch is 40 um. As long as this condition is satisfied, the transmitting module and the receiving module can be subjected to the COWOS package or the FOP package. The micro-bump pitch can be finely adjusted based on the package trace requirements to meet the specification requirements of different projects.
It should be noted that in the COWOS package or the FOP package, the width of the line connecting two microbumps in the figure and the distance between the lines can be adjusted according to actual needs.
According to the packaging method of the semiconductor assembly and the integrated circuit in the interconnection circuit from the bare chip to the bare chip, disclosed by the invention, for the same IP, COWOS or FOP packaging can be realized on the IP on the premise of not changing an IP structure, one process only needs to make a die-die interconnection IP to meet different packaging modes, and the development progress and the development cost of a chip are reduced.
On the basis of the above embodiment, preferably, the sphere center distance between any two adjacent micro bumps in the vertical direction is 80 um.
In the vertical direction, the distance between the centers of any two adjacent micro-bumps is 80 um.
On the basis of the above embodiment, preferably, any one of the modules transmits 52 signals, including 2 differential clock signals.
Referring to the transmitting module and the receiving module, each of the micro-bumps representing signals transmits one signal, that is, a white circle in the receiving module or the transmitting module in the figure, the number of the white circles is 52, and 2 of the micro-bumps represent differential clock signals, that is, a black circle in the receiving module or the transmitting module in the figure.
On the basis of the above embodiment, it is preferable that a transmission mode of a single data rate is adopted, and the transmission rate is 2.5 Gbps.
Specifically, the module adopts a transmission module with single data rate when transmitting data, and the transmission rate is 2.5 Gbps.
Fig. 3 is a schematic diagram of an MCM package in an embodiment of the present invention, as shown in fig. 3, on the basis of the above embodiment, preferably, if any module uses an MCM package, the any module transmits 26 signals, on the basis of the cog or FOP package of any module, a plurality of solder balls are disposed on any module, the solder balls are disposed on corresponding micro bumps, the solder balls are connected to the micro bumps representing the signals in the corresponding micro bumps through rewiring, a sum of the number of the solder balls and the number of the remaining micro bumps representing the signals in any module is 26, and a distance between centers of any two solder balls is 160 um.
In the embodiment of the invention, if the sending module or the receiving module needs to use an MCM packaging mode, the sending module or the receiving module is directly modified on the basis of the original COWOS or FOP packaging mode, specifically, a certain number of solder balls are added on the module, a white large circle in the figure is the solder ball, the solder ball and a signal end can be connected through rewiring, in addition, the number of the solder balls and the number of unconnected signal ends are 26, each solder ball and each unconnected signal end independently transmit a signal, and the unconnected signal end refers to the signal end which is not connected with the solder ball. Fig. 4 is a schematic diagram of Bump pitch when an MCM packaging method is adopted in the embodiment of the present invention, and as shown in fig. 4, the distance between the centers of any two adjacent solder balls is 160um, that is, the Bump pitch in the diagram is 160 um.
In the embodiment of the invention, when MCM package is required to be realized, a certain number of solder balls meeting certain requirements are added on the COWOS or FOP package without modifying an IP structure again, so that common COWOS, FOP and MCM package can be realized through one IP.
On the basis of the above embodiment, preferably, the solder ball is a flip-chip solder ball.
Specifically, the solder ball is a flip-Chip bonding solder ball, the flip-Chip bonding is a Controlled plated Chip Connection, abbreviated as C4, the solder ball is solderump, and the flip-Chip bonding solder ball is a C4 solder ball. In the implementation, the FANOUT technique is used to enlarge the bare chip, and the signal terminal and the C4 solder ball are connected by re-wiring.
On the basis of the above embodiment, preferably, there are 2 differential clock signals in any one of the modules.
Similarly, there are 2 differential clock signals in the package, which are the black circles in the figure.
On the basis of the above-described embodiment, it is preferable to adopt a double data rate transmission mode, with a transmission rate of 5 Gbps.
In the embodiment of the invention, the Bump pitch can be finely adjusted based on the package routing requirement so as to meet the specification requirements of different projects.
To improve high speed rate die-die interconnect reliability, IP needs to support and design integration of the following functions:
the IP supports the adjustment of the IO output impedance, and the adjustable range is 20-50 ohm.
The gear of an On Die Termination (ODT for short) of the IP supporting IO is adjustable, and the adjustable range is 60-480 ohm.
IP supports auto-calibration calculations.
The IP supports a Per-bit deskew function, and supports thickness adjustment and automatic adjustment.
The package routing is controlled in equal length, and short lines and few via holes are routed as much as possible.
And the packaging wiring needs SI simulation, the width and the spacing of iterative wiring are optimized through simulation, and the signal quality is ensured.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein.
Claims (9)
1. A method of packaging a semiconductor assembly, an integrated circuit, in a die-to-die interconnect circuit, comprising:
for any module in a hard core in a target interconnection circuit, if the module is packaged by COWOS or FOP, the module uses the micro-bumps in the packaging process, and the spherical center distance between any two adjacent micro-bumps in the horizontal direction is not less than 40 um.
2. The method of claim 1, wherein the distance between the centers of any two adjacent micro bumps in the vertical direction is 80 μm.
3. The method of claim 1, wherein the any module transmits 52 signals, including 2 differential clock signals.
4. The method of claim 1, wherein a single data rate transmission mode is used, and wherein the transmission rate is 2.5 Gbps.
5. The method as claimed in claim 1, wherein if any module uses MCM package, any module transmits 26 signals, on the basis of COWOS or FOP package of any module, a plurality of solder balls are disposed on any module, the solder balls are disposed on corresponding micro-bumps, the solder balls and the micro-bumps representing signals in the corresponding micro-bumps are connected by rewiring, the sum of the number of the solder balls and the number of the remaining micro-bumps representing signals in any module is 26, and the distance between the centers of any two solder balls is 160 μm.
6. The method of claim 5, wherein the solder balls are flip-chip solder balls.
7. The method of claim 5, wherein there are 2 differential clock signals in any module.
8. The method of claim 5 wherein a double data rate transmission mode is used, with a transmission rate of 5 Gbps.
9. The method of packaging a semiconductor assembly and an integrated circuit in a die-to-die interconnect circuit according to any of claims 1 to 8, wherein any of the modules is formed of a semiconductor assembly and/or an integrated circuit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111630031.1A CN114446806A (en) | 2021-12-28 | 2021-12-28 | Semiconductor assembly in die-to-die interconnection circuit and packaging method of integrated circuit |
| PCT/CN2022/109428 WO2023124068A1 (en) | 2021-12-28 | 2022-08-01 | Packaging method for semiconductor component and integrated circuit in die-die interconnection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111630031.1A CN114446806A (en) | 2021-12-28 | 2021-12-28 | Semiconductor assembly in die-to-die interconnection circuit and packaging method of integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114446806A true CN114446806A (en) | 2022-05-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111630031.1A Pending CN114446806A (en) | 2021-12-28 | 2021-12-28 | Semiconductor assembly in die-to-die interconnection circuit and packaging method of integrated circuit |
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| CN (1) | CN114446806A (en) |
| WO (1) | WO2023124068A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023124068A1 (en) * | 2021-12-28 | 2023-07-06 | 深圳市紫光同创电子有限公司 | Packaging method for semiconductor component and integrated circuit in die-die interconnection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117236263B (en) * | 2023-11-15 | 2024-02-06 | 之江实验室 | Multi-core interconnection simulation method and device, storage medium and electronic equipment |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8698323B2 (en) * | 2012-06-18 | 2014-04-15 | Invensas Corporation | Microelectronic assembly tolerant to misplacement of microelectronic elements therein |
| KR101684787B1 (en) * | 2015-02-13 | 2016-12-08 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor package device and method of forming same |
| US9882562B1 (en) * | 2016-12-07 | 2018-01-30 | Xilinx, Inc. | Rotated integrated circuit die and chip packages having the same |
| US11182532B2 (en) * | 2019-07-15 | 2021-11-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hierarchical density uniformization for semiconductor feature surface planarization |
| DE102020131125A1 (en) * | 2020-04-29 | 2021-11-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of making the same |
| DE102020130996A1 (en) * | 2020-05-01 | 2021-11-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING IT |
| CN114446806A (en) * | 2021-12-28 | 2022-05-06 | 深圳市紫光同创电子有限公司 | Semiconductor assembly in die-to-die interconnection circuit and packaging method of integrated circuit |
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2021
- 2021-12-28 CN CN202111630031.1A patent/CN114446806A/en active Pending
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2022
- 2022-08-01 WO PCT/CN2022/109428 patent/WO2023124068A1/en unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023124068A1 (en) * | 2021-12-28 | 2023-07-06 | 深圳市紫光同创电子有限公司 | Packaging method for semiconductor component and integrated circuit in die-die interconnection circuit |
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| WO2023124068A1 (en) | 2023-07-06 |
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