CN114429909A - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Semiconductor packaging method and semiconductor packaging structure Download PDF

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Publication number
CN114429909A
CN114429909A CN202011187616.6A CN202011187616A CN114429909A CN 114429909 A CN114429909 A CN 114429909A CN 202011187616 A CN202011187616 A CN 202011187616A CN 114429909 A CN114429909 A CN 114429909A
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chip
conductive
layer
front surface
forming
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Chinese (zh)
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霍炎
涂旭峰
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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Priority to CN202011187616.6A priority Critical patent/CN114429909A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

The application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the following steps: providing a first chip to be packaged, wherein the first chip is provided with a front surface, and a welding pad is arranged on the front surface of the first chip; arranging a second chip to be packaged and a conductive column on the front surface of the first chip; the conductive column is electrically connected with the welding pad of the first chip; the second chip is provided with a front surface, the front surface of the second chip deviates from the first chip, and a welding pad is arranged on the front surface of the second chip; forming an encapsulating layer and a conductive structure, wherein the encapsulating layer encapsulates the first chip and the second chip; the conductive structure comprises a rewiring layer located on one side, away from the first chip, of the encapsulating layer and a first conductive part penetrating through the encapsulating layer and electrically connecting the welding pad of the second chip to the rewiring layer, the encapsulating layer encapsulates the side part of the first conductive part, and the rewiring layer electrically connects the conductive column with the first conductive part.

Description

Semiconductor packaging method and semiconductor packaging structure
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
Background
In semiconductor packaging technology, chips with different functions are often packaged in a package structure to form a specific role, so as to obtain a multi-chip module (MCM), which has advantages of high performance, multi-functionalization and the like.
With the development of miniaturization and light weight of electronic equipment, a multi-chip module with a compact structure and a small volume is favored by more and more markets. Therefore, how to reduce the volume of the multi-chip module becomes a hot point of research.
Disclosure of Invention
A first aspect of embodiments of the present application provides a semiconductor packaging method. The semiconductor packaging method comprises the following steps:
providing a first chip to be packaged, wherein the first chip is provided with a front surface, and a welding pad is arranged on the front surface of the first chip;
arranging a second chip to be packaged and a conductive column on the front surface of the first chip; the conductive column is electrically connected with the welding pad of the first chip; the second chip is provided with a front surface, the front surface of the second chip deviates from the first chip, and a welding pad is arranged on the front surface of the second chip;
forming an encapsulating layer and a conductive structure, wherein the encapsulating layer encapsulates the first chip and the second chip; the conductive structure comprises a rewiring layer and a first conductive part, wherein the rewiring layer is located on one side, away from the first chip, of the encapsulating layer, the first conductive part penetrates through the encapsulating layer and electrically connects the welding pad of the second chip to the rewiring layer, and the rewiring layer electrically connects the conductive column and the first conductive part.
In one embodiment, the forming the encapsulation layer and the conductive structure includes:
forming an encapsulation layer;
forming a first opening exposing a pad of the second chip on the encapsulation layer;
and forming a conductive structure, wherein the conductive structure comprises a first conductive part positioned in the first opening and a rewiring layer positioned on one side of the encapsulating layer, which is far away from the second chip.
In one embodiment, a distance from a side of the conductive pillar facing away from the first chip to the first chip is smaller than a distance from a side of the encapsulation layer facing away from the first chip to the first chip; the forming of the encapsulating layer and the conductive structure further comprises: forming a second opening corresponding to the conductive pillar on the encapsulating layer; the conductive structure further comprises a second conductive part located in the second opening, and the second conductive part electrically connects the conductive pillar and the redistribution layer;
alternatively, the first and second electrodes may be,
the surface of the conductive column, which is far away from the first chip, exposes the encapsulating layer, and the surface of the conductive column, which is far away from the first chip, is in direct contact with the rewiring layer.
In one embodiment, the forming the encapsulation layer and the conductive structure includes:
arranging a first conductive part on the front surface of the second chip, wherein the first conductive part is electrically connected with a welding pad of the second chip;
forming an encapsulating layer, wherein the encapsulating layer is exposed out of the surfaces of the first conductive part and the conductive column, which are far away from the first chip;
and forming a rewiring layer on the surface of the encapsulating layer, which is far away from the first chip.
In one embodiment, the disposing a first conductive part on the front surface of the second chip includes:
fixing a preformed first conductive part on the front surface of the second chip; or forming a first conductive material layer on the front surface of the second chip by depositing a conductive material, and etching the first conductive material layer to form a first conductive part.
In one embodiment, the disposing the second chip to be packaged and the conductive pillars on the front surface of the first chip includes:
arranging a preformed conductive column and a second chip to be packaged on the front surface of the first chip;
alternatively, the first and second electrodes may be,
the front of first chip sets up treats second chip and the electrically conductive post of encapsulation, includes:
forming a second conductive material layer on the front surface of the first chip by depositing a conductive material;
etching the second conductive material layer to form a conductive column electrically connected with the welding pad of the first chip;
and mounting the second chip on the front surface of the first chip.
In one embodiment, the conductive structure further includes a pin located on a side of the redistribution layer facing away from the first chip;
after the forming of the encapsulating layer and the conductive structure, the semiconductor packaging method further comprises: forming a dielectric layer, wherein the dielectric layer covers the rewiring layer, and the surface of one side of the pin, which is far away from the first chip, is exposed out of the dielectric layer;
and/or the presence of a gas in the gas,
after the forming of the encapsulating layer and the conductive structure, the semiconductor packaging method further comprises:
and forming a tin-plated layer on one side of the conductive structure, which faces away from the encapsulating layer.
A second aspect of an embodiment of the present application provides a semiconductor package structure, including:
the chip packaging structure comprises a first chip to be packaged, wherein the first chip is provided with a front surface, and a welding pad is arranged on the front surface of the first chip;
the second chip to be packaged is arranged on the front surface of the first chip;
the conductive column is arranged on the front surface of the first chip and positioned on the peripheral side of the second chip, and the conductive column is electrically connected with the welding pad of the first chip;
the encapsulating layer encapsulates the first chip, the second chip and the conductive posts;
the conductive structure comprises a rewiring layer and a first conductive part, wherein the rewiring layer is located on one side, away from the first chip, of the encapsulating layer, the first conductive part penetrates through the encapsulating layer and electrically connects the welding pad of the second chip to the rewiring layer, and the rewiring layer electrically connects the conductive column and the first conductive part.
In one embodiment, a distance from a side of the conductive pillar facing away from the first chip to the first chip is smaller than a distance from a side of the encapsulation layer facing away from the first chip to the first chip; the conductive structure further comprises a second conductive part which is positioned between the conductive column and the redistribution layer, penetrates through the encapsulating layer and electrically connects the conductive column and the redistribution layer;
or, the surface of the conductive pillar, which faces away from the first chip, exposes the encapsulation layer; the redistribution layer electrically connects the first conductive portion and the conductive pillar.
In one embodiment, the conductive structure further includes a pin located on a side of the redistribution layer facing away from the first chip; the semiconductor packaging structure further comprises a dielectric layer, the dielectric layer covers the rewiring layer, and the surface of the pin, which deviates from the first chip, exposes the dielectric layer;
and/or the presence of a gas in the gas,
the semiconductor packaging structure further comprises a tin-plated layer positioned on one side of the conductive structure, which faces away from the encapsulating layer.
The embodiment of the application achieves the main technical effects that:
according to the semiconductor packaging method and the semiconductor packaging structure provided by the embodiment of the application, the conductive column is electrically connected with the welding pad of the first chip, the first conductive part of the conductive structure is electrically connected with the welding pad of the second chip, and the rewiring layer of the conductive structure electrically connects the first conductive part with the conductive column, so that the first chip is electrically connected with the second chip; the conductive column and the second chip are both positioned on the front side of the first chip, so that the space of the first chip in the horizontal direction is reasonably utilized, and the obtained semiconductor packaging structure is lighter and thinner; the formed encapsulating layer encapsulates the first chip and the second chip simultaneously, and compared with the scheme that the first chip and the second chip are respectively encapsulated and then connected, the light and thin semiconductor encapsulating structure is beneficial to the lightness and the thinness of the obtained semiconductor encapsulating structure, and the semiconductor encapsulating process is effectively simplified.
Drawings
FIG. 1 is a flow chart of a semiconductor packaging method provided by an exemplary embodiment of the present application;
fig. 2 is a schematic structural diagram of a first intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 3 is a schematic structural diagram of a second intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
FIG. 4 is a flow chart of forming an encapsulation layer and a conductive structure provided in an exemplary embodiment of the present application;
fig. 5 is a schematic structural diagram of a third intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 6 is a schematic structural diagram of a fourth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 7 is a schematic structural diagram of a fifth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 8 is a schematic structural diagram of a sixth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 9 is a schematic structural diagram of a seventh intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 10 is a schematic structural diagram of an eighth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 11 is a schematic structural diagram of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 12 is a schematic structural diagram of a ninth intermediate structure of a semiconductor package structure according to an exemplary embodiment of the present application;
fig. 13 is a schematic structural diagram of a tenth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 14 is a schematic structural diagram of an eleventh intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 15 is a schematic structural diagram of a twelfth intermediate structure of a semiconductor package structure according to an exemplary embodiment of the present application;
fig. 16 is a schematic structural diagram of a semiconductor package structure according to another exemplary embodiment of the present application;
FIG. 17 is a flow chart of forming an encapsulation layer and a conductive structure provided in another exemplary embodiment of the present application;
fig. 18 is a schematic structural diagram of a thirteenth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 19 is a schematic structural diagram of a fourteenth intermediate structure of a semiconductor package structure according to an exemplary embodiment of the present application;
fig. 20 is a schematic structural diagram of a fifteenth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 21 is a schematic structural diagram of a semiconductor package structure according to still another exemplary embodiment of the present application.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
The embodiment of the application provides a semiconductor packaging method. Referring to fig. 1, the semiconductor packaging method includes the following steps 110 to 130.
In step 110, a first chip to be packaged is provided, the first chip having a front surface, the front surface of the first chip being provided with a bonding pad.
In step 120, a second chip to be packaged and a conductive pillar are disposed on the front surface of the first chip; the conductive column is electrically connected with the welding pad of the first chip; the second chip is provided with a front face, the front face of the second chip deviates from the first chip, and a welding pad is arranged on the front face of the second chip.
In step 130, forming an encapsulation layer and a conductive structure, wherein the encapsulation layer encapsulates the first chip and the second chip; the conductive structure comprises a rewiring layer and a first conductive part, wherein the rewiring layer is located on one side, away from the first chip, of the encapsulating layer, the first conductive part penetrates through the encapsulating layer and electrically connects the welding pad of the second chip to the rewiring layer, and the rewiring layer electrically connects the conductive column and the first conductive part.
According to the semiconductor packaging method provided by the embodiment of the application, the conductive column is electrically connected with the welding pad of the first chip, the first conductive part of the conductive structure is electrically connected with the welding pad of the second chip, and the rewiring layer of the conductive structure electrically connects the first conductive part with the conductive column, so that the first chip is electrically connected with the second chip; the conductive column and the second chip are both positioned on the front side of the first chip, so that the space of the first chip in the horizontal direction is reasonably utilized, and the obtained semiconductor packaging structure is lighter and thinner; the formed encapsulating layer encapsulates the first chip and the second chip simultaneously, and compared with the scheme that the first chip and the second chip are respectively encapsulated and then connected, the light and thin semiconductor encapsulating structure is beneficial to the light and thin of the obtained semiconductor encapsulating structure.
The semiconductor packaging method provided by the embodiment of the present application will be described in detail below.
In step 110, a first chip is provided, the first chip having a front surface, and the front surface of the first chip is provided with a pad.
In one embodiment, the first chip may be obtained by dicing a silicon wafer. The silicon chip is provided with an active surface, and the active surface of the silicon chip is provided with a welding pad. The silicon wafer can be cut by adopting a mechanical cutting mode or a laser cutting mode. Optionally, before the silicon wafer is cut, a grinding device may be used to grind the back surface of the silicon wafer opposite to the active surface, so that the thickness of the silicon wafer is a specified thickness.
The welding pad of the first chip is composed of a conductive electrode which is led out to the surface of the chip by a chip internal circuit. The front surface of the first chip to be packaged can be provided with a plurality of welding pads. The welding pad is arranged on the conductive electrode of the first chip and leads out the conductive electrode of the first chip.
In step 120, a second chip to be packaged and a conductive pillar are disposed on the front surface of the first chip; the conductive column is electrically connected with the welding pad of the first chip; the second chip is provided with a front face, the front face of the second chip deviates from the first chip, and a welding pad is arranged on the front face of the second chip.
In one embodiment, before step 120, the first chip may be first mounted on a carrier board, and the carrier board may be manufactured into the first chip, so as to facilitate the subsequent processes.
In one embodiment, no bonding pad is disposed at a position where the second chip is disposed on the front surface of the first chip, and the second chip is disposed on the front surface of the first chip and is not electrically connected to the first chip.
In one embodiment, the step 120 of disposing the second chip to be packaged and the conductive pillars on the front surface of the first chip includes the following processes: and attaching the preformed conductive column and a second chip to be packaged on the front surface of the first chip. The preformed conductive posts can save the process steps for forming the conductive posts, and the semiconductor packaging process is facilitated to be simplified.
With preformed conductive pillars, a second chip may first be mounted on the front side of the first chip in step 120, resulting in a first intermediate structure as shown in fig. 2. The conductive pillars are then attached to the first chip, resulting in a second intermediate structure as shown in fig. 3. Referring to fig. 2, the size of the first chip 10 is larger than that of the second chip 20. The second chip 20 can be attached to the front surface of the first chip 10 by an adhesive layer 40, and the material of the adhesive layer 40 is an insulating material. Referring to fig. 3, the conductive pillars 30 are disposed on the peripheral side of the second chip 20, and the number of the conductive pillars 30 may be plural. The conductive pillars 30 may be fixed on the front surface of the first chip 10 by soldering, and electrically connected to the pads of the first chip 10.
When preformed conductive pillars are used, in step 120, the conductive pillars may be first attached to the first chip, and then the second chip is attached to the front surface of the first chip.
In some embodiments, the material of conductive post 30 may be a metallic material, such as metallic copper.
In some embodiments, the functions of the first chip 10 and the second chip 20 may be the same or different.
In another embodiment, the step 120 of disposing the second chip to be packaged and the conductive pillars on the front surface of the first chip includes the following steps:
first, a second conductive material layer is formed on the front surface of the first chip by depositing a conductive material. In this step, a seed layer may be first formed on the front side of the first chip 10 by a sputtering process. And forming a metal layer on the seed layer by adopting an electroplating process, thereby obtaining a second conductive material layer comprising the seed layer and the metal layer.
And etching the second conductive material layer to form a conductive column electrically connected with the welding pad of the first chip.
Subsequently, the second chip is mounted on the front surface of the first chip. By this step a second intermediate structure as shown in fig. 3 is obtained.
In step 130, forming an encapsulation layer and a conductive structure, wherein the encapsulation layer encapsulates the first chip and the second chip; the conductive structure comprises a rewiring layer and a first conductive part, wherein the rewiring layer is located on one side, away from the first chip, of the encapsulating layer, the first conductive part penetrates through the encapsulating layer and electrically connects the welding pad of the second chip to the rewiring layer, and the rewiring layer electrically connects the conductive column and the first conductive part.
The first conductive part penetrates through the encapsulation layer, and the first conductive part penetrates through the encapsulation layer and is positioned on one side, away from the first chip, of the second chip.
In one embodiment, referring to fig. 4, the step 130 of forming the encapsulating layer and the conductive structure includes the following steps 131 to 133.
In step 131, an encapsulation layer is formed.
In one embodiment, before the step 131 of forming the encapsulation layer, some pre-processing steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities from the surfaces of the first chip 10, the second chip 20, the conductive pillars 30 and the carrier, so that the connections between the encapsulation layer and the first chip 10, the second chip 20, the conductive pillars 30 and the carrier are more intimate and no delamination or cracking occurs.
In one embodiment, the encapsulating layer may be formed by laminating an epoxy resin film, or by injection molding, compression molding, transfer molding, or the like of an epoxy resin compound.
The encapsulation layer formed in step 131 encapsulates the first chip 10, the second chip 20 and the conductive pillars 30 to reconstruct a flat plate structure, so that the re-routing and packaging can be continued on the reconstructed flat plate structure.
In step 132, a first opening exposing a pad of the second chip is formed on the encapsulation layer.
In one embodiment, the first opening may be formed by a laser process.
In step 133, a conductive structure is formed, where the conductive structure includes a first conductive portion located in the first opening and a redistribution layer located on a side of the encapsulation layer away from the second chip.
The first conductive part is respectively in direct contact with the welding pad and the rewiring layer of the first chip, so that the first conductive part is respectively and electrically connected with the welding pad and the rewiring layer of the first chip.
In this embodiment, the distance from the side of the conductive pillar facing away from the first chip to the first chip is smaller than the distance from the side of the encapsulation layer facing away from the first chip to the first chip; alternatively, the surface of the conductive pillar facing away from the first chip exposes the encapsulation layer. These two different embodiments of the conductive post are described below.
First, a first embodiment is described: the distance from one side of the conductive column, which faces away from the first chip, to the first chip is smaller than the distance from one side of the encapsulating layer, which faces away from the first chip, to the first chip.
When the distance from the side of the conductive pillar facing away from the first chip to the first chip is smaller than the distance from the side of the encapsulation layer facing away from the first chip to the first chip, a third intermediate structure as shown in fig. 5 may be obtained through step 131. Referring to fig. 5, neither the second chip 20 nor the side of the conductive pillars 30 departing from the first chip 10 exposes the encapsulation layer 50, that is, both the second chip 20 and the side of the conductive pillars 30 departing from the first chip 10 are covered by the encapsulation layer 50. The surfaces of the conductive posts 30 facing away from the first chip 10 may be flush with the front surface of the second chip 20.
When the distance from the side of the conductive pillar away from the first chip to the first chip is smaller than the distance from the side of the encapsulation layer away from the first chip to the first chip, the step 130 of forming the encapsulation layer and the conductive structure further includes: and forming a second opening corresponding to the conductive post on the encapsulating layer.
After forming the first opening and the second opening on the encapsulating layer, a fourth intermediate structure as shown in fig. 6 can be obtained.
Referring to fig. 6, the second openings 52 correspond to the conductive pillars 30 one by one, and each second opening 52 exposes at least a portion of the surface of the corresponding conductive pillar 30. The first openings 51 may correspond to pads of the second chip 20 one to one, and the first openings 51 expose the corresponding pads of the second chip 20.
The first opening 51 and the second opening 52 may be formed by a laser process. Preferably, the step of forming the first opening corresponding to the pad of the second chip on the encapsulation layer and the step of forming the second opening corresponding to the conductive pillar on the encapsulation layer may be formed simultaneously, that is, the first opening 51 and the second opening 52 are formed simultaneously by one laser process, which helps to simplify the semiconductor packaging process.
In this embodiment, the conductive structure further includes a second conductive portion located within the second opening.
In step 133, the first conductive portion, the second conductive portion and the redistribution layer may be formed first, followed by forming the leads.
After the first conductive portion, the second conductive portion and the re-wiring layer are formed, a fifth intermediate structure as shown in fig. 7 can be obtained. Referring to fig. 7, the first conductive parts 61 are in direct contact with the pads of the second chip 20 and the rewiring layer 62, respectively, so that the pads of the second chip 20 are electrically connected to the rewiring layer 62 through the first conductive parts 61; the second conductive portion 64 is in direct contact with the conductive pillar 30 and the redistribution layer 62, so that the conductive pillar 30 is electrically connected to the redistribution layer 62 through the second conductive portion 64, and finally the bonding pad of the first chip 10 is electrically connected to the bonding pad of the second chip 20 through the redistribution layer 62.
In some embodiments, the first conductive portion 61, the second conductive portion 64 and the redistribution layer 62 may be formed by a metal deposition process such as metal sputtering or electroplating, and an etching process. The first conductive part 61, the second conductive part 64 and the rewiring layer 62 can be formed in the same process step, which helps to simplify the semiconductor packaging process.
After forming the leads, a sixth intermediate structure as shown in fig. 8 is obtained. Referring to fig. 8, the number of the leads 63 of the conductive structure 60 may be multiple, and one or more leads 63 may be formed on each redistribution layer 62.
In some embodiments, the leads 63 may be formed by a metal deposition process such as metal sputtering or plating, and an etching process.
In some embodiments, the material of the first conductive portion 61, the second conductive portion 64, the redistribution layer 62 and the leads 63 of the conductive structure 60 may be a metal material, such as copper.
In some embodiments, after step 133, the semiconductor packaging method further comprises: and forming a dielectric layer, wherein the dielectric layer covers the rewiring layer, and the surface of one side of the pin, which is deviated from the first chip, is exposed out of the dielectric layer.
The dielectric layer covers the rewiring layer and the exposed encapsulating layer. The dielectric layer may protect the rewiring layer.
In one embodiment, when forming the dielectric layer, the distance from the side of the dielectric layer facing away from encapsulation layer 50 to encapsulation layer 50 may be greater than the distance from the side of pin 63 facing away from encapsulation layer 50 to encapsulation layer 50, that is, the thickness of the dielectric layer may be greater than the thickness of pin 63, and the resulting structure is the seventh intermediate structure shown in fig. 9. Referring to fig. 9, the surface of the lead 63 facing away from the encapsulation layer 50 does not expose the dielectric layer 70. The dielectric layer 70 is then thinned to expose the surface of the lead 63 of the dielectric layer 70, and the resulting structure is an eighth intermediate structure shown in fig. 10.
In one embodiment, the dielectric layer 70 is one or more layers of insulating material, and the material of the dielectric layer 70 may be plastic film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite, or other material with similar properties. The dielectric layer 70 may be formed by lamination, spin coating, printing, molding, or other suitable means.
In some embodiments, after step 133, the semiconductor packaging method further comprises: and forming a tin-plated layer on one side of the conductive structure, which faces away from the encapsulating layer.
The tin coating is in direct contact with the pins and is electrically connected with the pins. The provision of the tin-plated layer facilitates the electrical connection of the pins 63 to external structures by soldering. The external structure is electrically connected to the pins 63 through the tin plating layer, thereby achieving electrical connection with the first chip and the second chip.
In one embodiment, the step of forming a tin plating layer on a side of the conductive structure facing away from the encapsulation layer may be performed after the step of forming a dielectric layer. After forming the tin plating layer, the semiconductor package structure shown in fig. 11 is obtained.
Next, a second embodiment is described: the surface of the conductive column, which faces away from the first chip, exposes the encapsulating layer.
In this embodiment, the height of the conductive post 30 is greater than the thickness of the second chip 20.
When the surface of the conductive pillar facing away from the first chip exposes the encapsulation layer, a ninth intermediate structure as shown in fig. 12 can be obtained through step 120; a tenth intermediate structure as shown in fig. 13 may be obtained through step 131; an eleventh intermediate structure as shown in fig. 14 can be obtained through step 132; a twelfth intermediate structure shown in fig. 15 can be obtained through step 133, referring to fig. 15, the conductive structure 60 includes a first conductive portion 61, a redistribution layer 62, and pins 63, and the surface of the conductive pillar 30 away from the first chip 10 is in direct contact with the redistribution layer 62; after the formation of the dielectric layer 70 and the tin-plated layer 80, the semiconductor package structure shown in fig. 16 can be obtained.
In this embodiment, the surface of the conductive pillar 30 away from the first chip 10 is in direct contact with the redistribution layer 62, so that there is no need to form a second opening on the encapsulation layer and a second conductive portion in the second opening.
In another embodiment, referring to fig. 17, the step 130 of forming the encapsulation layer and the conductive structure includes the following steps 134 to 136.
In step 134, a first conductive part is disposed on the front surface of the second chip, and the first conductive part is electrically connected to the pad of the second chip.
A thirteenth intermediate structure as shown in fig. 18 may be obtained through step 134. Referring to fig. 18, the first conductive portion 61 is fixed to the front surface of the second chip 20.
In some embodiments, the step 134 of providing the first conductive part on the front side of the second chip includes: and fixing a preformed first conductive part on the front surface of the first chip.
In this embodiment, a pre-formed first conductive part may be fixed on the front surface of the first chip 10 by soldering, and the first conductive part is electrically connected to the bonding pad of the first chip 10.
In other embodiments, the step 134 of providing the first conductive part on the front surface of the second chip includes the following steps:
first, a first conductive material layer is formed on the front surface of the second chip by depositing a conductive material. In this step, a seed layer may be first formed on the front surface of the second chip 20 by using a sputtering process, and then a metal layer may be formed on the seed layer by using an electroplating process, thereby obtaining a first conductive material layer including the seed layer and the metal layer.
And etching the first conductive material layer to form a first conductive part.
In one embodiment, after the step 134 of providing the first conductive part on the front surface of the second chip, the semiconductor packaging method may further include: and thinning one side of the first conductive part and/or the conductive column departing from the first chip so as to enable the first conductive part and the conductive column to be flush with the surface of the first chip. If the height of the first conductive part is greater than the set height, the height of the conductive column is approximately equal to the set height, and only one side of the first conductive part, which is far away from the first chip, is thinned; if the height of the first conductive part is approximately equal to the set height, the height of the conductive column is greater than the set height, and only one side of the conductive column, which is far away from the first chip, is thinned; if the height of the first conductive part is greater than the set height, and the height of the conductive column is greater than the set height, thinning is performed on the first conductive part and one side of the conductive column, which is far away from the first chip. In some embodiments, the first conductive portion and/or the conductive post may be thinned using a grinding process.
In step 135, an encapsulation layer is formed, and the surfaces of the first conductive portion and the conductive pillar facing away from the first chip are exposed out of the encapsulation layer.
A fourteenth intermediate structure as shown in fig. 19 may be obtained through step 135.
When the first conductive portion is preformed and the first conductive portion and the conductive pillar 30 are exposed out of the encapsulating layer 50, the first opening and the second opening are not required to be formed in the encapsulating layer 50, so that the process of opening the encapsulating layer can be omitted.
In step 136, a redistribution layer is formed on a surface of the encapsulation layer facing away from the first chip.
A fifteenth intermediate structure as shown in fig. 20 may be obtained through step 136.
In one embodiment, after step 136, step 130 of forming an encapsulation layer and a conductive structure may further include: and forming a pin on one side of the rewiring layer, which is far away from the first chip.
In one embodiment, after the step 130 of forming the encapsulation layer and the conductive structure, the semiconductor packaging method may further include:
and forming a dielectric layer, wherein the dielectric layer covers the rewiring layer, and the surface of one side of the pin, which is deviated from the first chip, is exposed out of the dielectric layer.
In some embodiments, after the step 130 of forming the encapsulation layer and the conductive structure, the semiconductor packaging method further comprises: and forming a tin-plated layer on one side of the conductive structure, which faces away from the encapsulating layer.
In one embodiment, the step of forming a tin plating layer on a side of the conductive structure facing away from the encapsulation layer may be performed after the step of forming a dielectric layer. After forming the tin plating layer, the semiconductor package structure shown in fig. 21 is obtained. Referring to fig. 21, a dielectric layer 70 covers one side of the rewiring layer 62. The tin-plated layer 80 is located on the side of the dielectric layer 70 facing away from the first chip 10.
It should be noted that, in the illustrated embodiment, only one second chip 20 is disposed on the front surface of the first chip 10 for illustration, in other embodiments, two or more second chips 20 may be disposed on the front surface of the first chip 10, and each second chip 20 on the first chip 10 is electrically connected to the first chip 10 through a conductive pillar and a conductive structure.
In one embodiment, after obtaining the semiconductor package structure shown in fig. 11, 16 or 21, if the semiconductor package structure includes two or more first chips 10, the semiconductor packaging method further includes: the semiconductor package structure is cut to obtain a plurality of sub-package structures, each of which includes a first chip 10.
The embodiment of the application also provides a semiconductor packaging structure. Referring to fig. 11, 16 and 21, the semiconductor package structure includes a first chip 10 to be packaged, a second chip 20 to be packaged, a conductive pillar 30, an encapsulation layer 50 and a conductive structure 60.
The first chip 10 has a front surface, and the front surface of the first chip 10 is provided with a bonding pad. The second chip 20 is disposed on the front side of the first chip 10. The conductive pillar 30 is disposed on the front surface of the first chip 10 and located on the periphery of the second chip 20, and the conductive pillar 30 is electrically connected to the pad of the first chip 10. The encapsulating layer 50 encapsulates the first chip 10, the second chip 20, and the conductive pillars 30. The conductive structure 60 includes a first conductive portion 61 electrically connected to a pad of the second chip 20, and a redistribution layer 62 located on a side of the encapsulation layer 50 away from the first chip 10, where the first conductive portion 61 is located between the second chip 20 and the redistribution layer 62, and the second chip 20 is electrically connected to the redistribution layer 62 by the first conductive portion 61 penetrating through the encapsulation layer 50. Further, the redistribution layer 62 electrically connects the conductive post 30 and the first conductive portion 61.
In one embodiment, the second chip 20 may be attached to the front side of the first chip 10 by an adhesive layer 40.
In one embodiment, referring to fig. 11, the distance from the side of the conductive pillar 30 facing away from the first chip 10 to the first chip 10 is smaller than the distance from the side of the encapsulation layer 50 facing away from the first chip 10 to the first chip 10. The conductive structure 60 further includes a second conductive portion 64 located between the redistribution layer 62 and the conductive pillar 30, penetrating through the encapsulation layer 50, and electrically connecting the conductive pillar 30 and the redistribution layer 62.
In another embodiment, referring to fig. 16 and 21, the surface of the conductive pillars 30 facing away from the first chip 10 exposes the encapsulation layer 50; the redistribution layer 62 electrically connects the first conductive portion 61 and the conductive post 30.
In one embodiment, the conductive structure 60 further includes a lead 63 located on a side of the redistribution layer 62 facing away from the first chip 10. The semiconductor packaging structure further comprises a dielectric layer 70, the dielectric layer 70 covers the rewiring layer 62, and the surface of the pin 63, which is away from the first chip 10, exposes the dielectric layer 70.
In one embodiment, the semiconductor package structure further includes a tin-plated layer 80 on a side of the conductive structure 60 facing away from the encapsulation layer 50. The tin coating 80 may be located on a side of the leads 63 facing away from the first chip 10.
The semiconductor packaging method and the semiconductor packaging structure provided by the embodiment of the application belong to the same inventive concept, and the description of relevant details and beneficial effects can be mutually referred to and are not repeated.
In the present application, the apparatus embodiments and the method embodiments may complement each other without conflict. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

Claims (10)

1. A semiconductor packaging method, characterized in that the semiconductor packaging method comprises:
providing a first chip to be packaged, wherein the first chip is provided with a front surface, and a welding pad is arranged on the front surface of the first chip;
arranging a second chip to be packaged and a conductive column on the front surface of the first chip; the conductive column is electrically connected with the welding pad of the first chip; the second chip is provided with a front surface, the front surface of the second chip deviates from the first chip, and a welding pad is arranged on the front surface of the second chip;
forming an encapsulating layer and a conductive structure, wherein the encapsulating layer encapsulates the first chip and the second chip; the conductive structure comprises a rewiring layer and a first conductive part, wherein the rewiring layer is located on one side, away from the first chip, of the encapsulating layer, the first conductive part penetrates through the encapsulating layer and electrically connects the welding pad of the second chip to the rewiring layer, and the rewiring layer electrically connects the conductive column and the first conductive part.
2. The method of claim 1, wherein the forming the encapsulation layer and the conductive structure comprises:
forming an encapsulation layer;
forming a first opening exposing a pad of the second chip on the encapsulation layer;
and forming a conductive structure, wherein the conductive structure comprises a first conductive part positioned in the first opening and a rewiring layer positioned on one side of the encapsulating layer, which is far away from the second chip.
3. The semiconductor packaging method according to claim 2, wherein a distance from a side of the conductive pillar facing away from the first chip to the first chip is smaller than a distance from a side of the encapsulation layer facing away from the first chip to the first chip; the forming of the encapsulating layer and the conductive structure further comprises: forming a second opening corresponding to the conductive pillar on the encapsulating layer; the conductive structure further comprises a second conductive part located in the second opening, and the second conductive part electrically connects the conductive pillar and the redistribution layer;
alternatively, the first and second electrodes may be,
the surface of the conductive column, which is far away from the first chip, exposes the encapsulating layer, and the surface of the conductive column, which is far away from the first chip, is in direct contact with the rewiring layer.
4. The method of claim 1, wherein the forming the encapsulation layer and the conductive structure comprises:
arranging a first conductive part on the front surface of the second chip, wherein the first conductive part is electrically connected with a welding pad of the second chip;
forming an encapsulating layer, wherein the encapsulating layer is exposed out of the surfaces of the first conductive part and the conductive column, which are far away from the first chip;
and forming a rewiring layer on the surface of the encapsulating layer, which is far away from the first chip.
5. The semiconductor packaging method according to claim 4, wherein the providing a first conductive portion on the front surface of the second chip comprises:
fixing a preformed first conductive part on the front surface of the second chip; or forming a first conductive material layer on the front surface of the second chip by depositing a conductive material, and etching the first conductive material layer to form a first conductive part.
6. The semiconductor packaging method according to claim 1, wherein the disposing the second chip to be packaged and the conductive pillar on the front surface of the first chip comprises:
arranging a preformed conductive column and a second chip to be packaged on the front surface of the first chip;
alternatively, the first and second electrodes may be,
the front of first chip sets up treats second chip and the electrically conductive post of encapsulation, includes:
forming a second conductive material layer on the front surface of the first chip by depositing a conductive material;
etching the second conductive material layer to form a conductive column electrically connected with the welding pad of the first chip;
and mounting the second chip on the front surface of the first chip.
7. The semiconductor packaging method of claim 1, wherein the conductive structure further comprises a pin on a side of the redistribution layer facing away from the first chip;
after the forming of the encapsulating layer and the conductive structure, the semiconductor packaging method further comprises: forming a dielectric layer, wherein the dielectric layer covers the rewiring layer, and the surface of one side of the pin, which is far away from the first chip, is exposed out of the dielectric layer;
and/or the presence of a gas in the gas,
after the forming of the encapsulating layer and the conductive structure, the semiconductor packaging method further comprises:
and forming a tin-plated layer on one side of the conductive structure, which faces away from the encapsulating layer.
8. A semiconductor package structure, comprising:
the chip packaging structure comprises a first chip to be packaged, wherein the first chip is provided with a front surface, and a welding pad is arranged on the front surface of the first chip;
the second chip to be packaged is arranged on the front surface of the first chip;
the conductive column is arranged on the front surface of the first chip and positioned on the peripheral side of the second chip, and the conductive column is electrically connected with the welding pad of the first chip;
the encapsulating layer encapsulates the first chip, the second chip and the conductive posts;
the conductive structure comprises a rewiring layer and a first conductive part, wherein the rewiring layer is located on one side, away from the first chip, of the encapsulating layer, the first conductive part penetrates through the encapsulating layer and electrically connects the welding pad of the second chip to the rewiring layer, and the rewiring layer electrically connects the conductive column and the first conductive part.
9. The semiconductor package structure according to claim 8, wherein a distance from a side of the conductive pillar facing away from the first chip to the first chip is smaller than a distance from a side of the encapsulation layer facing away from the first chip to the first chip; the conductive structure further comprises a second conductive part which is positioned between the conductive column and the redistribution layer, penetrates through the encapsulating layer and electrically connects the conductive column and the redistribution layer;
or, the surface of the conductive pillar, which faces away from the first chip, exposes the encapsulation layer; the redistribution layer electrically connects the first conductive portion and the conductive pillar.
10. The semiconductor package structure of claim 8, wherein the conductive structure further comprises a pin on a side of the redistribution layer facing away from the first chip; the semiconductor packaging structure further comprises a dielectric layer, the dielectric layer covers the rewiring layer, and the surface of the pin, which deviates from the first chip, exposes the dielectric layer;
and/or the presence of a gas in the gas,
the semiconductor packaging structure further comprises a tin-plated layer positioned on one side of the conductive structure, which faces away from the encapsulating layer.
CN202011187616.6A 2020-10-29 2020-10-29 Semiconductor packaging method and semiconductor packaging structure Pending CN114429909A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011187616.6A CN114429909A (en) 2020-10-29 2020-10-29 Semiconductor packaging method and semiconductor packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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