CN115148714A - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Semiconductor packaging method and semiconductor packaging structure Download PDF

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Publication number
CN115148714A
CN115148714A CN202110336527.1A CN202110336527A CN115148714A CN 115148714 A CN115148714 A CN 115148714A CN 202110336527 A CN202110336527 A CN 202110336527A CN 115148714 A CN115148714 A CN 115148714A
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China
Prior art keywords
wiring substrate
wiring
electrically connected
bare chip
die
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CN202110336527.1A
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Chinese (zh)
Inventor
周辉星
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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Priority to CN202110336527.1A priority Critical patent/CN115148714A/en
Publication of CN115148714A publication Critical patent/CN115148714A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60015—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using plate connectors, e.g. layer, film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

The present disclosure provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor package structure includes: the device comprises an enclosing body, a first side and a second side, wherein the enclosing body is provided with a first surface and a second surface which are opposite, and the first surface is provided with a plurality of concave parts which are arranged at intervals; a plurality of packaging pieces which are correspondingly arranged in the plurality of concave parts one by one; a first wiring board provided on the first surface, the plurality of packages are electrically connected to the first wiring substrate. The present disclosure can improve product yield.

Description

Semiconductor packaging method and semiconductor packaging structure
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
Background
With the rapid development of science and technology, semiconductor devices are increasingly widely used in social production and life.
At present, a bare chip is often packaged to form a Package, and a plurality of packages are packaged for a second time to form a PIP (Package in Package) Package structure. Among them, the plurality of packages in the PIP packaging structure need to be electrically connected through a rewiring structure having fine wiring. However, the rewiring structure is prone to short-circuiting, which reduces the yield of products.
Disclosure of Invention
The present disclosure provides a semiconductor packaging method and a semiconductor packaging structure, which can improve the yield of products.
According to an aspect of the present disclosure, there is provided a semiconductor package structure including:
the packaging structure comprises an encapsulating body, a first side and a second side, wherein the first side is opposite to the second side, and the first side is provided with a plurality of concave parts which are arranged at intervals;
the packaging pieces are arranged in the concave parts in a one-to-one correspondence manner;
and a first wiring substrate provided on the first surface, wherein the plurality of packages are electrically connected to the first wiring substrate.
Further, at least one of the packages comprises:
a die having opposing front and back sides and a side connecting the front and back sides, the die front side facing the first wiring substrate;
an encapsulation layer covering at least the die side;
and the wiring structure is arranged on the front surface of the bare chip, and the welding pads on the front surface of the bare chip and the first wiring substrate are electrically connected with the wiring structure.
Further, the front side of the bare chip is provided with a protection layer, the protection layer is provided with an opening for exposing the bonding pad on the front side of the bare chip, and the wiring structure comprises:
a rewiring layer covering the protective layer and filling the opening to contact with the bonding pad on the front side of the bare chip;
and the conductive convex column is arranged on one side of the rewiring layer, which is back to the bare chip, and one end of the conductive convex column, which is far away from the rewiring layer, is electrically connected to the first wiring substrate.
Further, a first pre-wiring line is arranged in the first wiring substrate, and the plurality of packages are electrically connected to the first pre-wiring line.
Furthermore, the semiconductor packaging structure further comprises a first dielectric layer, wherein the first dielectric layer covers the first surface and surrounds the first wiring substrate.
Further, one side of each package facing the first wiring substrate comprises a wiring structure, the wiring structure is electrically connected to the first wiring substrate, and the surface of the wiring structure electrically connected to the first wiring substrate is flush with the first surface.
According to an aspect of the present disclosure, there is provided a semiconductor packaging method including:
forming an encapsulation body and a plurality of encapsulation pieces, wherein the encapsulation body is provided with a first surface and a second surface which are opposite, and the first surface is provided with a plurality of concave parts which are arranged at intervals; the plurality of packaging pieces are arranged in the plurality of concave parts in a one-to-one correspondence manner;
a first wiring substrate is arranged on the first surface, and the packaging pieces are electrically connected to the first wiring substrate.
Further, the forming method of at least one package comprises the following steps:
providing a die having opposing front and back sides and a side connecting the front and back sides;
forming an encapsulation layer covering at least the sides of the die;
forming a wiring structure on the front side of the bare chip, wherein a welding pad on the front side of the bare chip is electrically connected with the wiring structure;
wherein the die front surface faces the first wiring substrate, and the wiring structure is electrically connected to the first wiring substrate.
Further, the front side of the bare chip is provided with a protection layer, the protection layer is provided with an opening for exposing the bonding pad on the front side of the bare chip, and the forming of the wiring structure on the front side of the bare chip comprises:
forming a rewiring layer covering the protective layer, wherein the rewiring layer fills the opening to be in contact with a welding pad on the front side of the bare chip;
and forming a conductive convex column on one side of the rewiring layer, which is opposite to the bare chip, wherein one end of the conductive convex column, which is far away from the rewiring layer, is electrically connected to the first wiring substrate.
Further, providing a first wiring substrate on the first surface includes:
and testing the first wiring substrate, and arranging the first wiring substrate qualified in the test on the first surface.
Further, the semiconductor packaging method further includes:
and forming a first dielectric layer which covers the first surface and surrounds the first wiring substrate.
Further, forming a wiring structure on the front side of the die includes:
forming a rewiring layer on the front surface of the bare chip, wherein a welding pad on the front surface of the bare chip is electrically connected to the rewiring layer;
forming a conductive convex column on one side of the rewiring layer, which is opposite to the bare chip, wherein the conductive convex column and the rewiring layer form the wiring structure;
forming the encapsulation includes:
the conductive convex columns are used as alignment marks, the packaging piece with the bare chip is mounted on a first carrier plate, and the front surface of the bare chip faces to the first carrier plate;
forming an encapsulation body covering the first carrier and the package, wherein the encapsulation body forms the concave part corresponding to the area of the package.
According to the semiconductor packaging method and the semiconductor packaging structure, the plurality of packaging pieces are arranged in the plurality of concave parts of the packaging body in a one-to-one correspondence mode, so that the packaging body packages the plurality of packaging pieces, and the plurality of packaging pieces are electrically connected with the first wiring substrate, so that the plurality of packaging pieces are electrically connected through the first wiring substrate, the problem of short circuit caused by the adoption of a rewiring structure is solved, and the product yield is improved.
Drawings
Fig. 1 is a flow chart of a semiconductor packaging method of an embodiment of the present disclosure.
FIG. 2 is a schematic illustration of a silicon wafer in an embodiment of the disclosure.
Fig. 3 is a schematic diagram of a semiconductor packaging method according to an embodiment of the disclosure after an encapsulation layer is formed.
Fig. 4 is a schematic diagram after a wiring structure is formed in the semiconductor packaging method according to the embodiment of the present disclosure.
Fig. 5 is a schematic diagram of the semiconductor packaging method according to the embodiment of the disclosure after an insulating material layer is formed.
Fig. 6 is a schematic view after an encapsulant is formed in the semiconductor packaging method according to the embodiment of the present disclosure.
Fig. 7 is a schematic view illustrating the semiconductor packaging method according to the embodiment of the disclosure after removing the first carrier.
Fig. 8 is a schematic view after a first wiring substrate is provided in the semiconductor packaging method according to the embodiment of the present disclosure.
Fig. 9 is a schematic view after forming a conductive structure in the semiconductor packaging method according to the embodiment of the present disclosure.
Fig. 10 is a schematic view after a second wiring substrate is provided in the semiconductor packaging method according to the embodiment of the present disclosure.
Fig. 11 is a schematic diagram illustrating a plurality of dies arranged on a second carrier according to the semiconductor packaging method of the embodiment of the disclosure.
Fig. 12 is a schematic view illustrating a plurality of packages arranged on a first carrier in a semiconductor packaging method according to an embodiment of the disclosure.
Fig. 13 is a schematic view after a first dielectric layer is formed in the semiconductor packaging method according to the embodiment of the disclosure.
Description of reference numerals: 1. a bare chip; 2. a protective layer; 3. a wiring layer is arranged; 4. a conductive convex column; 5. a layer of insulating material; 6. an enclosure; 601. a first surface; 602. a second surface; 7. a first dielectric layer; 8. a first wiring substrate; 9. a conductive structure; 10. a second wiring substrate; 11. an encapsulation layer; 12. a second dielectric layer; 13. a first carrier plate; 14. a second carrier plate; 15. a bonding pad; 16. a silicon wafer; 17. an opening; 18. a circuit leading-out terminal; 100. and (7) packaging the components.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of devices consistent with certain aspects of the present disclosure, as detailed in the appended claims.
The terminology used in the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in the description and claims does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms a, an, etc. do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "a number" means two or more. Unless otherwise indicated, "front", "rear", "lower" and/or "upper" and the like are for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that the element or item listed after "comprises" or "comprising" is inclusive of the element or item listed after "comprising" or "comprises", and the equivalent thereof, and does not exclude additional elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this disclosure and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
The embodiment of the disclosure provides a semiconductor packaging method. As shown in fig. 1, the semiconductor packaging method may include steps S100 to S120, in which:
step S100, forming an encapsulating body and a plurality of packaging parts, wherein the encapsulating body is provided with a first surface and a second surface which are opposite, and the first surface is provided with a plurality of sunken parts which are arranged at intervals; the plurality of packages are arranged in the plurality of concave parts in a one-to-one correspondence manner.
Step S110 is to dispose a first wiring substrate on the first surface, and electrically connect the plurality of packages to the first wiring substrate.
Step S120 is to provide a second wiring substrate on the second surface, and the second wiring substrate is electrically connected to the first wiring substrate.
In the semiconductor packaging method according to the embodiment of the present disclosure, as shown in fig. 10, the plurality of packages 100 are disposed in the plurality of recesses of the encapsulant 6 in a one-to-one correspondence manner, so that the encapsulant 6 encapsulates the plurality of packages 100, and the plurality of packages 100 are electrically connected to the first wiring substrate 8, so that the plurality of packages 100 are electrically connected through the first wiring substrate 8, thereby solving the problem of short circuit caused by adopting a rewiring structure and improving the yield of products; meanwhile, the second wiring substrate 10 is arranged on the second surface 602 of the enclosure 6, and the second wiring substrate 10 is electrically connected with the first wiring substrate 8, so that double-sided wiring of the packaging structure is realized; in addition, the second wiring substrate 10 and the first wiring substrate 8 are both prefabricated substrates, and the manufacturing process is independent of the packaging process, so that the packaging time of the whole packaging process is saved.
The steps of the semiconductor packaging method according to the embodiment of the present disclosure are explained in detail below:
in step S100, forming an encapsulation body and a plurality of packages, where the encapsulation body has a first surface and a second surface opposite to the first surface, and the first surface has a plurality of recesses arranged at intervals; the plurality of packaging pieces are arranged in the plurality of concave parts in a one-to-one correspondence manner.
For example, step S100 may include steps S1000 to S1002, wherein:
step S1000, providing a die having opposite front and back sides and a side connecting the front and back sides.
As shown in fig. 2 and 3, the die 1 may be formed by cutting a silicon wafer 16. The silicon wafer 16 has an active surface. The active side is provided with a bonding pad 15. The front side of the die 1 may be provided with a protective layer 2. The protective layer 2 may be formed on the silicon wafer 16 prior to dicing the silicon wafer 16. The protective layer 2 may be provided with openings 17 exposing the pads 15 of the die 1. The material of the protective layer 2 may be a plastic film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material or other material with similar characteristics, and may be formed by lamination, spin coating, printing, molding or other suitable means.
Step S1001, an encapsulating layer at least covering the side face of the bare chip is formed.
As shown in fig. 3, before forming the encapsulation layer 11, the semiconductor packaging method of the embodiment of the present disclosure may include: the die 1 is mounted on the second carrier 14 with the front side of the die 1 facing the second carrier 14. The second carrier 14 may be a rigid carrier, such as a glass carrier, a stainless steel carrier, etc. The protection layer 2 disposed on the front surface of the bare chip 1 is attached to the second carrier 14. As shown in fig. 11, the number of the dies 1 mounted on the second carrier 14 in the present disclosure may be multiple. In the process of arranging a plurality of bare chips 1 on the second carrier 14, the openings 17 of the protective layer 2 on the front side of the bare chips 1 can be used as alignment marks to arrange the bare chips 1 on the second carrier 14 according to the predetermined arrangement positions more accurately, thereby improving the yield of packaging. The encapsulating layer 11 may cover the side of the die 1 and the back of the die 1, with the front of the die 1 exposed. Of course, the encapsulation layer 11 may cover only the side of the die 1. The encapsulating layer 11 may be formed by injection molding, hot press molding, or the like. The material of the encapsulating layer 11 may be a resin, such as Epoxy Molding Compound (EMC) or the like.
Step S1002, a wiring structure is formed on the front surface of the bare chip, and the pads on the front surface of the bare chip are electrically connected to the wiring structure.
As shown in fig. 3 and 4, before forming the wiring structure, the present disclosure needs to remove the second carrier 14 to expose the front surface of the die 1. Taking the case that the front surface of the bare chip 1 is provided with the protection layer 2 as an example, forming the wiring structure may include: forming a rewiring layer 3 covering the protective layer 2, wherein the rewiring layer 3 fills the opening 17 of the protective layer 2 to be in contact with the bonding pad 15 on the front surface of the bare chip 1, so that the rewiring layer 3 is electrically connected to the bonding pad 15 on the front surface of the bare chip 1; a conductive stud 4 is formed on the side of the redistribution layer 3 facing away from the die 1. One surface of the encapsulating layer 11 may be flush with the surface of the passivation layer 2 facing away from the die 1, and the redistribution layer 3 may also partially cover the surface of the encapsulating layer 11 flush with the surface of the passivation layer 2 facing away from the die 1. The redistribution layer 3 or the conductive pillar 4 may be formed by metal sputtering, electrolytic plating, electroless plating, or the like. Furthermore, as shown in fig. 5, after forming the conductive studs 4, the present disclosure may also form a layer of insulating material 5. The insulating material layer 5 may cover the rewiring layer 3 and the encapsulation layer 11, an end surface of the conductive pillar 4 away from the rewiring layer 3 is exposed from the encapsulation layer 11, and an end surface of the conductive pillar 4 away from the rewiring layer 3 may be flush with a surface of the insulating material layer 5 away from the rewiring layer 3. The above steps S1000 to S1002 may constitute a method of forming at least one package 100 among the plurality of packages 100. The number of packages 100 may be two, three, four or more. The function of the bare chip 1 in each package 100 may be different, the bare chips 1 with various functions are packaged once to form an intermediate package structure, and each bare chip 1 independently implements a rewiring process.
Step S1003, taking the conductive convex columns as alignment marks, and attaching a packaging piece with a bare chip on a first carrier plate, wherein the front surface of the bare chip in the packaging piece faces the first carrier plate; and forming an encapsulating body covering the first carrier plate and the packaging piece, wherein the encapsulating body forms a concave part corresponding to the area of the packaging piece.
As shown in fig. 6, the first carrier 13 may be a hard carrier, such as a glass carrier, a stainless steel carrier, etc. The end surface of the conductive pillar 4 away from the bare chip 1 and the insulating material layer 5 are both attached to the first carrier 13. The conductive posts 4 are used as alignment marks, so that the package 100 can be more accurately disposed on the first carrier 13 according to a predetermined position, thereby improving the yield of the package. As shown in fig. 12, a plurality of the above-mentioned packages 100 may be arranged on the first carrier 13, and the plurality of packages 100 are disposed at intervals. After forming the encapsulant, the present disclosure may further include: the first carrier 13 is removed. The surface of the encapsulating body 6 facing the first carrier 13 is the first surface 601, and the surface of the encapsulating body 6 facing away from the first carrier 13 is the second surface 602. An end surface of the conductive pillar 4 of each package 100 away from the redistribution layer 3 may be flush with the first surface 601. The encapsulant 6 forms a plurality of recesses corresponding to the areas of the plurality of packages 100, and the plurality of packages 100 are disposed in the recesses in a one-to-one correspondence. The envelope 6 may be formed by injection molding, hot press molding, or the like. The material of the package body 6 may be a resin, such as Epoxy Molding Compound (EMC) or the like.
In step S110, a first wiring substrate is disposed on the first surface, and a plurality of packages are electrically connected to the first wiring substrate.
As shown in fig. 6 to 8, before the first wiring substrate 8 is disposed, the first carrier 13 is removed. By way of example, step 110 may include: the first wiring substrate 8 is tested, and the first wiring substrate 8 that passes the test is disposed on the first surface 601. Testing of the wiring substrate is performed prior to packaging, avoiding the use of known poor wiring substrates. The first wiring board 8 is provided with a first pre-wired line. The plurality of packages 100 are electrically connected to the first pre-wiring line, so that the plurality of packages 100 are electrically connected to the first wiring substrate 8. Specifically, the wiring structure of each package 100 is electrically connected to the first pre-wiring line. More specifically, the surface of the conductive post 4 on each package 100 away from the rewiring layer 3 is electrically connected to the first pre-wiring line. The conductive pillar 4 may be electrically connected to the first pre-wiring line by soldering. The wiring structure is electrically connected to the surface of the first wiring substrate 8 and the first surface 601 of the encapsulation 6, that is, the surface of the conductive stud 4 away from the redistribution layer 3 and the first surface 601 of the encapsulation 6 are flush. The first wiring substrate 8 has a plurality of complex circuits, and the first wiring substrate 8 having a plurality of complex circuits rewires between the plurality of packages 100, improving the performance of the entire package structure; in addition, the first wiring substrate 8 having a complicated multi-circuit replaces a fine wiring in a rewiring structure, reducing the probability of a short circuit, increasing the product yield, reducing the process complexity, and forming a PIP package structure having a complicated circuit.
In step S120, a second wiring substrate is provided on the second surface, and the second wiring substrate is electrically connected to the first wiring substrate.
As shown in fig. 8 to 10, before providing the second wiring substrate 10, the semiconductor packaging method of the present disclosure may further include: forming a via hole through the first surface 601 and the second surface 602 of the encapsulation 6; a conductive structure 9 is formed within the via hole, and the conductive structure 9 is electrically connected to the first wiring substrate 8. Wherein the conductive structure 9 is electrically connected to the first pre-wiring line in the first wiring substrate 8. The material of the conductive structure 9 may be copper, but the embodiment of the present disclosure is not limited thereto. By way of example, step 120 may include: the second wiring substrate 10 is tested, and the second wiring substrate 10 that passes the test is disposed on the second surface 602. Testing of the wiring substrate is performed prior to packaging, avoiding the use of known poor wiring substrates. The second wiring substrate 10 is electrically connected to the conductive structure 9 in the via hole so that the second wiring substrate 10 is electrically connected to the first wiring substrate 8. A second pre-wiring circuit is disposed in the second wiring substrate 10, and the conductive structure 9 is electrically connected to the second pre-wiring circuit.
The semiconductor packaging method of the present disclosure may further include:
step S130, forming a first dielectric layer and a second dielectric layer.
As shown in fig. 10, in one embodiment of the present disclosure, the first dielectric layer 7 covers the first wiring substrate 8 and the first surface 601, and the second dielectric layer 12 covers the second surface 602 and surrounds the second wiring substrate 10. In another embodiment of the present disclosure, the first dielectric layer 7 covers the first surface 601 and surrounds the first wiring substrate 8, and the second dielectric layer 12 covers the second wiring substrate 10 and the second surface 602. The material of the first dielectric layer 7 or the second dielectric layer 12 may be a plastic film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite, or other material with similar characteristics, and may be formed by lamination, spin coating, printing, molding, or other suitable means. In addition, the semiconductor packaging method of the present disclosure may further include: a circuit terminal 18 is formed on a surface of the second wiring substrate 10 remote from the enclosure 6, the circuit terminal 18 being electrically connected to a second pre-wired circuit in the second wiring substrate 10. The circuit terminals 18 may be solder structures.
In other embodiments of the present disclosure, as shown in fig. 13, the first dielectric layer 7 may be formed before the second wiring substrate 10 is disposed. The first dielectric layer 7 covers the first surface 601 and surrounds the first wiring substrate 8.
The embodiment of the disclosure also provides a semiconductor packaging structure. The semiconductor packaging structure can be prepared by the semiconductor packaging method described in any of the above embodiments. As shown in fig. 10, the semiconductor package structure may include an encapsulant 6, a package 100, a first wiring substrate 8, and a second wiring substrate 10, wherein:
the enclosure 6 has a first surface 601 and a second surface 602 opposite to each other, and the first surface 601 has a plurality of recesses arranged at intervals. The plurality of packages 100 are disposed in the plurality of recesses in a one-to-one correspondence. The first wiring substrate 8 is provided on the first surface 601, and the plurality of packages 100 are electrically connected to the first wiring substrate 8. The second wiring board 10 is provided on the second surface 602 and is electrically connected to the first wiring board 8.
At least one of the packages 100 includes a die 1, an encapsulation layer 11, and a wiring structure. The die 1 has opposite front and back surfaces and side surfaces connecting the front and back surfaces, the front surface of the die 1 facing the first wiring substrate 8. The encapsulation layer 11 covers at least the side of the die 1. The wiring structure is provided on the front surface of the bare chip 1, and the bonding pads 15 on the front surface of the bare chip 1 and the first wiring substrate 8 are electrically connected to the wiring structure.
The bare chip 1 is provided with a protective layer 2 on the front side. The protective layer 2 is provided with openings 17 exposing the pads 15 on the front side of the die 1. The wiring structure may include a wiring layer wiring layer 3 and conductive posts 4. The redistribution layer 3 covers the passivation layer 2 and fills the opening 17 to contact the pad 15 on the front side of the die 1. The conductive pillar 4 is disposed on a side of the redistribution layer 3 facing away from the die 1, and an end of the conductive pillar 4 away from the redistribution layer 3 is electrically connected to the first wiring substrate 8.
The encapsulation 6 has a via through the first surface 601 and the second surface 602. The semiconductor package structure may further include a conductive structure 9. The conductive structure 9 may be provided in a via. The first wiring board 8 and the second wiring board 10 are electrically connected to the conductive structure 9, so that the first wiring board 8 is electrically connected to the second wiring board 10.
The first wiring substrate 8 is provided with a first pre-wiring line, the second wiring substrate 10 is provided with a second pre-wiring line, the conductive structure 9 and the plurality of packages 100 are electrically connected to the first pre-wiring line, and the second pre-wiring line is electrically connected to the conductive structure 9.
The semiconductor packaging structure further comprises a first dielectric layer 7 and a second dielectric layer 12, wherein the first dielectric layer 7 covers the first wiring substrate 8 and the first surface 601, and the second dielectric layer 12 covers the second surface 602 and surrounds the second wiring substrate 10. Of course, in other embodiments of the present disclosure, the first dielectric layer 7 covers the first surface 601 and surrounds the first wiring substrate 8, and the second dielectric layer 12 covers the second wiring substrate 10 and the second surface 602.
Each package 100 includes a wiring structure on a side facing the first wiring substrate 8, the wiring structure being electrically connected to a surface of the first wiring substrate 8 flush with the first surface 601.
The semiconductor packaging method and the semiconductor packaging structure provided by the embodiments of the present disclosure belong to the same inventive concept, and the description of the relevant details and beneficial effects can be referred to each other and will not be repeated.
Although the present disclosure has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the present disclosure.

Claims (12)

1. A semiconductor package structure, comprising:
the device comprises an enclosing body, a first side and a second side, wherein the enclosing body is provided with a first surface and a second surface which are opposite, and the first surface is provided with a plurality of concave parts which are arranged at intervals;
a plurality of packaging pieces which are correspondingly arranged in the plurality of concave parts one by one;
and the first wiring substrate is arranged on the first surface, and the plurality of packaging pieces are electrically connected to the first wiring substrate.
2. The semiconductor package structure of claim 1, wherein at least one of the packages comprises:
a die having opposing front and back sides and a side connecting the front and back sides, the die front side facing the first wiring substrate;
an encapsulation layer covering at least the die side;
and the wiring structure is arranged on the front surface of the bare chip, and the welding pads on the front surface of the bare chip and the first wiring substrate are electrically connected with the wiring structure.
3. The semiconductor package structure of claim 2, wherein the front side of the die is provided with a protective layer provided with an opening exposing a pad of the front side of the die, the wiring structure comprising:
the rewiring layer covers the protective layer and fills the opening so as to be in contact with the welding pad on the front side of the bare chip;
and the conductive convex column is arranged on one side of the rewiring layer, which is back to the bare chip, and one end of the conductive convex column, which is far away from the rewiring layer, is electrically connected to the first wiring substrate.
4. The semiconductor package structure according to claim 1, wherein a first pre-wiring line is provided in the first wiring substrate, and the plurality of packages are electrically connected to the first pre-wiring line.
5. The semiconductor package structure of claim 1, further comprising a first dielectric layer covering the first surface and surrounding the first wiring substrate.
6. The semiconductor package structure according to claim 1, wherein a side of each of the packages facing the first wiring substrate includes a wiring structure electrically connected to the first wiring substrate, the wiring structure being electrically connected to a surface of the first wiring substrate flush with the first surface.
7. A semiconductor packaging method, comprising:
forming an encapsulation body and a plurality of encapsulation pieces, wherein the encapsulation body is provided with a first surface and a second surface which are opposite, and the first surface is provided with a plurality of concave parts which are arranged at intervals; the plurality of packaging pieces are arranged in the plurality of concave parts in a one-to-one correspondence manner;
a first wiring substrate is arranged on the first surface, and the packaging pieces are electrically connected to the first wiring substrate.
8. The semiconductor packaging method of claim 7, wherein the forming of at least one of the packages comprises:
providing a die having opposing front and back sides and a side connecting the front and back sides;
forming an encapsulation layer covering at least the sides of the die;
forming a wiring structure on the front side of the bare chip, wherein a welding pad on the front side of the bare chip is electrically connected with the wiring structure;
wherein the die front surface faces the first wiring substrate, and the wiring structure is electrically connected to the first wiring substrate.
9. The semiconductor packaging method according to claim 8, wherein the front side of the die is provided with a protective layer, the protective layer is provided with an opening for exposing a pad on the front side of the die, and the forming of the wiring structure on the front side of the die comprises:
forming a rewiring layer covering the protective layer, wherein the rewiring layer fills the opening to be in contact with a welding pad on the front side of the bare chip;
and forming a conductive convex column on one side of the rewiring layer, which is opposite to the bare chip, wherein one end of the conductive convex column, which is far away from the rewiring layer, is electrically connected to the first wiring substrate.
10. The semiconductor packaging method according to claim 7, wherein providing a first wiring substrate on the first surface comprises:
and testing the first wiring substrate, and arranging the first wiring substrate qualified in the test on the first surface.
11. The semiconductor packaging method according to claim 7, further comprising:
and forming a first dielectric layer, wherein the first dielectric layer covers the first surface and surrounds the first wiring substrate.
12. The semiconductor packaging method of claim 8, wherein forming a routing structure on the front side of the die comprises:
forming a rewiring layer on the front surface of the bare chip, wherein a welding pad on the front surface of the bare chip is electrically connected to the rewiring layer;
forming a conductive convex column on one side of the rewiring layer, which is back to the bare chip, wherein the conductive convex column and the rewiring layer form the wiring structure;
forming the encapsulation includes:
the conductive convex columns are used as alignment marks, the packaging piece with the bare chip is mounted on a first carrier plate, and the front surface of the bare chip faces to the first carrier plate;
forming an encapsulation body covering the first carrier and the package, wherein the encapsulation body forms the concave part corresponding to the area of the package.
CN202110336527.1A 2021-03-29 2021-03-29 Semiconductor packaging method and semiconductor packaging structure Pending CN115148714A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110336527.1A CN115148714A (en) 2021-03-29 2021-03-29 Semiconductor packaging method and semiconductor packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110336527.1A CN115148714A (en) 2021-03-29 2021-03-29 Semiconductor packaging method and semiconductor packaging structure

Publications (1)

Publication Number Publication Date
CN115148714A true CN115148714A (en) 2022-10-04

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Country Status (1)

Country Link
CN (1) CN115148714A (en)

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