CN114389753A - POS interface capable of adapting to multiple rates - Google Patents
POS interface capable of adapting to multiple rates Download PDFInfo
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- CN114389753A CN114389753A CN202111535602.3A CN202111535602A CN114389753A CN 114389753 A CN114389753 A CN 114389753A CN 202111535602 A CN202111535602 A CN 202111535602A CN 114389753 A CN114389753 A CN 114389753A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/18—Protocol analysers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
- H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
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Abstract
The invention discloses a POS interface capable of adapting to various rates, which comprises an FPGA chip, wherein the FPGA chip comprises: a Transceiver Transceiver, a frame searching and tracking module, a descrambling and B1 verification module, a pointer analyzing and monitoring module, a payload extracting module, an HDLC de-encapsulation module, a bit width conversion module, a PPP protocol analyzing module and an interface conversion module; the Transceiver converts the received serial optical signals into parallel electrical signals, and transmits IP protocol data packets with the protocol number of 0x0021 to an interface conversion module after completing data processing by a frame search and frame tracking module, a descrambling and B1 verification module, a payload extraction module, an HDLC decapsulation module, a bit width conversion module and a PPP protocol analysis module in sequence, and converts the IP protocol data packets into Ethernet interface data for output. The POS interface of the invention is designed to overcome the problem of high cost of the traditional structure, and can adapt to various rates.
Description
Technical Field
The invention belongs to the field of data transmission, and particularly relates to a POS interface capable of adapting to multiple rates.
Background
POS is called Packet Over SDH, also called IP Over SDH, and is a technology for transmitting IP data traffic through a high-speed transmission channel provided by SDH, which maps an IP data Packet of variable length into an SDH payload, providing a high-speed, reliable, point-to-point data connection.
At present, POS interface cards are configured in both home and abroad middle-end and high-end router equipment, and the design and implementation of the POS interface are difficult points for the development of the POS interface cards. The POS interface is typically implemented using a POS framer chip design, of which the framer chip PM53XX offered by the Canadian optical communication solutions vendor PMC corporation is the most widely used. The scheme for realizing the POS interface by adopting the framer design has the advantages of maturity, easiness in use, simplicity in design and the like, but also has the defects of higher chip price and the like.
Therefore, a need exists for a low cost POS interface that can accommodate multiple rates.
Disclosure of Invention
The invention aims to provide a POS interface capable of adapting to various rates in order to overcome the defects of the prior art, and the POS interface can be adapted to various rates.
The purpose of the invention is realized by the following technical scheme:
a POS interface capable of adapting to a plurality of rates, the POS interface comprising an FPGA chip, the FPGA chip comprising: a Transceiver Transceiver, a frame searching and tracking module, a descrambling and B1 verification module, a pointer analyzing and monitoring module, a payload extracting module, an HDLC de-encapsulation module, a bit width conversion module, a PPP protocol analyzing module and an interface conversion module; the Transceiver converts the received serial optical signals into parallel electrical signals, and transmits IP protocol data packets with the protocol number of 0x0021 to an interface conversion module after completing data processing by a frame search and frame tracking module, a descrambling and B1 verification module, a payload extraction module, an HDLC decapsulation module, a bit width conversion module and a PPP protocol analysis module in sequence, and converts the IP protocol data packets into Ethernet interface data for output.
According to a preferred embodiment, the FPGA chip further includes: the device comprises a data combining module, a bit width conversion module, an HDLC packaging module, a data mapping virtual container, a frame header insertion and B1 calculation and scrambling module; the PPP protocol analysis module sends a network control protocol frame NCP with a protocol number of 0x8021 to the data combining module, and then the data processing is completed through the bit width conversion module, the HDLC packaging module, the data mapping virtual container, the frame header insertion and B1 calculation and the scrambling module in sequence, and the data is transmitted to the optical fiber circuit after parallel-serial conversion through the Transceiver Transceiver.
According to a preferred embodiment, the POS interface further includes an optical module, one end of the optical module is connected to the optical fiber end, and the other end is connected to the FPGA chip via a SerDes interface, so as to realize conversion of the high-speed SerDes interface between the optical signal and the electrical signal at the optical fiber end
According to a preferred embodiment, the POS interface further includes a configuration interface, the configuration interface is an input signal interface configured for POS interface rate and CRC check mode, and the configuration interface is connected to a Transceiver in the FPGA chip.
According to a preferred embodiment, the frame searching and tracking module is configured to perform frame searching in a half-search mode and perform frame tracking in a half-frame header tracking mode, and includes: if the frame head is not detected in four continuous frames, setting an out-of-position OOF alarm signal of the frame to indicate that the receiving line part detects that the frame is not synchronous; when two continuous frames detect the frame head, clearing OOF alarm signals; in the OOF state, if the duration lasts for 3 milliseconds, setting a frame loss LOF; in the LOF state, if no OOF lasts for 3 milliseconds, the LOF is cleared; if the data is normally 0 or 1 within 20 microseconds, the LOS is lost by the setting signal;
in the LOS state, if an incoming data frame header is found, the LOS is cleared.
According to a preferred embodiment, the descrambling and B1 checking module is configured to descramble the scrambled SDH frame to recover the SDH frame, where the descrambling polynomial is 1+ X6+X7Meanwhile, the detection of the error code of the regeneration section is finished through B1 check, 8 bit groups are used for bit interpolation parity check, and no check existsAnd transmitting the error data to a pointer analyzing and monitoring module.
According to a preferred embodiment, the pointer parsing and monitoring module extracts the management unit pointer corresponding to the SDH frame, parses the H1, H2 pointer fields, determines the start position of the VC frame in the payload of the SDH frame, and generates the frame header, the channel trace J0/J1 fields, and the indication signal of the VC frame payload.
According to a preferred embodiment, the payload extraction module is configured to strip the payload from the SDH frame based on an indication signal of the VC frame payload, and send the stripped payload to the HDLC decapsulation module; the HDLC decapsulation module is configured to decapsulate the extracted data payload according to an HDLC protocol to obtain an output data frame; the bit width conversion module is configured to realize the interconversion between the data bit width 8 bits and 32 bits; the PPP protocol analysis module is configured to analyze the protocol field of the PPP frame, and send the IP protocol data packet with the protocol number of 0x0021 to the interface conversion module to be converted into Ethernet interface data; and sending the LCP and the 0x8021 LCP frames to the data combining module.
According to a preferred embodiment, the data combining module is configured to combine the IP protocol data packet sent by the interface conversion module with the received link control protocol frame and network control protocol frame, and output the combined data packet to the bit width conversion module.
According to a preferred embodiment, the HDLC encapsulation module is configured to encapsulate the bandwidth-converted data according to an HDLC protocol, and output an HDLC format frame; the data mapping virtual container is configured to map HDLC format frames into VC-4/VC-4-4c concatenated frames.
According to a preferred embodiment, the frame header insertion and B1 calculation and scrambling module is configured to complete insertion of segment overhead and management unit pointers; at the network node, the STM-N signal is scrambled prior to transmission, the digital signal sequence is scrambled, a B1 bit interleaved parity is regenerated, and inserted into the corresponding position of the frame header.
The aforementioned main aspects of the invention and their respective further alternatives can be freely combined to form a plurality of aspects, all of which are aspects that can be adopted and claimed by the present invention. The skilled person in the art can understand that there are many combinations, which are all the technical solutions to be protected by the present invention, according to the prior art and the common general knowledge after understanding the scheme of the present invention, and the technical solutions are not exhaustive herein.
The invention has the beneficial effects that: the POS interface capable of adapting to various rates disclosed by the invention solves the problem of high cost of the POS interface realized by an imported framer chip at present. And by realizing the design and the realization method of the POS interface with STN-N multiple rates on the FPGA chip, the interface rate is configured according to the requirement, the application range is wide, and the practicability is strong.
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FIG. 1 is a schematic diagram of a POS interface capable of adapting to multiple rates according to the present invention;
FIG. 2 is a block diagram of the logic architecture of the FPGA chip in the POS interface architecture capable of adapting to multiple rates according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that, in order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments.
Example 1:
referring to fig. 1, the present invention discloses a POS interface capable of adapting to multiple rates, where the POS interface includes an optical module, an FPGA chip, a configuration interface, a state information interface, and an ethernet interface.
One end of the optical module is connected with the optical fiber end, and the other end of the optical module is connected with the FPGA chip through the SerDes interface, so that the conversion of the high-speed SerDes interface of the optical signal and the electric signal of the optical fiber end is realized.
The FPGA chip is also connected with the configuration interface, the state information interface and the Ethernet interface respectively.
The configuration interface is an input signal interface configured by POS interface rate and CRC check mode, and is connected with a Transceiver in the FPGA chip. Typically GPIO
(General-Purpose Input/Output).
And can obtain through the status information interface: and outputting the state information of the POS interface speed, the state information of a CRC (Cyclic Redundancy check) check mode, the on-off state of the POS interface, the on-off state of the POS link, the receiving and transmitting packet number of the RGMII interface, the byte number, the packet error number, the packet loss number and the like.
Preferably, as shown in fig. 2, in this embodiment, the FPGA chip includes two input/output links.
Preferably, each input-output link comprises the following functional modules: the device comprises a Transceiver, a frame searching and tracking module, a descrambling and B1 verifying module, a pointer analyzing and monitoring module, a payload extracting module, an HDLC de-encapsulating module, a bit width converting module, a PPP protocol analyzing module and an interface converting module.
The Transceiver converts the received serial optical signal into a parallel electrical signal, and after data processing is completed by the frame search and frame tracking module, the descrambling and B1 verification module, the payload extraction module, the HDLC decapsulation module, the bit width conversion module and the PPP protocol analysis module in sequence, an IP protocol data packet with the protocol number of 0x0021 is sent to the interface conversion module and converted into Ethernet interface data to be output.
Preferably, the Transceiver Transceiver is configured to perform interconversion between serial optical signals and parallel electrical signals, and the configuration of STM-N multiple rate modes is performed at the module. According to the input POS interface rate and CRC check mode configuration information, the Transceiver adopts the dynamic local reconfigurable technology of the FPGA, generates a Transceiver soft core according to the configuration information, and converts the serial optical signal into a parallel binary electrical signal.
By utilizing the advantages of reconfigurable and parallel pipeline processing of FPGA logic design, various STM-N (synchronous transmission mode) such as POS interfaces with various rates and configurable requirements of STM-1(155.52Mbps), STM-4(622.08Mbps), STM-16(2488.32Mbps), STM-64(9953.28Mbps) and STM-256(39813.12Mbps) are realized.
Preferably, the frame searching and tracking module is configured to perform frame searching in a half-search mode and perform frame tracking in a half-frame header tracking mode. The method specifically comprises the following steps: 1) if the frame head is not detected in four continuous frames, an OOF (out of frame) alarm signal is set to indicate that the receiving line part detects that the frames are not synchronous; when two continuous frames detect the frame head, clearing OOF alarm signals; 2) in the OOF state, if it lasts for 3 milliseconds, the LOF (loss of frame, frame loss) is set; in the LOF state, if no OOF lasts for 3 milliseconds, the LOF is cleared; 3) if the data is normally "0" or normally "1" within 20 microseconds, setting LOS (LOSs of signal); in the LOS state, if an incoming data frame header is found, the LOS is cleared.
Preferably, the descrambling and B1 checking module is configured to descramble the scrambled SDH frame to recover the SDH frame, where the descrambling polynomial is 1+ X6+X7. Meanwhile, the error code monitoring of the regeneration section is completed through B1 check, 8 bit groups are used for bit interleaving parity check, and data without error is checked and transmitted to the pointer analyzing and monitoring module.
Preferably, the pointer parsing and monitoring module extracts the management unit pointer corresponding to the SDH frame, parses the H1 and H2 pointer fields, determines the start position of the VC frame in the payload of the SDH frame, and generates the frame header, the channel trace J0/J1 fields, and the indication signal of the VC frame payload.
Specifically, the detection frame tracking process generates LOS, LOF, OOF and other alarm models, and supports the software query of the microprocessor. All of the regenerated segment, multiplexed segment, and channel overhead (including B1, B2, B3, E1, F1, etc.) bytes are monitored. Alarm signals are detected and received, error counts for each stage of performance monitoring are accumulated, and remote error indications M1, G1 for segments and channels are generated. The C2, J0, and J1 bytes are extracted and the corresponding alarms may be inserted back by the software.
Preferably, the payload extraction module is configured to strip the payload from the SDH frame based on an indication signal of the VC frame payload, and send the stripped payload to the HDLC decapsulation module.
Preferably, the HDLC decapsulation module is configured to decapsulate the extracted data payload according to an HDLC protocol to obtain an output data frame.
Preferably, the bit width conversion module is configured to implement mutual conversion between 8 bits and 32 bits of data bit width.
Preferably, the PPP protocol parsing module is configured to parse a protocol field of a PPP frame, send an IP protocol data packet with a protocol number of 0x0021 to the interface conversion module, and convert the IP protocol data packet into ethernet interface data; and sending the LCP and the 0x8021 LCP frames to the data combining module.
Preferably, each input-output link further comprises the following functional modules: the device comprises a data combining module, a bit width conversion module, an HDLC packaging module, a data mapping virtual container, a frame header insertion and B1 calculation and scrambling module.
The PPP protocol analysis module sends a network control protocol frame NCP with a protocol number of 0x8021 to the data combining module, and then the data is processed by the bit width conversion module, the HDLC packaging module, the data mapping virtual container, the frame header insertion and B1 calculation and scrambling module in sequence, and then the data is transmitted to the optical fiber circuit after parallel-serial conversion by the Transceiver Transceiver.
Preferably, the data combining module is configured to combine the IP protocol data packet sent by the interface conversion module with the received link control protocol frame and network control protocol frame, and output the combined data packet to the bit width conversion module.
Preferably, the HDLC encapsulation module is configured to encapsulate the bandwidth-converted data according to an HDLC protocol, and output an HDLC format frame.
Preferably, the data mapping virtual container is configured to map HDLC format frames into VC-4/VC-4-4c concatenated frames.
Preferably, the frame header insertion and B1 calculation and scrambling module is configured to complete the insertion of the segment overhead and the management unit pointer. At the network node, the STM-N signal is scrambled prior to transmission, the digital signal sequence is scrambled, a B1 bit interleaved parity is regenerated, and inserted into the corresponding position of the frame header.
The POS interface capable of adapting to various rates disclosed by the invention solves the problem of high cost of the POS interface realized by an imported framer chip at present. And by realizing the design and the realization method of the POS interface with STN-N multiple rates on the FPGA chip, the interface rate is configured according to the requirement, the application range is wide, and the practicability is strong. The design structure provided by the invention can be suitable for the design and development of a chip special for a domestic POS interface/framer, and fills the blank in the technical field of POS framer chips in China.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A POS interface capable of adapting to a plurality of rates, the POS interface comprising an FPGA chip, the FPGA chip comprising: a Transceiver Transceiver, a frame searching and tracking module, a descrambling and B1 verification module, a pointer analyzing and monitoring module, a payload extracting module, an HDLC de-encapsulation module, a bit width conversion module, a PPP protocol analyzing module and an interface conversion module;
the Transceiver converts the received serial optical signals into parallel electrical signals, and transmits IP protocol data packets with the protocol number of 0x0021 to an interface conversion module after completing data processing by a frame search and frame tracking module, a descrambling and B1 verification module, a payload extraction module, an HDLC decapsulation module, a bit width conversion module and a PPP protocol analysis module in sequence, and converts the IP protocol data packets into Ethernet interface data for output.
2. The POS interface of claim 1, wherein the FPGA chip further comprises: the device comprises a data combining module, a bit width conversion module, an HDLC packaging module, a data mapping virtual container, a frame header insertion and B1 calculation and scrambling module;
the PPP protocol analysis module sends a network control protocol frame NCP with a protocol number of 0x8021 to the data combining module, and then the data processing is completed through the bit width conversion module, the HDLC packaging module, the data mapping virtual container, the frame header insertion and B1 calculation and the scrambling module in sequence, and the data is transmitted to the optical fiber circuit after parallel-serial conversion through the Transceiver Transceiver.
3. The POS interface capable of adapting to multiple rates according to claim 1 or 2, wherein the POS interface further comprises an optical module, one end of the optical module is connected with the optical fiber end, and the other end of the optical module is connected with the FPGA chip through a SerDes interface, so that the conversion of the high-speed SerDes interface of the optical signals and the electric signals of the optical fiber end is realized.
4. The POS interface capable of adapting to multiple rates of claim 1, wherein the POS interface further comprises a configuration interface, the configuration interface is an input signal interface configured for POS interface rate and CRC check mode, and the configuration interface is connected with a Transceiver Transceiver in an FPGA chip.
5. The POS interface of claim 2, wherein the frame search and frame tracking module is configured to perform frame search using a half search approach and perform frame tracking using a half frame header tracking approach, comprising:
if the frame head is not detected in four continuous frames, setting an out-of-position OOF alarm signal of the frame to indicate that the receiving line part detects that the frame is not synchronous; when two continuous frames detect the frame head, clearing OOF alarm signals;
in the OOF state, if the duration lasts for 3 milliseconds, setting a frame loss LOF; in the LOF state, if no OOF lasts for 3 milliseconds, the LOF is cleared;
if the data is normally 0 or 1 within 20 microseconds, the LOS is lost by the setting signal;
in the LOS state, if an incoming data frame header is found, the LOS is cleared.
6. The multi-rate-adaptable POS interface of claim 5, wherein the descrambling and B1 checking module is configured to descramble the scrambled SDH frame to recover the SDH frame, and the descrambling polynomial is 1+ X6+X7Meanwhile, the error code monitoring of the regeneration section is completed through B1 inspection, 8 bit groups are used for bit interleaving parity check, and data without error is checked and transmitted to a pointer analyzing and monitoring module;
the pointer analyzing and monitoring module extracts the management unit pointer corresponding to the SDH frame, analyzes the pointer fields of H1 and H2, determines the initial position of the VC frame in the payload of the SDH frame, and generates the frame header, the channel trace J0/J1 fields and the indication signal of the VC frame payload.
7. The multi-rate-adaptable POS interface of claim 6, wherein the payload extraction module is configured to strip payload from SDH frames based on an indication signal of a VC frame payload, and send the stripped payload to the HDLC decapsulation module;
the HDLC decapsulation module is configured to decapsulate the extracted data payload according to an HDLC protocol to obtain an output data frame;
the bit width conversion module is configured to realize the interconversion between the data bit width 8 bits and 32 bits;
the PPP protocol analysis module is configured to analyze the protocol field of the PPP frame, and send the IP protocol data packet with the protocol number of 0x0021 to the interface conversion module to be converted into Ethernet interface data; and sending the LCP and the 0x8021 LCP frames to the data combining module.
8. The POS interface capable of adapting to multiple rates of claim 7, wherein the data combining module is configured to combine the IP protocol data packet sent by the interface conversion module with the received link control protocol frame and network control protocol frame, and output the combined IP protocol data packet to the bit width conversion module.
9. The POS interface capable of adapting to multiple rates of claim 8,
the HDLC encapsulation module is configured to encapsulate the data after bit width conversion according to an HDLC protocol and output an HDLC format frame;
the data mapping virtual container is configured to map HDLC format frames into VC-4/VC-4-4c concatenated frames.
10. The POS interface capable of adapting to multiple rates of claim 9,
the frame header insertion and B1 calculation and scrambling module is configured to complete insertion section overhead and management unit pointers;
at the network node, the STM-N signal is scrambled prior to transmission, the digital signal sequence is scrambled, a B1 bit interleaved parity is regenerated, and inserted into the corresponding position of the frame header.
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