CN114389753B - POS interface capable of adapting to various rates - Google Patents
POS interface capable of adapting to various rates Download PDFInfo
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- CN114389753B CN114389753B CN202111535602.3A CN202111535602A CN114389753B CN 114389753 B CN114389753 B CN 114389753B CN 202111535602 A CN202111535602 A CN 202111535602A CN 114389753 B CN114389753 B CN 114389753B
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- 238000013506 data mapping Methods 0.000 claims description 9
- 239000013307 optical fiber Substances 0.000 claims description 9
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- 238000007689 inspection Methods 0.000 claims description 3
- 230000001172 regenerating effect Effects 0.000 claims description 3
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- 238000004891 communication Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/18—Protocol analysers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
- H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
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Abstract
The invention discloses a POS interface capable of adapting to various rates, which comprises an FPGA chip, wherein the FPGA chip comprises: the system comprises a Transceiver, a frame searching and tracking module, a descrambling and B1 checking module, a pointer analyzing and monitoring module, a payload extracting module, an HDLC (high-level data link control) unpacking module, a bit width converting module, a PPP (point to point) protocol analyzing module and an interface converting module; the Transceiver converts the received serial optical signals into parallel electrical signals, and after finishing data processing by the frame searching and frame tracking module, the descrambling and B1 checking module, the payload extracting module, the HDLC unpacking module, the bit width converting module and the PPP protocol analyzing module, the Transceiver sends an IP protocol data packet with the protocol number of 0x0021 to the interface converting module to be converted into Ethernet interface data for output. The structure design of the POS interface overcomes the problem of high cost of the traditional structure, and the POS interface can adapt to various speeds.
Description
Technical Field
The invention belongs to the field of data transmission, and particularly relates to a POS interface capable of adapting to various rates.
Background
POS is called Packet Over SDH, also called IP Over SDH, which is a technology for transmitting IP data service through high-speed transmission channel provided by SDH, and maps variable length IP data package into SDH load to provide high-speed, reliable and point-to-point data connection.
At present, both the middle-end router equipment and the high-end router equipment at home and abroad are provided with POS interface cards, and the design and the realization of the POS interfaces are the difficulties in developing the POS interface cards. The POS interface is typically implemented using a POS framer chip design, with the framer chip PM53XX provided by the PMC company of the canadian optical communication scheme solution being most widely used. The scheme for realizing the POS interface by adopting the framing device has the advantages of maturity, easiness in use, simplicity in design and the like, but also has the defect of high chip price and the like.
Thus, there is a need for a low cost POS interface that can accommodate multiple rates.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a POS interface capable of adapting to various rates.
The aim of the invention is achieved by the following technical scheme:
a POS interface capable of adapting to multiple rates, the POS interface comprising an FPGA chip comprising: the system comprises a Transceiver, a frame searching and tracking module, a descrambling and B1 checking module, a pointer analyzing and monitoring module, a payload extracting module, an HDLC (high-level data link control) unpacking module, a bit width converting module, a PPP (point to point) protocol analyzing module and an interface converting module; the Transceiver converts the received serial optical signals into parallel electrical signals, and after finishing data processing by the frame searching and frame tracking module, the descrambling and B1 checking module, the payload extracting module, the HDLC unpacking module, the bit width converting module and the PPP protocol analyzing module, the Transceiver sends an IP protocol data packet with the protocol number of 0x0021 to the interface converting module to be converted into Ethernet interface data for output.
According to a preferred embodiment, the FPGA chip further comprises: the device comprises a data combining module, a bit width conversion module, an HDLC packaging module, a data mapping virtual container, a frame header insertion and B1 calculation and scrambling module; the PPP protocol analysis module sends the network control protocol frame NCP with the protocol number of 0x8021 to the data combining module, and then the data processing is completed through the bit width conversion module, the HDLC packaging module, the data mapping virtual container, the frame header insertion and the B1 calculation and scrambling module in sequence, and the data processing is sent to the optical fiber line after parallel-serial conversion through the Transceiver.
According to a preferred embodiment, the POS interface further includes an optical module, where one end of the optical module is connected to the optical fiber end, and the other end of the optical module is connected to the FPGA chip through the SerDes interface, so as to implement conversion of the optical signal and the electrical signal of the optical fiber end by the high-speed SerDes interface
According to a preferred embodiment, the POS interface further comprises a configuration interface, the configuration interface is an input signal interface configured by POS interface speed and CRC check mode, and the configuration interface is connected to a Transceiver in the FPGA chip.
According to a preferred embodiment, the frame searching and frame tracking module is configured to perform frame searching in a half-search mode and frame tracking in a half-frame header tracking mode, and includes: setting a frame out-of-position OOF alarm signal if a frame header is not detected in four continuous frames, wherein the frame out-of-position OOF alarm signal indicates that a receiving line part detects that frames are not synchronous; when two continuous frames detect the frame header, the OOF alarm signal is cleared; in the OOF state, if it lasts 3 milliseconds, the set frame loses LOF; in the LOF state, if there is no OOF for 3 milliseconds, the LOF is cleared; data is always 0 or 1 in 20 microseconds, and the LOSs of signal LOS is set;
in the LOS state, if the incoming data frame header is found, the LOS is cleared.
According to a preferred embodiment, the descrambling and B1 checking module is configured to descramble the scrambled SDH frame to recover the SDH frame, the descrambling polynomial being 1+x 6 +X 7 Meanwhile, the error code monitoring of the regeneration section is finished through B1 inspection, 8 bit groups are used as bit interleaved parity check, and error-free data are checked and transmitted to a pointer analysis and monitoring module.
According to a preferred embodiment, the pointer parsing and monitoring module extracts the SDH frame corresponding management unit pointer, parses the H1, H2 pointer fields, determines the starting position of the VC frame in the SDH frame payload, and generates the frame header, the channel trace J0/J1 field, and an indication signal of the VC frame payload.
According to a preferred embodiment, the payload extraction module is configured to strip the payload from the SDH frame based on the indication signal of the VC frame payload, and send the payload to the HDLC decapsulation module; the HDLC decapsulation module is configured to decapsulate the extracted data payload according to an HDLC protocol to obtain an output data frame; the bit width conversion module is configured to realize the mutual conversion between 8 bits and 32 bits of data bit width; the PPP protocol analysis module is configured to analyze the protocol field of the PPP frame, and send the IP protocol data packet with the protocol number of 0x0021 to the interface conversion module to be converted into Ethernet interface data; and the link control protocol frame LCP with the protocol number of 0xC021 and the network control protocol frame with the protocol number of 0x8021 are sent to a data combining module.
According to a preferred embodiment, the data combining module is configured to combine the IP protocol data packet sent by the interface conversion module with the received link control protocol frame and network control protocol frame, and output the combined IP protocol data packet to the bit width conversion module.
According to a preferred embodiment, the HDLC encapsulation module is configured to encapsulate the bit-width converted data according to an HDLC protocol, and output an HDLC format frame; the data mapping virtual container is configured to map HDLC format frames into VC-4/VC-4-4c concatenated frames.
According to a preferred embodiment, the frame header insertion and B1 calculation and scrambling module is configured to complete the insertion section overhead and the management unit pointer; at the network node, the STM-N signal is scrambled prior to transmission, scrambling the digital signal sequence, regenerating the B1 bit interleaved parity, and inserting into the corresponding position of the frame header.
The foregoing inventive concepts and various further alternatives thereof may be freely combined to form multiple concepts, all of which are contemplated and claimed herein. Various combinations will be apparent to those skilled in the art from a review of the present disclosure, and are not intended to be exhaustive or all of the present disclosure.
The invention has the beneficial effects that: the POS interface capable of adapting to various rates solves the problem of high cost of realizing the POS interface by the imported framer chip at present. And through realizing the design and implementation method of STN-N multiple speed POS interface on FPGA chip, interface speed is configured as required, the application scope is wide, the practicability is strong.
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FIG. 1 is a schematic diagram of the structure of a POS interface capable of adapting to multiple rates in accordance with the present invention;
fig. 2 is a block diagram of the logic architecture of an FPGA chip in a POS interface architecture capable of adapting to multiple rates in accordance with the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that, for the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments.
Example 1:
referring to fig. 1, the invention discloses a POS interface capable of adapting to various rates, wherein the POS interface comprises an optical module, an FPGA chip, a configuration interface, a status information interface and an ethernet interface.
One end of the optical module is connected with the optical fiber end, and the other end of the optical module is connected with the FPGA chip through the SerDes interface, so that the conversion of the high-speed SerDes interface of optical signals and electric signals of the optical fiber end is realized.
The FPGA chip is also respectively connected with a configuration interface, a state information interface and an Ethernet interface.
The configuration interface is an input signal interface configured by POS interface speed and CRC check mode, and is connected with a Transceiver in the FPGA chip. Typically GPIO
(General-Purpose Input/Output).
And can be obtained through a state information interface: outputting state information of POS interface speed, state information of CRC (Cycilc Redundancy Check) check mode, POS interface on-off state, POS link on-off state, receiving and transmitting packet number, byte number, error packet number, packet loss number of RGMII interface, etc.
Preferably, as shown in fig. 2, in this embodiment, the FPGA chip includes two input-output links.
Preferably, each input-output link includes the following functional modules: the system comprises a Transceiver, a frame searching and tracking module, a descrambling and B1 checking module, a pointer analyzing and monitoring module, a payload extracting module, an HDLC (high-level data link control) decapsulating module, a bit width converting module, a PPP (point to point) protocol analyzing module and an interface converting module.
The Transceiver converts the received serial optical signal into parallel electrical signals, and after finishing data processing by the frame searching and frame tracking module, the descrambling and B1 checking module, the payload extracting module, the HDLC unpacking module, the bit width converting module and the PPP protocol analyzing module, the Transceiver sends an IP protocol data packet with the protocol number of 0x0021 to the interface converting module to be converted into Ethernet interface data for output.
Preferably, the Transceiver is configured to perform the mutual conversion of the serial optical signal and the parallel electrical signal, and the configuration of the STM-N multiple rate modes is performed in the module. According to the input POS interface rate and CRC check mode configuration information, a Transceiver soft core is generated by a Transceiver adopting a dynamic local reconfiguration technology of an FPGA according to the configuration information, and a serial optical signal is converted into a parallel binary electric signal.
By taking advantage of the advantages of reconfigurable FPGA logic design, parallel pipeline processing and the like, multiple STM-N (synchronous transfer mode, synchronous transmission modes) are realized, such as a POS interface with multiple rates of STM-1 (155.52 Mbps), STM-4 (622.08 Mbps), STM-16 (2488.32 Mbps), STM-64 (9953.28 Mbps) and STM-256 (39813.12 Mbps) which can be configured as required.
Preferably, the frame searching and frame tracking module is configured to perform frame searching in a half-searching mode and frame tracking in a half-frame header tracking mode. The method specifically comprises the following steps: 1) Setting an OOF (out of frame) alarm signal if no frame header is detected for four consecutive frames, indicating that the receiving line part detects that the frames are not synchronized; when two continuous frames detect the frame header, the OOF alarm signal is cleared; 2) In the OOF state, if 3 milliseconds persist, LOF (loss of frame) is set; in the LOF state, if there is no OOF for 3 milliseconds, the LOF is cleared; 3) Data is always "0" or always "1" in 20 microseconds, and LOS (LOSs of signal) is set; in the LOS state, if the incoming data frame header is found, the LOS is cleared.
Preferably, the descrambling and B1 checking module is configured to descramble the scrambled SDH frame to recover the SDH frame, where the descrambling polynomial is 1+x 6 +X 7 . Meanwhile, the error code monitoring of the regeneration section is completed through B1 inspection, 8 bit groups are used for bit interleaved parity check, and error-free data are checked and transmitted to a pointer analysis and monitoring module.
Preferably, the pointer analyzing and monitoring module extracts pointers of management units corresponding to the SDH frame, analyzes the fields of the pointers of H1 and H2, determines the starting position of the VC frame in the payload of the SDH frame, and generates indication signals of frame header, channel trace J0/J1 fields and the VC frame payload.
Specifically, the alarm model LOS, LOF, OOF generated in the frame tracking process is detected, and the software inquiry of the microprocessor is supported. All regeneration segment, multiplex segment, and channel overhead (including B1, B2, B3, E1, F1, etc.) bytes are monitored. Alarm signals are detected and received, and error counts for each stage of performance monitoring are accumulated, resulting in far-end error indications M1, G1 for the stages and channels. The C2, J0 and J1 bytes are extracted and the corresponding alarms can be inserted back by the software.
Preferably, the payload extraction module is configured to strip the payload from the SDH frame based on the indication signal of the VC frame payload, and send the payload to the HDLC decapsulation module.
Preferably, the HDLC decapsulation module is configured to decapsulate the extracted data payload according to an HDLC protocol to obtain an output data frame.
Preferably, the bit-width conversion module is configured to effect a mutual conversion between 8 bits and 32 bits of data bit-width.
Preferably, the PPP protocol parsing module is configured to parse a protocol field of a PPP frame, and send an IP protocol data packet with a protocol number of 0x0021 to the interface converting module to convert the IP protocol data packet into ethernet interface data; and the link control protocol frame LCP with the protocol number of 0xC021 and the network control protocol frame with the protocol number of 0x8021 are sent to a data combining module.
Preferably, each input-output link further comprises the following functional modules: the device comprises a data combining module, a bit width conversion module, an HDLC packaging module, a data mapping virtual container, a frame header insertion and B1 calculation and scrambling module.
The PPP protocol analysis module sends the network control protocol frame NCP with the protocol number of 0x8021 to the data combining module, and then the data processing is completed through the bit width conversion module, the HDLC encapsulation module, the data mapping virtual container, the frame header insertion and the B1 calculation and scrambling module in sequence, and the data processing is sent to the optical fiber line after the parallel-serial conversion through the Transceiver of the Transceiver.
Preferably, the data combining module is configured to combine the IP protocol data packet sent by the interface conversion module with the received link control protocol frame and network control protocol frame, and output the combined IP protocol data packet to the bit width conversion module.
Preferably, the HDLC encapsulation module is configured to encapsulate the data after the bit width conversion according to the HDLC protocol, and output an HDLC format frame.
Preferably, the data mapping virtual container is configured to map HDLC format frames into VC-4/VC-4-4c concatenated frames.
Preferably, the frame header insertion and B1 computation and scrambling module is configured to complete insertion of segment overhead and management unit pointers. At the network node, the STM-N signal is scrambled prior to transmission, scrambling the digital signal sequence, regenerating the B1 bit interleaved parity, and inserting into the corresponding position of the frame header.
The POS interface capable of adapting to various rates solves the problem of high cost of realizing the POS interface by the imported framer chip at present. And through realizing the design and implementation method of STN-N multiple speed POS interface on FPGA chip, interface speed is configured as required, the application scope is wide, the practicability is strong. The design structure provided by the invention can be suitable for the design and development of domestic POS interface/framing device special chips, and fills the blank in the technical field of domestic POS framing device chips.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (8)
1. A POS interface capable of adapting to multiple rates, the POS interface comprising an FPGA chip comprising: the system comprises a Transceiver, a frame searching and tracking module, a descrambling and B1 checking module, a pointer analyzing and monitoring module, a payload extracting module, an HDLC (high-level data link control) unpacking module, a bit width converting module, a PPP (point to point) protocol analyzing module and an interface converting module;
the Transceiver converts the received serial optical signals into parallel electrical signals, and sequentially passes through a frame searching and frame tracking module, a descrambling and B1 checking module, a payload extracting module, an HDLC (high-level data Link control) unpacking module, a bit width converting module and a PPP (point-to-point protocol) analyzing module to finish data processing, and then sends an IP (Internet protocol) data packet with the protocol number of 0x0021 to the interface converting module to be converted into Ethernet interface data for output;
the FPGA chip further includes: the device comprises a data combining module, a bit width conversion module, an HDLC packaging module, a data mapping virtual container, a frame header insertion and B1 calculation and scrambling module;
the PPP protocol analysis module sends a network control protocol frame NCP with the protocol number of 0x8021 to the data combining module, and then sequentially completes data processing through the bit width conversion module, the HDLC packaging module, the data mapping virtual container, the frame header insertion and the B1 calculation and scrambling module, and then sends the data processing to the optical fiber line after parallel-serial conversion through the Transceiver;
the frame searching and frame tracking module is configured to perform frame searching in a half-searching mode and frame tracking in a half-frame head tracking mode, and comprises:
setting a frame out-of-position OOF alarm signal if a frame header is not detected in four continuous frames, wherein the frame out-of-position OOF alarm signal indicates that a receiving line part detects that frames are not synchronous; when two continuous frames detect the frame header, the OOF alarm signal is cleared;
in the OOF state, if it lasts 3 milliseconds, the set frame loses LOF; in the LOF state, if there is no OOF for 3 milliseconds, the LOF is cleared;
data is always 0 or 1 in 20 microseconds, and the LOSs of signal LOS is set;
in the LOS state, if the incoming data frame header is found, the LOS is cleared.
2. The POS interface of claim 1, further comprising an optical module, wherein one end of the optical module is connected to the optical fiber end, and the other end of the optical module is connected to the FPGA chip via the SerDes interface, so as to implement conversion of optical signals and electrical signals of the optical fiber end.
3. The POS interface capable of adapting to multiple rates of claim 1 further comprising a configuration interface, the configuration interface being an input signal interface for POS interface rate and CRC check mode configuration, the configuration interface being coupled to a Transceiver in an FPGA chip.
4. The POS interface capable of adapting to multiple rates according to claim 1, wherein the descrambling and B1 checking module is configured to perform descrambling of the scrambled SDH frame to recover the SDH frame, the descrambling polynomial being 1+x 6 +X 7 Meanwhile, the error code monitoring of the regeneration section is finished through B1 inspection, 8 bit groups are used as bit interleaved parity check, and error-free data are checked and transmitted to a pointer analysis and monitoring module;
the pointer analyzing and monitoring module extracts pointers of management units corresponding to the SDH frame, analyzes the fields of the pointers of H1 and H2, determines the starting position of the VC frame in the payload of the SDH frame, and generates indication signals of frame header, channel trace J0/J1 fields and the VC frame payload.
5. The POS interface capable of adapting to multiple rates according to claim 4, wherein the payload extraction module is configured to strip out the payload from the SDH frame based on an indication signal of the VC frame payload, and send the payload to the HDLC decapsulation module;
the HDLC decapsulation module is configured to decapsulate the extracted data payload according to an HDLC protocol to obtain an output data frame;
the bit width conversion module is configured to realize the mutual conversion between 8 bits and 32 bits of data bit width;
the PPP protocol analysis module is configured to analyze the protocol field of the PPP frame, and send the IP protocol data packet with the protocol number of 0x0021 to the interface conversion module to be converted into Ethernet interface data; and the link control protocol frame LCP with the protocol number of 0xC021 and the network control protocol frame with the protocol number of 0x8021 are sent to a data combining module.
6. The POS interface capable of adapting to multiple rates according to claim 5, wherein the data combining module is configured to combine the IP protocol data packet sent by the interface conversion module with the received link control protocol frame and network control protocol frame, and output the combined IP protocol data packet to the bit width conversion module.
7. The POS interface capable of adapting to multiple rates of claim 6 wherein,
the HDLC packaging module is configured to package the data subjected to the bit width conversion according to an HDLC protocol and output an HDLC format frame;
the data mapping virtual container is configured to map HDLC format frames into VC-4/VC-4-4c concatenated frames.
8. The POS interface capable of adapting to multiple rates of claim 7,
the frame header insertion and B1 calculation and scrambling module is configured to complete insertion section overhead and management unit pointers;
at the network node, the STM-N signal is scrambled prior to transmission, scrambling the digital signal sequence, regenerating the B1 bit interleaved parity, and inserting into the corresponding position of the frame header.
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Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316146A (en) * | 1999-07-27 | 2001-10-03 | 信息产业部武汉邮电科学研究院 | Interfacing apparatus and method for adapting ethernet directly to physical channel |
| KR20020041315A (en) * | 2000-11-27 | 2002-06-01 | 김재근 | 622Mbps level Packet over SDH equipment with ATM interworking function |
| CN1392684A (en) * | 2001-06-15 | 2003-01-22 | 北京邮电大学 | Wavelength division multiplexing optical network transmission adapting method for IP data |
| US6697373B1 (en) * | 2000-01-18 | 2004-02-24 | Mark Henrik Sandstrom | Automatic method for dynamically matching the capacities of connections in a SDH/SONET network combined with fair sharing of network resources |
| CN1499776A (en) * | 2002-11-11 | 2004-05-26 | 华为技术有限公司 | Method of flow-concourse and flow-distribution in multi speed rates synchronous digital network and device |
| CN1543162A (en) * | 2003-11-06 | 2004-11-03 | 西安电子科技大学 | Method for hybrid transmission of variable-length data packet and fixed length cell, and adaptation device |
| CN1980107A (en) * | 2006-12-11 | 2007-06-13 | 烽火通信科技股份有限公司 | Method for realizing STM-256 frame-former |
| CN101072036A (en) * | 2007-04-29 | 2007-11-14 | 浙江大学 | Series low-density even-odd check code decoder for supporting multi-rate multi-code-length |
| CN101741865A (en) * | 2010-01-28 | 2010-06-16 | 中国电子科技集团公司第五十四研究所 | High-speed reconfigurable data forwarding device |
| CN101795200A (en) * | 2010-01-28 | 2010-08-04 | 中国电子科技集团公司第五十四研究所 | Multi-rate POS interface adaptive transmission method |
| CN101795274A (en) * | 2010-01-28 | 2010-08-04 | 中国电子科技集团公司第五十四研究所 | Routing device supporting safe multi-service multifunctional access |
| CN201699737U (en) * | 2010-01-28 | 2011-01-05 | 中国电子科技集团公司第五十四研究所 | High-performance communication processing and control platform device |
| US8180919B1 (en) * | 2004-07-30 | 2012-05-15 | Xilinx, Inc. | Integrated circuit and method of employing a processor in an integrated circuit |
| CN104506451A (en) * | 2014-12-24 | 2015-04-08 | 中国电子科技集团公司第五十四研究所 | POS (packet over SONET (synchronous optical network)/SDH (synchronous digital hierarchy)) data link layer classification processing device based on FPGA (field programmable gate array) |
| CN104580031A (en) * | 2015-01-28 | 2015-04-29 | 中国人民解放军国防科学技术大学 | Multi-protocol link encapsulation technique based POS (packet over synchronous optical network/internet protocol) frame decoding and framing device and method thereof |
| CN108683962A (en) * | 2018-07-24 | 2018-10-19 | 国家电网公司 | A kind of network system based on SDH Yu PON technologies |
| CN109120369A (en) * | 2018-11-23 | 2019-01-01 | 湖南有马信息技术有限公司 | A kind of SDH data processing method, system and relevant apparatus |
| CN111245550A (en) * | 2020-01-14 | 2020-06-05 | 北京恒光信息技术股份有限公司 | SDH signal processing method, device and system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1246012A (en) * | 1999-07-14 | 2000-03-01 | 邮电部武汉邮电科学研究院 | Adaptation method for making internet be compatible with synchronous digital system |
-
2021
- 2021-12-15 CN CN202111535602.3A patent/CN114389753B/en active Active
Patent Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316146A (en) * | 1999-07-27 | 2001-10-03 | 信息产业部武汉邮电科学研究院 | Interfacing apparatus and method for adapting ethernet directly to physical channel |
| US6697373B1 (en) * | 2000-01-18 | 2004-02-24 | Mark Henrik Sandstrom | Automatic method for dynamically matching the capacities of connections in a SDH/SONET network combined with fair sharing of network resources |
| KR20020041315A (en) * | 2000-11-27 | 2002-06-01 | 김재근 | 622Mbps level Packet over SDH equipment with ATM interworking function |
| CN1392684A (en) * | 2001-06-15 | 2003-01-22 | 北京邮电大学 | Wavelength division multiplexing optical network transmission adapting method for IP data |
| CN1499776A (en) * | 2002-11-11 | 2004-05-26 | 华为技术有限公司 | Method of flow-concourse and flow-distribution in multi speed rates synchronous digital network and device |
| CN1543162A (en) * | 2003-11-06 | 2004-11-03 | 西安电子科技大学 | Method for hybrid transmission of variable-length data packet and fixed length cell, and adaptation device |
| US8180919B1 (en) * | 2004-07-30 | 2012-05-15 | Xilinx, Inc. | Integrated circuit and method of employing a processor in an integrated circuit |
| CN1980107A (en) * | 2006-12-11 | 2007-06-13 | 烽火通信科技股份有限公司 | Method for realizing STM-256 frame-former |
| CN101072036A (en) * | 2007-04-29 | 2007-11-14 | 浙江大学 | Series low-density even-odd check code decoder for supporting multi-rate multi-code-length |
| CN101741865A (en) * | 2010-01-28 | 2010-06-16 | 中国电子科技集团公司第五十四研究所 | High-speed reconfigurable data forwarding device |
| CN101795200A (en) * | 2010-01-28 | 2010-08-04 | 中国电子科技集团公司第五十四研究所 | Multi-rate POS interface adaptive transmission method |
| CN101795274A (en) * | 2010-01-28 | 2010-08-04 | 中国电子科技集团公司第五十四研究所 | Routing device supporting safe multi-service multifunctional access |
| CN201699737U (en) * | 2010-01-28 | 2011-01-05 | 中国电子科技集团公司第五十四研究所 | High-performance communication processing and control platform device |
| CN104506451A (en) * | 2014-12-24 | 2015-04-08 | 中国电子科技集团公司第五十四研究所 | POS (packet over SONET (synchronous optical network)/SDH (synchronous digital hierarchy)) data link layer classification processing device based on FPGA (field programmable gate array) |
| CN104580031A (en) * | 2015-01-28 | 2015-04-29 | 中国人民解放军国防科学技术大学 | Multi-protocol link encapsulation technique based POS (packet over synchronous optical network/internet protocol) frame decoding and framing device and method thereof |
| CN108683962A (en) * | 2018-07-24 | 2018-10-19 | 国家电网公司 | A kind of network system based on SDH Yu PON technologies |
| CN109120369A (en) * | 2018-11-23 | 2019-01-01 | 湖南有马信息技术有限公司 | A kind of SDH data processing method, system and relevant apparatus |
| CN111245550A (en) * | 2020-01-14 | 2020-06-05 | 北京恒光信息技术股份有限公司 | SDH signal processing method, device and system |
Non-Patent Citations (3)
| Title |
|---|
| E. Beier ; DeTeSystem ; .MAPOS/PPP Tunneling mode.IETF rfc3186.2001,全文. * |
| GFP在POS接口应用的可行性分析;马琳;电信科学(06);全文 * |
| S. Shimizu ; T. Kawano ; K. Murakami ; NTT Network Innovation Labs. * |
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