KR20000046316A - Multiplexor between administrative unit signal and synchronous transport module signal in synchronous transport apparatus - Google Patents

Abstract

PURPOSE: A multiplexor between an administrative unit signal and a synchronous transport module signal in the synchronous transport apparatus is provided to multiplex an administrative unit-3(AU-3) into a synchronous transport module-1(STM-1). CONSTITUTION: A transmission timing generation part(480) receives a main clock signal from a clock supply part(510) and generates control clock signals. A serial/parallel conversion and multiplexing part(410) converts a required administrative unit-3(AU-3) inputted in serial into parallel signals using relevant clock signals among the control clock signals. A multiplexor section overhead processing part(420) inserts required multiplexor section overheads into the signals outputted from the serial/parallel conversion and multiplexing part(410). A regenerator section overhead processing part(440) inserts required regenerator section overheads into the signals outputted from the multiplexor section overhead processing part(420). A scrambler(450) carries out a required scrambling processing for the signals outputted from the regenerator section overhead processing part(440). A second parity generation part(430) outputs a bit interleaved parity check byte of 24 bits for required part of the signals outputted through the multiplexor section overhead processing part(420). A first parity generation part(460) outputs a bit interleaved parity check byte of 8 bits for the regenerator section overhead out of the signals outputted from the scrambler(450).

Description

A unit of multiplexing Administrative Unit-3 signals to Synchronous Transport Module-1 signals in synchronous communication equipments

The present invention relates to a multiplexing device between a management unit signal and a synchronous transport module signal in a synchronous transmission device. In particular, three management unit signals (AU-) in a multiplexing process according to a synchronous multiplexing procedure in a communication device using a synchronous transmission method. 3: relates to an apparatus for multiplexing Administrative Unit-3) into a synchronous transport module signal (STM-1).

1 is a basic network configuration diagram of an optical subscriber transmission device, which is an example of a communication device using a synchronous transmission method, and includes a main station 10 (Central Office Terminal) and a remote station (Remote Terminal 11). At this time, the master station 10 is connected to each subscriber through a general switching line, a leased line, a local area network (LAN), and the like, and these subscribers are connected to the ordinary telephone subscriber or the leased line subscriber through the remote station 11. Connected with

The main station 10 and the remote station 11 constituting such an optical subscriber transmission device are connected by the optical path 12 to perform communication by light with each other. At this time, the communication by the light between the master station 10 and the remote station 11 is performed by using a synchronous transmission method. In the synchronous transmission method, each signal is multiplexed according to a synchronous digital hierarchy (SDH). It is multiplexed by the procedure and then transmitted and received.

FIG. 2 is a diagram illustrating a mapping structure of a DS1 signal to a synchronous transport module signal (STM-1) and a DS1 signal 110 is mapped to a lower box C-11: 120 having a container structure. When the lower path overhead 131 is added to the lower box C-11: 120, the lower virtual box 130 becomes a lower virtual box 130.

In addition, when a pointer 141 indicating the position of the lower virtual box 130 is added to the lower virtual box VC-11: 130, it becomes a level unit signal TU-11: 140, and the level unit signal 140 Four are gathered to form a hierarchical unit group signal 150 (TUG-2). The pointer 151 to the four hierarchical unit signals (TU-11: 140) is the front of the hierarchical unit group signal 150: TUG-2. It is located at all.

When seven hierarchical unit group signals 150 (TUG-2) are gathered and the upper path overhead 161 is added to the foremost part, a high-level virtual box signal (VC-3: 160) is generated. When the pointer 171 is added to the 160, a management unit signal (AU-3: 170) is generated, and three management unit signals (170) are gathered to form a management unit group signal (180: AUG). When a section overhead is added to the unit group signal 180 (AUG), the synchronous transport module signal STM-1: 190 is finally generated.

As described above, the DS1 signal 110 input to the optical subscriber transmission apparatus using the synchronous transmission method is made into the synchronous transport module signal (STM-1: 190) after each multiplexing process, and then the optical path 12 is opened. Is sent through.

3 is a structural diagram of a synchronous transmission module signal STM-1, in which three management unit signals AU-3 are entered into one synchronous transmission module signal 190: STM-1, and one synchronous transmission module signal. (190: STM-1) has a total of 2430 bytes, which is configured as a 270-byte row and a 9-byte column. In addition, the section overhead 191 includes a player section overhead 192 and a multiplexer section overhead 193.

At this time, among the data of the columns 1 to 9 in the synchronous transmission module signal 190: STM-1, rows 1 to 3 are places where the player section overhead 192 is located, and rows 5 to 9 are This is where the multiplexer interval overhead 193 is located.

In addition, 9 bytes of 10 columns are places where the upper path overhead (POH) is located, and 270 columns of the remaining 11 columns are used as payload spaces, and the pay of the management unit signal (AU-3) is performed. The load is located. In addition, the management unit signal pointers located in the fourth row of columns 1 to 9 are processed by the management unit signal AU-3, the transmitted signals are simply multiplexed, and the received signals are predetermined. It is processed after being interpreted by the pointer processing unit.

Table 1 below summarizes each overhead byte and its role of the synchronous transmission module signal 190 (STM-1) shown in FIG.

Segment overhead Frame bytes A1, A2 A1 = "11110110" A2 = "101000" Error check byte B1 Position at player interval overhead (8 bits) B2 Position in multiplexer interval overhead (24-bit) Data communication channel D1, D2, D3 For maintenance (192 Kbits / s) D4-D12 For maintenance (576 Kbits / s) Batting line E1, E2 Tarmac voice channel STM-1 signal identifier C1 Use to identify each STM-1 signal Transmission line protection byte K1, K2 Used for transmission line switching User channel byte F1 Custom bytes Pointer H1, H2 Marks the starting point of synchronized payload H3 Stuffing byte Path overhead Error check byte B3 For error checking on paths (8 bits) Alert send byte C2, G1 For sending alarms on path Path trace bytes J1 For verifying continuous connection

Specifically, the function of each overhead byte of Table 1 shown above is a frame byte (A1: 3 bytes, A2: 3 bytes) to specify the initial position of the corresponding synchronous transport module signal, and the error checking byte ( B1, B2) are used to check for errors through bit interleaved parity (BIP).

The byte for the data communication channel (DCC) is composed of the first data communication byte (D1) to the twelfth data communication byte (D12), and the first data communication byte (D1) to the third data communication byte (D3). ) Is used to transmit and receive maintenance data of 192 Kbits / sec, and the fourth data communication byte D4 to twelfth data communication byte D12 are used to transmit and receive maintenance data of 576 Kbits / sec.

The first pruning line byte E1 and the second pruning line byte E2 are channels used for transmitting and receiving voice data through the order wire, and the synchronous transport module signal identification byte C1 is a signal for each synchronous transport module. To distinguish between them.

The first transmission path protection byte (K1) and the second transmission path protection byte (K2) used for transmission channel switching are used to change the transmission path in case of an error in the transmission path, and the user defined byte (F1) is used for each user. Can be used according to.

The management unit signal pointers H1, H2 and H3 are used to indicate the point where the payload of each management unit signal AU-3 is loaded, and the path error check byte B3 is displayed on the path. Used for error checking.

In addition, the alert transmission byte (C2, G1) is used for the alert transmission on the path, the path trace byte (J1) is used to verify the continuous connection state.

As described above, the apparatus for performing communication using the synchronous transmission scheme adds the section overhead 191 including the above information to the three management unit signals AU-3 during the synchronous multiplexing procedure. There is a need for a device that makes the transmission module signal (STM-1).

Therefore, the present invention has been made to meet the above needs, and is used in the apparatus for performing communication using a synchronous transmission method, a clock supply unit for supplying a predetermined main clock signal, data for transmitting and receiving maintenance data Three management unit signals by operating together with a Data Communication Channel Unit (DCC Unit), a serial communication connecting device for serial connection with a predetermined external device, and a central processing unit (CPU) used as a main control device. It is an object of the present invention to provide an apparatus for generating a synchronous transmission module signal 190 (STM-1) by adding a predetermined section overhead 191 to AU-3.

In order to achieve the above object, the multiplexing device between the management unit signal and the synchronous transmission module signal in the synchronous transmission apparatus according to the present invention receives the main clock signal from the clock supply unit to generate predetermined control clock signals A timing generator; By using a corresponding clock signal among the main clock signal and the control clock signal, a predetermined number of management unit signals (AU-3) are serially received, converted into parallel signals, retimed, and multiplexed and output. Serial / parallel conversion and multiplexing unit; A multiplexer section overhead processor for inserting and outputting a predetermined multiplexer section overhead into a signal output from the serial / parallel conversion and multiplexer using the corresponding clock signal among the control clock signals; A player section overhead processor configured to insert a predetermined player section overhead into a signal output from the multiplexer section overhead processing section by using a corresponding clock signal among the control clock signals; A mixer for performing a predetermined scrambling process on the signal output from the player section overhead processor using the corresponding clock signal among the control clock signals; A second parity generating unit for outputting a 24-bit bit parity parity check byte (B2) for a predetermined portion of a signal output through the multiplexer section overhead processing unit using the corresponding clock signal among the control clock signals; And a first parity generator for outputting an 8 bit bit parity parity check byte B1 for a player section overhead among signals outputted from the mixer using the corresponding clock signals among the control clock signals. It is characterized by.

At this time, the serial / parallel conversion and multiplexing unit converts the predetermined number of management unit signals (AU-3) in parallel using the corresponding clock signal among the main clock signal and the control clock signal, respectively. An output serial / parallel converter; A retiming unit for retiming each parallel management unit signal (AU-3) output from the serial / parallel conversion unit by using a corresponding clock signal among the control clock signals; And a management unit signal multiplexing unit configured to multiplex each of the parallel management unit signals AU-3 outputted after being retimed from the retiming unit by using a corresponding clock signal among the control clock signals. It can implement preferably.

In addition, the multiplexer section overhead processing unit outputs the parallel management unit group output from the serial / parallel conversion and multiplexing unit according to a predetermined transmission management unit-alarm indication signal (AU-AIS) insertion command signal from the central processing unit. An alarm display signal processor between the multiplexing mechanism for outputting one of a signal AUG and predetermined alarm display signal data; A transmission path protection byte processing unit for dividing and outputting predetermined transmission path protection bytes (K1, K2) respectively inputted from the CPU using the corresponding clock signals among the control clock signals; High speed data communication which receives predetermined serial data from the data communication channel unit and divides the data into fourth data communication bytes D4 to 12th data communication bytes D12 by using corresponding clock signals among the control clock signals. A byte processing unit; A second pruning line byte processing unit which receives a predetermined spare byte and a second pruning line byte E2 and separately outputs each byte using a corresponding clock signal among the control clock signals; And a signal output from the alarm display signal processor between the multiplexing mechanisms, the 24-bit bit shifting parity byte (B2), the transmission path protection byte (K1, K2), using a corresponding clock signal among the control clock signals. An overhead processing unit for multiplexing mechanisms for receiving and multiplexing the fourth data communication byte D4 to the twelfth data communication byte D12, the reserved overhead byte, and the second pruning line byte E2, and outputting the multiplexed data in parallel. It can be implemented so that it may implement more preferably.

On the other hand, the player section overhead processing unit user channel byte processing unit for receiving a predetermined user defined byte (F1) and the synchronous transport module signal identification byte (C1) from the central processing unit, respectively; The predetermined serial data is received from the data communication channel unit using the corresponding clock signal among the control clock signals, and is divided into a first data communication byte D1 to a third data communication byte D3 and outputs the serial communication connection. A low-speed data communication byte processing unit which receives a predetermined first pruning line byte (E1) from the device and converts it to a transistor-transistor logic (TTL) level and outputs the converted low-speed data byte; According to the predetermined first summing line mode selection signal from the central processing unit, one of the first summing line byte E1 output from the low-speed data communication byte processing unit and the received first summing line byte E1 is selected. A first other short-circuit byte processing unit for outputting; Receives a predetermined multiplexer section warning display signal insertion command signal from the central processing unit, and accordingly selects and outputs one of a signal output from the multiplexer section overhead processing unit and a predetermined multiplexer section warning display signal (AIS) data. An alarm display signal processor between the playback mechanism; And a signal output from the alarm display signal processor between the playback mechanism, the predetermined frame byte (A1, A2), the user-defined byte (F1), and the synchronous transport module signal identification byte using the corresponding clock signal among the control clock signals. C1), a first data communication byte D1 to a third data communication byte D3, and a player section overhead processing unit for multiplexing and outputting the first pruning line byte E1 to be implemented. Can be.

1 is a block diagram of a basic network of an optical subscriber transmitter;

2 is a mapping structure diagram of a synchronous transport module signal STM-1 to a DS1 signal;

3 is a structural diagram of a synchronous transport module signal STM-1;

4 is a block diagram of the present invention;

5 is a detailed configuration diagram of a transmission timing generator;

6 is a detailed configuration diagram of a serial / parallel conversion and multiplexing unit;

7 is a detailed configuration diagram of a multiplexer section overhead processor;

8 is a detailed configuration diagram of a player section overhead processing unit;

9 is a schematic diagram of a mixer.

* Explanation of symbols for main parts of the drawings

400: multiplexer 410 of the present invention: serial / parallel conversion and multiplexing unit,

411: serial / parallel conversion unit 412: retiming unit

413: management unit signal multiplexing unit 420: multiplexer section overhead processing unit

421: transmission path protection byte processing unit 422: high-speed data communication byte processing unit

423: second short circuit line processing unit 424: overhead processing unit between multiplexing mechanisms

425: alarm display signal processing unit between multiplexing mechanism

430: a second parity generator

440: player section overhead processing unit

441: user channel byte processing unit 442: low speed data communication byte processing unit

443: first short circuit line processing unit 444: alarm display signal processing unit between the playback mechanism

445: player section overhead processing unit

450: mixer 460: first parity generator

480: transmission timing generator 481: timing unit

482: timing controller 510: clock supply unit

520: data communication channel unit 530: serial communication connection device

540: central processing unit

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a multiplexing apparatus 400 between a management unit signal (AU-3) and a synchronous transmission module signal (STM-1) in the synchronous transmission apparatus according to the present invention. 410, the multiplexer section overhead processor 420, the second parity generator 430, the player section overhead processor 440, the mixer 450, the first parity generator 460, and the transmission timing generation It is made up of a portion 480.

This invention is responsible for the overall control of the multiplexing device 400 of the present invention as the clock supply unit 510, maintenance data transmission and reception unit (520: DCC unit), serial communication connection device 530, and the main control device. It is connected to a predetermined external device such as a central processing unit 540 and operate together, the description of each external device will be described with the description of the components of the present invention.

FIG. 5 is a configuration diagram of the transmission timing generator 480, which includes a timing unit 481 and a timing controller 482, and receives a main clock signal (51.84 MHz, 8 KHz) from the clock supply unit 510. Generate control clock signals.

That is, a 155.52 MHz clock is generated by using a 51.84 MHz main clock signal supplied from the clock supply unit 510, and the 155.52 MHz clock is divided into eight by a main clock signal of 8 kHz to generate a 19.44 MHz clock (Tx19M). Each component is supplied as a main clock source.

The main clock source, the 19.44 MHz clock (Tx19M), is used to process the management unit signal (AU-3) with a data rate of 51.84 Mbps into 6.48 Mbps of parallel data, and also the synchronous transmission module signal 190 (STM-1). It is also used to handle the section overhead 191. The synchronous transmission module signal STM-1, which is finally formed, is transmitted using the above 155.52 MHz clock. Once again, the main clock source used in the present invention is a 19.44 MHz clock (Tx19M) synchronized with an 8 KHz clock provided from the clock supply 510.

Now, components of the transmission timing generator 480 will be described in detail.

The timing unit 481 generates a 155.52 MHz clock using a 51.84 MHz main clock signal supplied from the clock supply unit 510, and divides the 155.52 MHz clock into 8 KHz clocks to generate a 19.44 MHz clock (Tx19M).

Then, three 6.48 MHz clocks (6MA, 6MB, 6MC) divided into three 19.44 MHz (Tx19M) clocks using a 19.44 MHz clock (Tx19M) and an 8KHz main clock signal (6MA, 6MB, 6MC), and a 648KHz clock divided by 10 A 216KHz clock divided into three 648KHz clocks, a 72KHz clock divided into three 216KHz clocks, a 24KHz clock divided into three 72KHz clocks, and an 8KHz offset clock (8KOFFSET) divided into three 24KHz clocks. .

These clock signals for control use the same clock source for generating the corresponding clock for clocks having the same frequency, and use the same buffer to branch into multiple parts for use in multiple locations.

Meanwhile, the timing controller 482 receives and processes a 19.44 MHz clock (Tx19M), a 6.48 MHz clock, a 72 KHz clock, and an 8 KHz clock supplied from the timing unit 481, and outputs predetermined control clock signals.

Specifically, using the 8KHz offset clock (8KOFFSET) made by the timing unit 481, the player section overhead 192 and the multiplexer section overhead 193 of the synchronous transmission module signal 190: STM-1 Create a place to be located. That is, in order to process the necessary matters separately from the payload at the time of interface connection between the relay lines or the interface between the section lines, a control clock signal used to insert overhead signals is generated.

In addition, the control clock signal for each block of the overhead is generated using the generated control clock signal and transmitted to the multiplexer section overhead processor 420 and the player section overhead processor 440.

Meanwhile, the control clock signals output from the timing controller 482 are as follows.

First, the clock for the frame byte A1 position SOH1 is a clock made by retiming an 8KHz offset clock (8KOFFSET) made by dividing a 19.44 MHz clock (Tx19M) 2340 from the timing unit 481 to a 72KHz clock once. For example, the first signal of the section overhead 191 of the synchronous transmission module signal 190 (STM-1) is a clock signal generated for the first column A1.

The first error check byte (B1) position clock (SOH2) is a clock made by retiming the above 8KHz offset clock (8KOFFSET) twice with a 72KHz clock, and the section overhead of the synchronous transmission module signal 190 (STM-1). The second row of (191), the clock signal is made for the seat of the first column (B1).

The first data communication byte (D1) position clock (SOH3) is a clock made by retiming the above 8KHz offset clock (8KOFFSET) three times at 72KHz clock, and the section overhead of the synchronous transmission module signal 190 (STM-1). The third row of (191), the clock signal is made for the position of the first column (D1).

The clock SOH4 for the first management unit signal pointer H1 is a clock made by retiming the above 8KHz offset clock 8KOFFSET four times with a 72KHz clock, and the section over the synchronous transmission module signal 190 (STM-1). The clock signal is generated for the fourth row of the head 191 and the first column H1.

The second error check byte (B2) position clock (SOH5) is a clock made by retiming the above 8KHz offset clock (8KOFFSET) five times with a 72KHz clock, and the section overhead of the synchronous transmission module signal 190 (STM-1). In the fifth row of (191), the clock signal is created for the first column B2.

The fourth data communication byte (D4) position clock (SOH6) is a clock made by retiming the above 8KHz offset clock (8KOFFSET) six times with a 72KHz clock, and the section overhead of the synchronous transmission module signal 190 (STM-1). The sixth row of (191) is the clock signal produced for the first column (D4).

The seventh data communication byte (D7) position clock (SOH7) is a clock made by retiming the above 8KHz offset clock (8KOFFSET) seven times with a 72KHz clock, and the section over the synchronous transmission module signal 190 (STM-1). The clock signal is generated for the seventh row of the head 191, the first column D7.

The tenth data communication byte (D10) position clock (SOH8) is a clock made by retiming the above 8KHz offset clock (8KOFFSET) eight times with a 72KHz clock, and the section over the synchronous transmission module signal 190 (STM-1). The clock signal is generated for the eighth row of the head 191 and the first column D10.

The first preliminary overhead byte (Z1) position clock (SOH9) is a clock made by retiming the above 8KHz offset clock (8KOFFSET) nine times with a 72KHz clock, and is a section of the synchronous transmission module signal 190 (STM-1). The clock signal is generated for the ninth row of the overhead 191 and the first column Z1.

The clock signals SOH1-SOH9 are retimed one more time because one row of the section overhead 191 includes nine bytes.

6 is a detailed block diagram of the serial / parallel conversion and multiplexing unit 410, and includes a serial / parallel conversion unit 411, a retiming unit 412, and a management unit signal multiplexing unit 413. It receives three unit signals (AU-3), performs serial / parallel conversion, performs a retiming process, and then outputs the signals by 3: 1 multiplexing.

More specifically, the serial / parallel conversion unit 411 includes three management unit signals (AU-3: CH1AUD, CH2AUD, CH3AUD) and the main clock signal 51.84 MHz output from the clock supply unit 510, respectively. 8 KHz), a 6.48 MHz clock generated from the timing unit 481, and a reset signal RESET from the central processing unit 540 are received and converted into three management unit signals AU-3 in parallel. .

At this time, the serial management unit signal (AU-3) is input using the main clock signal of 51.84 MHz, and the control clock signal of 6.48 MHz is a clock signal obtained by dividing 51.84 MHz by 8, using the management unit signal. Convert (AU-3) to 8-bit parallel data. The management unit signals AU-3 converted in parallel by the three serial / parallel converters are sent to the retiming unit 412 through 8-bit data lines. Therefore, the transmission rate of the management unit signal AU-3 output from one serial / parallel converter 411 is 6.48 Mbps.

Here, the reset signal RESET sent from the CPU 540 is a signal for resetting the serial / parallel converter 411.

The retiming unit 412 is also composed of three. The three serial / parallel conversion units 411 each receive the parallel management unit signals AU-3 sent through 8-bit data lines, respectively, and also the timing unit 481. ) Receives control clock signals of 19.44MHz and 6.48MHz. Each of the parallel management unit signals (AU-3) is received using the 6.48 MHz clock and retimed from the 19.44 MHz clock (Tx19M), which is the main clock source for transmission, to the divided 6.48 MHz clock. It is for.

The management unit signal multiplexer 413 receives the parallel management unit signal AU-3 retimed from each of the three retiming units through an 8-bit data line, and then uses the main clock source Tx19M of 19.44 MHz. 3: 3 multiplex the output. That is, the signal output from the management unit signal multiplexer 413 is a management unit group signal 180 (AUG) multiplexed with three parallel management unit signals (AU-3), and is transmitted through an 8-bit data line. Therefore, the transfer rate at this time is 19.44 Mbps.

Now, since the management unit group signal AUG is formed, the interval overhead 191 must be added to generate the synchronous transmission module signal STM-1 as shown in FIG. 2.

7 is a detailed configuration diagram of the multiplexer section overhead processing unit 420, which includes a transmission path guard byte processing unit 421, a high speed data communication byte processing unit 422, a second pruning line byte processing unit 423, and an alarm between multiplexing mechanisms. And a display signal processor 425 and an inter-multiplexer overhead processor 424. Among the bytes in the multiplexer section overhead 193, K1, K2, D4-D12, S1, Z1, Z2, M1, and E2. Performs a byte insert function. Also, the second parity generator 430 is illustrated together.

First, the second parity generator 430 will be described.

The second parity generator 430 receives a corresponding control clock signal from the timing controller 482 and a 19.44 MHz clock (Tx19M) from the timing unit 481. A 24-bit bit interleaved parity (BIP-24) is applied to the 19.44 MHz parallel signal (MSOHO) output through the multiplexer section overhead processor 420 using the 19.44 MHz clock. The test is carried out, and the result is recorded as three second error check bytes B2: B2A, B2B, and B2C. This second error check byte (B2: B2A, B2B, B2C) is output in the next frame period.

In other words, the second error check byte B2 is an overhead allocated for checking payload data of the synchronous transmission module signal 190: STM-1 including the multiplexer interval overhead 193. 24 bit bit parity (BIP-24) for the remaining frames except for the player section overhead 192 from the frame byte A1 to the third data communication byte D3 before performing scrambling. Calculate your code.

At this time, since the second error check byte B2 is 3 bytes, the i th (i = 1, 2, ..., 24) bit among the 24 bits starts with the i th bit of the corresponding data and is applied to every 24 th bit. After an odd even check, we generate a 24-bit bit parity (BIP-24) code by filling itself with ones or zeros so that it is even.

On the other hand, the transmission path protection byte processing unit 421 of the multiplexer section overhead processing unit 420 receives the bytes (K1, K2) used for transmission path protection from the central processing unit 540 and this is the overhead processing unit between multiplexing mechanisms. Output each to (424). In general, the central processing unit 540 stores the values of the transmission path protecting bytes K1 and K2 in a predetermined register (not shown), and then transmits them.

Thereafter, the receiving end examines the transmission path protection bytes K1 and K2 of the synchronous transmission module signal STM-1, and when the same value is sequentially entered in three frames, the corresponding line is automatically used for the corresponding line. The transfer function will be performed.

The high speed data communication byte processing unit 422 receives data for serial data communication having a data rate of 576 Kbps by making a signal connection with a predetermined data communication channel unit (520: DCC unit), and then uses the corresponding control clock signal to perform fourth data communication. The output is divided into bytes D4 to twelfth data communication bytes D12.

For this operation, the high speed data communication byte processing unit 422 receives maintenance data corresponding to nine overhead bytes (fourth to twelveth data communication bytes) from the data communication channel unit 520. In this case, the data rate per byte is 64Kbps, so the maintenance data can be processed at a total rate of 576KHz.

The second pruning line byte processing unit 423 is allocated from the central processing unit 540 the first preliminary overhead byte Z1 (the first preliminary overhead byte is 3 bytes, of which the first byte is set to S1 byte). Second spare overhead byte (Z2) (the second spare overhead byte is allocated 3 bytes, the third of which is set to M1 bytes), and the first pruning line byte (E1). ) Is input, and each byte is outputted by using the corresponding control clock signals.

The multiplexing mechanism alarm indication signal processing unit 425 receives an alarm indication signal (AU-AIS: AU-Alarm Indication Signal) insertion command signal (TAUAIS) for a predetermined transmission management unit signal from the central processing unit 540, and thus serializes it. One of the parallel management unit group signal AUG and the management unit group signal AUG, which is output from the parallel conversion and multiplexing unit 410, is selected and output.

At this time, the data for the alarm display signal (AIS) is the payload in the down stream direction when an AIS or an Excessive Bit Error Ratio (E-BER) occurs. Have a logical value '1', and the fourth data communication byte D4 to the twelfth data communication byte D12, the first spare overhead byte Z1, the second spare overhead byte Z2, And the second pruning line byte E2 also have a logic value '1'.

The multiplexing mechanism overhead processing unit 424 includes a second error check byte (B2: B2A) related to a signal output from the multiplexing alarm display signal processor 425 and a previous frame output from the second parity generating unit 430. B2B, B2C), transmission path protection byte (K1, K2) output from transmission path protection byte processing unit 421, fourth data communication bytes (D4) to twelfth data communication output from high speed data communication byte processing unit 422; Byte D12, and three first preliminary overhead bytes Z1: Z1A, Z1B, Z1C output from the second chopped line byte processing unit 423, three second preliminary overhead bytes Z2: Z2A, Z2B , Z2C), and the second batting line byte E2.

After multiplexing the signals output from the multiplexing alarm display signal processor 425 and the respective overhead bytes to the corresponding positions using the corresponding control clock signals, an 8-bit data line is formed using a 19.44 MHz clock (Tx19M). Output in parallel via In addition, when the second transmission path protection byte K2, which is information on line switching, is applied, the second transmission path protection byte enable signal K2ENX is output.

8 is a configuration diagram of the player section overhead processing unit 440. The user channel byte processing unit 441, the low-speed data communication byte processing unit 442, the first pruning line byte processing unit 443, and the playback mechanism warning display signal processing unit ( 444) and the player section overhead processing unit 445, and among the signals MSOHO output from the multiplexer section overhead processing unit 420 and the bytes in the player section overhead 192, the frame bytes A1 and A2; First error check byte B1, first data communication byte D1 to third data communication byte D3, asynchronous transmission module signal identifier byte C1, user-defined byte F1, and first strike short byte This function outputs multiplexing (E1).

Also shown is a first parity generator 460 that generates a first error check byte B1.

First, the first parity generator 460 will be described.

The first parity generator 460 uses the corresponding clock signal among the 19.44 MHz (Tx19M) clock and the control clock signal with respect to the signal SCRO output in the state of being mixed by the mixer 450. Bit bit parity parity (BIP-8) checking of the bits is performed.

That is, the first error check byte B1 uses one byte as the bit shift even check byte for the error monitoring function of the player section, and the i-th (i = 1, 2, ..., 8) bit of the B1 byte. Performs an even check on only the i th bits of each byte. At this time, the 8 bit bit parity parity (BIP-8) is calculated after the mixed processing for the entire frame immediately before the synchronous transmission module signal (STM-1) to which the corresponding B1 byte belongs, and the current synchronous transmission module signal (STM-). It is to be inserted into the position of the first error check byte B1 before the mixing process of 1).

Meanwhile, the user channel byte processor 441 of the player section overhead processor 440 receives the user defined byte F1 and the synchronous transport module signal identification byte C1 from the central processing unit 540 and outputs the received byte.

Thereafter, the receiving end examines the user-defined byte F1 and the synchronous transport module signal identification byte C1 of the corresponding synchronous transmission module signal STM-1, and when the same value is successively inputted in three frames, By using this function, the function of the user byte is performed.

The low-speed data communication byte processing unit 442 receives the data for serial data communication from the data communication channel unit 520 at a data rate of 192 Kbps, and is a predetermined first audio data for the other short-circuit channel through the serial communication connection device 530. After receiving the grounding line byte E1, the serial communication data is divided into the first data communication byte D1 to the third data communication byte D3 and outputted, and the first grounding line byte E1 is the transmission grounding line byte for transmission. Output to (E1T).

At this time, the first tripping line byte E1 of the RS-422 level input through the serial communication connection device 530 is converted to the transistor-transistor logic (TTL) level and then of the transistor-transistor logic (TTL) level. Outputs the first short-circuit byte E1T.

On the other hand, since the data rate of each data byte is 64Kbps, it is possible to perform maintenance data communication at a rate of 192KHz. That is, each of the first data communication byte D1 to the third data communication byte D3 has a transmission rate of 64 Kbps.

The first ground fault byte processing unit 443 is a first ground fault byte E1 for transmission output from the low speed data communication byte processing unit 442, and a predetermined received first ground fault byte E (received from an external device). E1 byte of the synchronous transmission module signal being received), and selects one of them according to the mode selection signal for the first predetermined short-circuit byte from the central processing unit 540 and outputs the selected one. That is, upon reception, the received first pruning line byte E1 is passed as it is.

The replay mechanism alarm display signal processor 444 outputs the signal MSOHO outputted from the multiplexer zone overhead processor 420 according to a predetermined multiplexer zone alarm display signal insertion command signal TMSAIS sent from the central processing unit 540. ) And one of the predetermined alarm display signal (AIS) data is outputted.

At this time, the data for the alarm display signal (AIS) is a logical value of all the payloads in the down stream direction when a loss of signal (LOS) or a loss of frame (LOF) occurs. It has a '1', and also the first pruning line byte E1, the user-defined byte F1, and the first data communication byte D1 to the third data communication byte D3 are also logical values '1'. The data to have

The player section overhead processing unit 445 outputs an output signal MSOHO of the multiplexer section overhead processing unit 420, a first error check byte B1 output from the first parity generating unit 460, and a user channel byte. User-defined byte (F1) output from processor 441, synchronous transport module signal identification byte (C1), first data communication byte (D1) to third data communication bytes (output from low-speed data communication byte processor 452 ( D3), the first batting line byte E1 output from the first batting line byte processing section 443, and the signal output from the alarm display signal processing section 444 between the playback mechanisms and the corresponding control clock signal and the 19.44 MHz clock (Tx19M). Multiplex using In addition, "11110110" is inserted in place of the first frame byte A1 and "101000" is inserted in place of the second frame byte A2.

At this time, the signal RSOHO output from the player section overhead processing unit 445 is output at a transmission rate of 19.44 Mbps through a parallel 8-bit data line.

9 is a schematic diagram of a mixer, in which the mixer 450 receives a 19.44 MHz clock (Tx19M) and outputs the same from the player section overhead processor 440 through an 8-bit data line at a rate of 19.44 Mbps. After receiving the synchronous transmission module signal (STM-1: RSOHO) and performing a scrambling process, the synchronous transmission module signal (STM-1: RSOHO) is outputted at a transmission rate of 19.44Mbps through an 8-bit data line.

When such a mixing process is performed, the bit stream is randomized to reduce interference, to reduce static pattern dependent jitter, and to form a symbol state. By increasing the crossover, it is possible to obtain an effect to easily restore the clock.

At this time, the first row (9 bytes including the frame byte) of the section overhead 191 is not mixed.

As described above, in the synchronous multiplexing procedure, the synchronous transmission module signal 190: STM-1 may be generated by adding a predetermined section overhead 191 to the three management unit signals AU-3. In general, the present invention can be used in an apparatus for performing communication using a synchronous transmission scheme.

Claims (4)

A clock supply unit for supplying a predetermined main clock signal, a data communication channel unit for transmitting and receiving maintenance data, a serial communication connection device for serial connection with a predetermined external device, used in a predetermined communication device using a synchronous transmission method; And an apparatus for operating with a central processing unit used as a main control unit to multiplex a predetermined management unit signal (AU-3) to a synchronous transmission module signal (STM-1) during a synchronous multiplexing procedure. A transmission timing generator which receives the main clock signal from the clock supply unit and generates predetermined control clock signals; By using a corresponding clock signal among the main clock signal and the control clock signal, a predetermined number of management unit signals (AU-3) are serially received, converted into parallel signals, retimed, and multiplexed and output. Serial / parallel conversion and multiplexing unit; A multiplexer section overhead processor for inserting and outputting a predetermined multiplexer section overhead into a signal output from the serial / parallel conversion and multiplexer using the corresponding clock signal among the control clock signals; A player section overhead processor configured to insert a predetermined player section overhead into a signal output from the multiplexer section overhead processing section by using a corresponding clock signal among the control clock signals; A mixer for performing a predetermined scrambling process on the signal output from the player section overhead processor using the corresponding clock signal among the control clock signals; A second parity generating unit for outputting a 24-bit bit parity parity check byte (B2) for a predetermined portion of a signal output through the multiplexer section overhead processing unit using the corresponding clock signal among the control clock signals; And And a first parity generator configured to output an 8-bit bit parity parity check byte B1 for a player section overhead among signals output from the mixer using the corresponding clock signals among the control clock signals. Multiplexing device between the management unit signal and the synchronous transmission module signal in the synchronous transmission device. The control unit of claim 1, wherein the serial / parallel conversion and multiplexing unit parallelly inputs the predetermined number of management unit signals AU-3, respectively, by using a corresponding clock signal among the main clock signal and the control clock signal. A serial / parallel converter for outputting after converting; A retiming unit for retiming each parallel management unit signal (AU-3) output from the serial / parallel conversion unit by using a corresponding clock signal among the control clock signals; And And a management unit signal multiplexing unit configured to multiplex each parallel management unit signal (AU-3) outputted after being retimed from the retiming unit by using a corresponding clock signal among the control clock signals. A multiplexing device between a management unit signal and a synchronous transmission module signal in a synchronous transmission device. The apparatus of claim 1, wherein the multiplexer section overhead processing unit is output from the serial / parallel conversion and multiplexing unit according to a predetermined transmission management unit-alarm indication signal (AU-AIS) insertion command signal from the central processing unit. An alarm display signal processor between the multiplexing mechanisms for outputting one of the parallel management unit group signal AUG and predetermined alarm display signal data; A transmission path protection byte processing unit for dividing and outputting predetermined transmission path protection bytes (K1, K2) respectively inputted from the CPU using the corresponding clock signals among the control clock signals; High speed data communication which receives predetermined serial data from the data communication channel unit and divides the data into fourth data communication bytes D4 to 12th data communication bytes D12 by using corresponding clock signals among the control clock signals. A byte processing unit; A second pruning line byte processing unit which receives a predetermined spare byte and a second pruning line byte E2 and separately outputs each byte using a corresponding clock signal among the control clock signals; And A signal output from the alarm display signal processor between the multiplexing mechanisms, the 24-bit bit parity byte (B2), the transmission path protection byte (K1, K2), Including an overhead processing unit for multiplexing mechanisms for receiving and multiplexing 4 data communication bytes D4 to 12th data communication byte D12, a spare overhead byte, and a second mash line byte E2, and multiplexing them And a multiplexing device between the management unit signal and the synchronous transmission module signal in the synchronous transmission device. The apparatus of claim 1, wherein the player section overhead processing unit comprises: a user channel byte processing unit configured to receive a predetermined user defined byte (F1) and a synchronous transport module signal identification byte (C1) from the central processing unit; The predetermined serial data is received from the data communication channel unit using the corresponding clock signal among the control clock signals, and is divided into a first data communication byte D1 to a third data communication byte D3 and outputs the serial communication connection. A low-speed data communication byte processing unit which receives a predetermined first pruning line byte (E1) from the device and converts it to a transistor-transistor logic (TTL) level and outputs the converted low-speed data byte; According to the predetermined first summing line mode selection signal from the central processing unit, one of the first summing line byte E1 output from the low-speed data communication byte processing unit and the received first summing line byte E1 is selected. A first other short-circuit byte processing unit for outputting; Receives a predetermined multiplexer section warning display signal insertion command signal from the central processing unit, and accordingly selects and outputs one of a signal output from the multiplexer section overhead processing unit and a predetermined multiplexer section warning display signal (AIS) data. An alarm display signal processor between the playback mechanism; And A signal output from the alarm display signal processor between the playback mechanisms, the predetermined frame bytes A1 and A2, the user defined byte F1, and the synchronous transport module signal identification byte C1, using the corresponding clock signal among the control clock signals. And a player section overhead processing unit for multiplexing and outputting the first data communication byte (D1) to the third data communication byte (D3), and the first chopped line byte (E1). Multiplexing device between management unit signal and synchronous transmission module signal in the device.