CN114375499A - 垂直场效应晶体管和用于构造垂直场效应晶体管的方法 - Google Patents

垂直场效应晶体管和用于构造垂直场效应晶体管的方法 Download PDF

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CN114375499A
CN114375499A CN202080060851.9A CN202080060851A CN114375499A CN 114375499 A CN114375499 A CN 114375499A CN 202080060851 A CN202080060851 A CN 202080060851A CN 114375499 A CN114375499 A CN 114375499A
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trench structure
field effect
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effect transistor
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J·巴林豪斯
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Robert Bosch GmbH
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Abstract

提供一种垂直场效应晶体管(100)，该垂直场效应晶体管具有：具有第一导电类型的漂移区(112)、在所述漂移区(112)上面或者在所述漂移区(112)上方的沟槽结构(102)、屏蔽结构(118，119)和源/漏电极(151，152)。沟槽结构(102)具有至少一个侧壁，在所述侧壁上构造场效应晶体管(FET)沟道区，其中，所述FET沟道区具有用于在III‑V族异质结构(117，121)的界面上构造二维电子气的III‑V族异质结构(117，121)。屏蔽结构横向地布置在所述沟槽结构(102)的至少一个侧壁旁边，并且垂直地延伸到所述漂移区(112)中，或者垂直地在所述漂移区(112)的方向上比所述沟槽结构(102)更远地延伸。屏蔽结构(118，119)具有不同于第一导电类型的第二导电类型。源/漏电极(151)与沟槽结构(102)的III‑V族异质结构(117，121)和屏蔽结构(118，119)导电连接。

Description

垂直场效应晶体管和用于构造垂直场效应晶体管的方法
技术领域
本发明涉及一种垂直场效应晶体管和一种用于构造其的方法。
背景技术
与基于硅或碳化硅的同类构件相比，基于氮化镓(GaN)的晶体管提供了实现在具有更高的击穿电压的同时具有更低的导通电阻的构件的可能性。相关技术的、在图1中示出的这种晶体管10的可能的结构方式是所谓的垂直HEMT(具有高电子迁移率的晶体管，英文：high-electron-mobility transistor)，其中，沟道通过在氮化铝镓(AlGaN)/氮化镓(GaN)-异质结构的界面上的二维电子气(2DEG)构造。该异质结构例如通过生长构造在V形的沟槽中。晶体管10具有导电的GaN衬底11，在所述GaN衬底上施加弱n型导电的GaN漂移区12。p型导电的GaN区域15位于漂移区12上方并且其上有绝缘的GaN或者AlGaN区域16。两个区域15、16由V形的沟槽穿透，未掺杂的或者本征的GaN区域17以及AlGaN区域21在该V形的沟槽上延伸。在两个区域17、21的界面上的区域17中产生2DEG。在V形的沟槽中引入p型导电的GaN区域31，以便确保构件的自锁(英文：normally off)运行。栅电极32接触p型GaN区域31。源电极51不仅接触2DEG而且接触p区域15。绝缘件41将源电极51和栅电极32分开。漏电极52位于衬底11的背侧上。在没有施加栅极电压的情况下，晶体管10是自锁的，因为在区域31下方的2DEG是耗尽的。通过将正电压施加到栅电极32上，整个2DEG被电子填充，并且，电子从源电极51经由沟槽的侧壁流动到沟槽的底部中并且从那里流动到漂移区12中、通过衬底11流动到漏电极52中。
在截止运行中，晶体管10在沟槽的底部上具有高电场。由此，存在提早电击穿晶体管10的或者说施加到漏电极52上的电压穿通到栅极31、32上的风险。
发明内容
本发明的任务是，提供一种垂直场效应晶体管和一种用于其制造的方法，该垂直场效应晶体管/该方法解决上述问题中的一个或者多个。
根据本发明的一个方面，该任务通过垂直场效应晶体管来解决。该垂直场效应晶体管具有：具有第一导电类型的漂移区；在所述漂移区上面或者在所述漂移区上方的沟槽结构，其中，所述沟槽结构具有至少一个侧壁，在所述侧壁上构造场效应晶体管(FET)沟道区，其中，所述FET沟道区具有用于在III-V族异质结构的界面上构造二维电子气的III-V族异质结构；以及屏蔽结构，所述屏蔽结构横向地布置在所述沟槽结构的至少一个侧壁旁边，并且垂直地延伸到所述漂移区中，或者垂直地在漂移区的方向上比所述沟槽结构更远地延伸，其中，所述屏蔽结构具有不同于第一导电类型的第二导电类型；以及源/漏电极，所述源/漏电极与所述沟槽结构的III-V族异质结构和所述屏蔽结构导电连接。
屏蔽结构实现了沟槽结构的底部相对于电场的屏蔽。这实现了，充分利用晶体管的电势。这例如阻止了提早电击穿晶体管或者说施加到漏电极上的电压穿通到栅极上。
根据本发明的另一个方面，该任务通过用于构造垂直场效应晶体管的方法来解决。该方法具有：构造具有第一导电类型的漂移区；在所述漂移区上面或者在所述漂移区上方构造沟槽结构，其中，所述沟槽结构具有至少一个侧壁，在所述侧壁上构造场效应晶体管(FET)沟道区，其中，所述FET沟道区具有用于在III-V族异质结构的界面上构造二维电子气的III-V族异质结构；构造屏蔽结构，所述屏蔽结构横向地布置在所述沟槽结构的至少一个侧壁旁边，并且垂直地延伸到所述漂移区中，或者垂直地在所述漂移区的方向上比所述沟槽结构更远地延伸，其中，所述屏蔽结构具有不同于第一导电类型的第二导电类型；以及，构造源/漏电极，所述源/漏电极与所述沟槽结构的所述III-V族异质结构和所述屏蔽结构导电连接。
附图说明
在从属权利要求和说明书中解释所述方面的扩展方案。在附图中示出并且在下文中更详细地阐述本发明的实施方式。附图示出：
图1示出相关技术的晶体管结构的剖面图；
图2A、2B、2C和2D示出根据不同实施方式的垂直场效应晶体管的视图；
图3A和3B示出根据不同实施方式的垂直场效应晶体管的视图；
图4A、4B和4C示出根据不同实施方式的垂直场效应晶体管的视图；
图5A、5B和5C示出根据不同实施方式的垂直场效应晶体管的视图；以及
图6A和6B根据不同实施方式的垂直场效应晶体管的视图；以及
图7示出根据不同实施方式的用于构造垂直场效应晶体管的方法的流程图。
具体实施方式
在以下详细的描述中，参考附上的附图，所述附图形成本说明书的一部分，并且在所述附图中为了说明而示出具体的实施例，在所述实施例中能够实施本发明。可以理解，能够使用其他的实施例并且进行结构上或者逻辑上的改变，而不偏离本发明的保护范围。可以理解，在本文中描述的不同实施例的特征能够彼此组合，除非另有具体说明。因此，以下详细的描述不应在限制的意义上被理解，并且本发明的保护范围由所附的权利要求限定。在附图中，相同或者相似的元件设有相同的附图标记，只要这是符合目的的。
图2A至图6B示出根据不同实施方式的垂直场效应晶体管100的视图。在不同实施方式中，垂直场效应晶体管100都具有：漂移区112；在漂移区112上面或者上方的沟槽结构102，屏蔽结构118、119，第一源/漏电极(例如，源电极)151，第二源/漏电极(例如，漏电极)152以及栅极沟槽(该栅极沟槽在绘图平面中延伸并且也被称为沟槽结构，如在图4C和图5A中以俯视图示出的那样)。下面，示例性地假设：第一源/漏电极151是源电极，并且，第二源/漏电极152是漏电极。漂移区112具有第一导电类型，并且，屏蔽结构118、119具有不同于第一导电类型的第二导电类型。沟槽结构102具有至少一个侧壁，在所述侧壁上构造场效应晶体管FET沟道区，其中，FET沟道区具有用于在III-V族异质结构的界面上构造二维电子气(2DEG)的III-V族异质结构117、121。屏蔽结构118、119横向地布置在沟槽结构102的至少一个侧壁旁边，并且垂直地延伸到漂移区112中，或者垂直地在漂移区112的方向上比沟槽结构102更远地延伸。源电极151与沟槽结构102的III-V族异质结构和屏蔽结构118、119导电连接。例如，源电极151由金属或者金属合金形成，并且，屏蔽结构118、119由掺杂的半导体材料形成。
屏蔽结构118、119的区域119具有比漂移区112更高的掺杂物浓度。借助将例如以高掺杂的p型GaN区域的形式的屏蔽区域119引入到漂移区112中实现了，屏蔽沟槽结构102的底部101。在运行中，在屏蔽结构118、119的区域119和漂移区112之间能够构造空间电荷区。由此，能够减小电流能够在其中流动的区域，从而能够增加电阻。通过引入屏蔽结构118、119，与没有屏蔽结构的变型(图1)相比，增加了场效应晶体管100的总电阻。在截止情况下在漏电极152上施加的电势导致电场，该电场在屏蔽结构118、119的正下方具有其最大值，而不是如在没有屏蔽结构118、119的情况下(参见图1)那样在沟槽结构102的底部101中具有其最大值。这例如阻止了提早电击穿场效应晶体管100或者说施加到漏电极152上的电压穿通到栅电极132上。
场效应晶体管100能够进一步具有导电的GaN衬底111，在该GaN衬底上施加有弱n型导电的GaN漂移区112。在漂移区112上能够构造p型导电的GaN区域115和在其上方的绝缘的GaN或者AlGaN区域116。两个区域115、116均由V形的沟槽穿透，未掺杂的或者本征的GaN区域117和AlGaN区域121能够在该V形的沟槽上延伸。在两个区域117、121的界面上的区域117中能够产生2DEG。在V形的沟槽中可以引入p型导电的GaN区域131，以便确保场效应晶体管100的自锁(英文：normally off)运行。栅电极132能够接触p型GaN区域131。源电极151不仅能够接触2DEG而且能够接触p型区域115。绝缘件141能够将源电极151和栅电极132彼此电绝缘。漏电极152能够位于衬底111的背侧上。在没有施加栅极电压的情况下，场效应晶体管100能够是自锁的，因为在区域131下方的2DEG能够是耗尽的。通过将正电压施加到栅电极132上，整个2DEG能够被电子填充，并且，电子能够从源电极151经由沟槽结构102的侧壁流动到沟槽结构102的底部101中并且从那里进入到漂移区112中、通过衬底111进入到漏电极152中。
在另外的实施方式中，屏蔽结构118、119也能够构造在p型导电的区域115的正下方，如在图2B中示出的那样。屏蔽结构118、119能够具有另外的高掺杂的p型导电的区域118，所述高掺杂的p型导电的区域将屏蔽结构118、119的区域119与源电极151连接。这实现了更好的电连接。
此外，屏蔽结构118、119能够如此设立，使得它们在横向上具有和源电极151相同的延伸(如在图2C中示出的那样)，或者能够替代地如此设立，使得它们与源电极151的延伸相比具有在横向上更小的延伸，如在图2D中示出的那样。屏蔽结构118、119的横向延伸的变化提供了如下可能性：在屏蔽(能够随着横向延伸的变大而改善)方面或者在通态电阻(能够随着横向延伸的变小而变小)方面优化构件。
在不同实施方式中，能够构造至少一个高掺杂的n型GaN区域122，该高掺杂的n型GaN区域将源电极151与2DEG连接，如在图2D中示出的那样。这能够实现改进2DEG到源电极151的连接。
在不同实施方式中，p型GaN屏蔽结构113能够构造在沟槽结构102的p型导电的区域115下方在漂移区112上、上方和/或中。例如，在不同实施方式中，在漂移区112和沟槽结构102的底部101之间能够构造GaN区域113，如在图3A中示出的那样。GaN区域113能够例如构造在屏蔽结构118、119的至少一部分旁边，例如在共同的层平面中。GaN区域113能够例如构造得比漂移区112更高n型导电。这引起空间电荷区的延伸的减小，从而能够减少电阻的增加。
在不同实施方式中，在沟槽结构102的每侧上都构造有屏蔽结构118、119，如在图2A至图3A中示出的那样。在这种情况下，屏蔽结构113能够构造在两个屏蔽区域119之间和/或两个屏蔽区域118之间。在不同实施方式中，能够构造另外的屏蔽结构，以便进一步提高屏蔽效果。例如，在沟槽结构102的底部101的(正)下方能够设置p型导电的区域120作为屏蔽结构，如在图3B中示出的那样。这实现了相对于电场最大程度地屏蔽沟槽结构102的底部101。
在不同实施方式中，通过以下方式实现了沟槽结构102的底部101的有效屏蔽：屏蔽结构118、119(例如屏蔽结构的屏蔽区域119)延伸到沟槽结构的底部下方，如在图4A中示出的那样(左屏蔽区域119)。在另一个实施方式中，这也能够利用屏蔽结构118、119来实现，所述屏蔽结构邻接沟槽结构102的底部101、例如接触该底部。在这种情况下，在图4B中构造在沟槽结构的左侧壁上的FET沟道不再导电，因为不存在从左源电极151到漏电极152的连贯的电流路径。在不同实施方式中，屏蔽区域119能够交替地布置在沟槽结构的右侧和沟槽结构的左侧上，如在图4C中的俯视图中示出的那样。这实现了，在图4B中位于左侧壁上的电子在该深度上流动到相邻的单元中，并且随后在该单元中在垂直方向上流出至漏电极152。由此，整个FET沟道能够对电流流动做出贡献。
在另一个实施方式中，屏蔽区域119的横向结构能够与位于其上的单元的结构解耦，如在图5A、5B和5C中示出的那样。例如，屏蔽区域119能够实施为连续的条形结构，该条形结构在相对于如下方向垂直的方向上延伸：栅极沟槽在所述方向上延伸，如在图5A和图5B中示出的那样。如下单元不会或者基本上不再对电流流动做出贡献：在所述单元中，屏蔽区域119构造为沟槽结构的底部下方的连贯的条形结构(图5B)。条形的屏蔽区域119也能够屏蔽如下单元：在所述单元中，没有屏蔽区域119构造在沟槽结构的底部下方(图5C)。这实现了，沟槽结构102和屏蔽区域119的光刻例如不必必要地彼此定向。由此，能够简化场效应晶体管100的制造。
换句话说：在不同实施方式中，能够设置附加的沟槽结构102，该附加的沟槽结构在该平面中相对于沟槽结构102偏移，从而源电极151布置在沟槽结构102和附加的沟槽结构102之间。在此，屏蔽结构118、119能够具有附加的布置在漂移区112中的区域119，该区域横向地至少延伸到附加的沟槽结构102的底部的一部分的下方。屏蔽结构118、119的布置在漂移区112中的区域119和屏蔽结构118、119的附加的布置在漂移区112中的区域119能够在沟槽方向上彼此偏移地布置。沟槽方向例如是沟槽结构102的细长的(例如最长的或者线形的)延伸方向。
屏蔽结构119的横向的延伸方向能够选择为相对于栅极沟槽的延伸方向成任意角度。除了栅极沟槽以及屏蔽结构的线形的实施以外，两者还能够构造在(例如六边形的)网格图案中，如在图6A和图6B中示出的那样。在图6A中示出具有六边形的栅极沟槽和条形的屏蔽区域119的实施方式。在图6B中示出一种实施方式，在该实施方式中，栅极沟槽具有六边形的图案。屏蔽区域119能够例如构造在六边形网格的每第二个基点上。在另外的实施方式中，能够设置用于栅极沟槽和/或屏蔽结构的其他网格图案，例如人字形或者立体网格。
在不同实施方式中，沟槽结构102能够具有带有FET沟道的至少一个侧壁，该侧壁与衬底111围成角度。例如，沟槽结构102的侧壁能够与衬底111的上侧围成角度，其中，该角度能够大于0°并且小于90°。III-V族异质结构117、121能够具有AlGaN层121和邻接AlGaN层121的GaN层117。因而，FET沟道能够具有氮化铝镓(AlGaN)区域和氮化镓(GaN)区域。
漂移区112也能够被称为垂直场效应晶体管100的漂移区112。漂移区112能够具有例如n型导电的GaN区域112，例如n型掺杂的GaN。漂移区112能够构造在半导体衬底111、例如GaN衬底111上面或者上方。屏蔽结构118、119能够具有例如至少一个p型导电的GaN区域118、119，该p型导电的GaN区域的掺杂物浓度能够高于漂移区112的掺杂物浓度。例如，漂移区112能够具有n型掺杂的GaN，并且，屏蔽结构118、119能够具有p++掺杂的GaN。屏蔽结构118、119能够具有p++GaN区域并且设立用于，横向地包围沟槽结构102的底部101。垂直场效应晶体管100能够具有横向地包围沟槽结构102的底部101的p型导电的GaN区域115。屏蔽结构118、119能够至少部分地在p型导电的GaN区域115下方延伸。屏蔽结构118、119能够穿过p型导电的GaN区域115延伸到n型导电的GaN区域112中。
在不同实施方式中，在漂移区112中能够至少构造在沟槽结构102下方具有第一导电类型的区域113。替代地或者附加地，区域113能够具有比漂移区112更高的掺杂物浓度。至少构造在沟槽结构102下方的区域113能够邻接屏蔽结构118、119，例如与所述屏蔽结构导电连接。在不同实施方式中，能够设置附加的屏蔽结构120。附加的屏蔽结构120能够布置在至少构造在沟槽结构102下方的区域113中。附加的屏蔽结构120能够具有第二导电类型。附加的屏蔽结构120能够至少部分地布置在沟槽结构102下方。在不同实施方式中，附加的屏蔽结构120能够通过至少构造在沟槽结构102下方的区域113而与屏蔽结构118、119分开。
图7示出根据不同实施方式的用于构造垂直场效应晶体管100的方法700的流程图。方法700具有：构造710具有第一导电类型的漂移区；在漂移区上面或者上方构造720沟槽结构，其中，沟槽结构具有至少一个侧壁，在所述侧壁上构造场效应晶体管FET沟道区，其中，FET沟道区具有用于在III-V族异质结构的界面上构造二维电子气的III-V族异质结构；以及，构造730屏蔽结构，所述屏蔽结构横向地布置在沟槽结构的至少一个侧壁旁边，并且垂直地延伸到漂移区中，或者垂直地在漂移区的方向上比沟槽结构更远地延伸，其中，屏蔽结构具有不同于所述第一导电类型的第二导电类型；以及，构造源/漏电极，所述源/漏电极与沟槽结构的III-V族异质结构和屏蔽结构导电连接。
沟槽结构能够构造在半导体衬底上面或者上方。沟槽结构能够构造有底部。漂移区构造在沟槽结构的底部和半导体衬底之间。在沟槽结构和漂移区之间能够构造屏蔽结构。屏蔽结构能够与沟槽结构间接地、例如通过源电极导电连接。显然，屏蔽结构能够在半导体衬底的方向上延伸超过沟槽结构的底部。在不同实施方式中，在沟槽结构的底部和半导体衬底之间的区域能够保持没有屏蔽结构。
仅示例性地选择所描述的和在附图中所示出的实施方式。不同的实施方式能够完全地或者关于各个特征地彼此组合。一个实施方式也能够由另一个实施方式的特征来补充。此外，所描述的方法步骤能够重复地以及以不同于所述的顺序来实施。尤其地，本发明不限于所给出的方法。

Claims (11)

1.一种垂直场效应晶体管(100)，所述垂直场效应晶体管具有：
具有第一导电类型的漂移区(112)；
在所述漂移区(112)上面或者在所述漂移区(112)上方的沟槽结构(102)，其中，所述沟槽结构(102)具有至少一个侧壁，在所述侧壁上构造场效应晶体管(FET)沟道区，其中，所述FET沟道区具有III-V族异质结构(117，121)，所述III-V族异质结构用于在所述III-V族异质结构(117，121)的界面上构造二维电子气；以及
屏蔽结构(118，119)，所述屏蔽结构横向地布置在所述沟槽结构(102)的至少一个侧壁旁边，并且垂直地延伸到所述漂移区(112)中，或者垂直地在所述漂移区(112)的方向上比所述沟槽结构(102)更远地延伸，其中，所述屏蔽结构(118，119)具有不同于所述第一导电类型的第二导电类型；以及
源/漏电极(151)，所述源/漏电极与所述沟槽结构(102)的所述III-V族异质结构(117，121)和所述屏蔽结构(118，119)导电连接。
2.根据权利要求1所述的垂直场效应晶体管(100)，
其中，所述III-V族异质结构(117，121)具有AlGaN层(121)和邻接所述AlGaN层(121)的GaN层(117)。
3.根据权利要求2所述的垂直场效应晶体管(100)，
其中，所述漂移区(112)是n型导电的，并且其中，所述屏蔽结构(118，119)具有至少一个p型导电的GaN区域(118)，所述p型导电的GaN区域的掺杂物浓度高于所述漂移区(112)的掺杂物浓度。
4.根据前述权利要求中任一项所述的垂直场效应晶体管(100)，其中，所述屏蔽结构(118，119)具有布置在所述漂移区(112)中的区域(119)，所述区域横向地在所述沟槽结构(102)的方向上延伸。
5.根据权利要求4所述的垂直场效应晶体管(100)，其中，所述屏蔽结构(118，119)的布置在所述漂移区(112)中的区域(119)至少延伸到所述沟槽结构(102)的底部(101)的一部分的下方。
6.根据权利要求4或5所述的垂直场效应晶体管(100)，其中，所述屏蔽结构(118，119)还具有：
在垂直方向上延伸的、在所述源/漏电极(151)和所述屏蔽结构(118，119)的在横向方向上延伸的区域(119)之间的区域(118)。
7.根据前述权利要求中任一项所述的垂直场效应晶体管(100)，所述垂直场效应晶体管还具有：
在所述漂移区(112)中至少构造在所述沟槽结构(102)下方的区域(113)，所述区域具有所述第一导电类型并且具有比所述漂移区(112)更高的掺杂物浓度；
其中，所述至少构造在所述沟槽结构(102)下方的区域(113)与所述屏蔽结构(118，119)邻接。
8.根据权利要求7所述的垂直场效应晶体管(100)，所述垂直场效应晶体管还具有：
附加的屏蔽结构(120)，所述附加的屏蔽结构布置在所述至少构造在所述沟槽结构(102)下方的区域(113)中并且具有所述第二导电类型，其中，所述附加的屏蔽结构(120)至少部分地布置在所述沟槽结构(102)下方并且通过所述至少构造在所述沟槽结构(102)下方的区域(113)与所述屏蔽结构(118，119)分开。
9.根据权利要求5所述的垂直场效应晶体管(100)，所述垂直场效应晶体管还具有：
附加的沟槽结构(102)，所述附加的沟槽结构在平面中相对于所述沟槽结构(102)偏移，从而所述源/漏电极(151)布置在所述沟槽结构(102)和所述附加的沟槽结构(102)之间，其中，所述屏蔽结构(118，119)具有附加的布置在所述漂移区(112)中的区域(119)，所述区域横向地至少延伸到所述附加的沟槽结构(102)的底部的一部分的下方。
10.根据权利要求9所述的垂直场效应晶体管(100)，
其中，所述屏蔽结构(118，119)的布置在所述漂移区(112)中的区域(119)和所述屏蔽结构(118，119)的附加的布置在所述漂移区(112)中的区域(120)在沟槽方向上彼此偏移地布置。
11.一种用于构造垂直场效应晶体管(100)的方法，所述方法具有：
构造(710)具有第一导电类型的漂移区(112)；
在所述漂移区(112)上面或者在所述漂移区(112)上方构造(720)沟槽结构(102)，其中，所述沟槽结构(102)具有至少一个侧壁，在所述侧壁上构造场效应晶体管(FET)沟道区，其中，所述FET沟道区具有III-V族异质结构(117，121)，所述III-V族异质结构用于在所述III-V族异质结构(117，121)的界面上构造二维电子气；
构造(730)屏蔽结构(118，119)，所述屏蔽结构横向地布置在所述沟槽结构(102)的至少一个侧壁旁边，并且垂直地延伸到所述漂移区(112)中，或者垂直地在所述漂移区(112)的方向上比所述沟槽结构(102)更远地延伸，其中，所述屏蔽结构(118，119)具有不同于所述第一导电类型的第二导电类型；以及
构造源/漏电极(151)，所述源/漏电极与所述沟槽结构(102)的所述III-V族异质结构(117，121)和所述屏蔽结构(118，119)导电连接。
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