CN114335273B - LED epitaxial wafer, preparation method thereof and LED chip - Google Patents
LED epitaxial wafer, preparation method thereof and LED chip Download PDFInfo
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- CN114335273B CN114335273B CN202111655190.7A CN202111655190A CN114335273B CN 114335273 B CN114335273 B CN 114335273B CN 202111655190 A CN202111655190 A CN 202111655190A CN 114335273 B CN114335273 B CN 114335273B
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Abstract
The invention relates to the technical field of light-emitting diode epitaxial wafers, in particular to an LED epitaxial wafer, a preparation method thereof and an LED chip. The LED epitaxial wafer comprises an N-type semiconductor layer, an active layer, a depletion region layer and a P-type semiconductor layer which are sequentially stacked on the surface of a substrate; the depletion region layer comprises a first superlattice layer and a second superlattice layer which are sequentially stacked; the first superlattice layer comprises an AlN layer and a P-type AlGaN layer which are grown periodically and alternately; the second superlattice layer comprises a P-type GaN layer and a P-type InN layer which are periodically and alternately grown. The potential energy of the first superlattice layer is high, electrons can be blocked, and electron overflow is reduced; the second superlattice layer provides holes so as to reduce energy loss of the holes provided by the P-type semiconductor layer in the depletion region, thereby improving the quantity of holes in the active layer and further improving the radiation recombination efficiency of electrons and holes.
Description
Technical Field
The invention relates to the technical field of light-emitting diode epitaxial wafers, in particular to an LED epitaxial wafer, a preparation method thereof and an LED chip.
Background
Gallium nitride (GaN) -based Light Emitting Diodes (LEDs) are widely used in various fields such as display and illumination due to their long life, low power consumption, and no pollution. The GaN is a wide-bandgap compound semiconductor material, has the characteristics of blue light emission, high temperature, high frequency, high voltage, high power, acid resistance, alkali resistance, corrosion resistance and the like, is an important semiconductor material after germanium, silicon and gallium arsenide, plays an important role in the technical field of blue light and ultraviolet electronics, and is also an ideal material for manufacturing high-temperature and high-power semiconductor devices.
The LED epitaxial wafer refers to a specific single crystal thin film grown on a substrate sheet heated to an appropriate temperature. The epitaxial wafer is located in the upstream link of the LED industry chain, and is the link with the highest technical content in the semiconductor lighting industry and the greatest influence on the quality and cost control of the final product.
Although GaN-based LEDs have been industrialized, high brightness epitaxial wafers are critical to LEDs. The epitaxial wafer capable of improving the brightness of the GaN-based LED has important significance.
In view of this, the present invention has been made.
Disclosure of Invention
The first object of the invention is to provide an LED epitaxial wafer, which can block electrons and reduce electron overflow by arranging a depletion region layer between an active layer and a P-type semiconductor layer, wherein the potential energy of a first superlattice layer of the depletion region layer is high; the second superlattice layer of the depletion region layer provides holes so as to reduce energy loss of the holes provided by the P-type semiconductor layer in the depletion region, thereby improving the quantity of holes in the active layer and further improving the radiation recombination efficiency of electrons and holes. And the potential in the depletion region layer is from high to low, so that holes in the P-type semiconductor layer can more easily enter the active layer, the quantity of the holes is further improved, the radiation recombination efficiency of electrons and holes is improved, and finally the internal quantum efficiency of the light-emitting diode is improved.
The second object of the present invention is to provide a method for preparing the LED epitaxial wafer, which can improve the internal quantum efficiency of the light emitting diode.
A third object of the present invention is to provide an LED chip having high internal quantum efficiency and good light emission performance.
In order to achieve the above object of the present invention, the following technical solutions are specifically adopted:
the invention provides an LED epitaxial wafer, which comprises an N-type semiconductor layer, an active layer, a depletion region layer and a P-type semiconductor layer which are sequentially stacked on the surface of a substrate;
the depletion region layer comprises a first superlattice layer and a second superlattice layer which are sequentially stacked;
the first superlattice layer comprises an AlN layer and a P-type AlGaN layer which are grown periodically and alternately;
the second superlattice layer comprises a P-type GaN layer and a P-type InN layer which are periodically and alternately grown.
Preferably, a P-type GaN transition layer is further arranged between the first superlattice layer and the second superlattice layer;
preferably, the thickness of the P-type GaN transition layer is 1-2 nm.
Preferably, the period of the alternate growth of the first superlattice layer is 2-5 periods;
preferably, the thickness of the first superlattice layer is 3-6 nm.
Preferably, the period of the alternate growth of the second superlattice layer is 2-5 periods;
preferably, the thickness of the second superlattice layer is 10-15 nm.
Preferably, the doping concentration of the P-type impurity used in the first superlattice layer is 5×10 17 ～5×10 18 atom/cm 3 ；
And/or;
the doping concentration of the P-type impurity used in the second superlattice layer is 5×10 18 ～2×10 20 atom/cm 3 。
Preferably, the active layer includes InGaN well layers and GaN barrier layers grown in a periodically alternating stack; the depletion region layer is the last barrier layer and is arranged on the surface of the InGaN well layer or the GaN barrier layer.
Preferably, the thickness of the depletion region layer is 5 to 40nm.
The invention also provides a preparation method of the LED epitaxial wafer, which comprises the following steps:
an MOCVD method is adopted, an N-type semiconductor layer, an active layer, a depletion region layer and a P-type semiconductor layer are sequentially grown on the surface of a substrate, and the LED epitaxial wafer is obtained;
the depletion region layer comprises a first superlattice layer and a second superlattice layer which are sequentially grown on the surface of the active layer;
the first superlattice layer comprises an AlN layer and a P-type AlGaN layer which are grown periodically and alternately;
the second superlattice layer comprises a P-type GaN layer and a P-type InN layer which are periodically and alternately grown.
Preferably, the P-type GaN transition layer is further included between the first superlattice layer and the second superlattice layer;
preferably, the growth temperature of the P-type GaN transition layer is 800-850 ℃, and the growth pressure is 200-300 mbar.
Preferably, the growth temperature of the first superlattice layer is 800-850 ℃;
and/or the growth temperature of the second superlattice layer is 850-900 ℃;
preferably, the growth pressure of the first superlattice layer and/or the second superlattice layer is 200-300 mbar.
The invention also provides an LED chip, which comprises the LED epitaxial wafer.
Compared with the prior art, the invention has the beneficial effects that:
according to the LED epitaxial wafer, the depletion region layer is arranged between the active layer and the P-type semiconductor layer, and comprises a first superlattice layer and a second superlattice layer which are sequentially stacked; the first superlattice layer comprises an AlN layer and a P-type AlGaN layer which are grown periodically and alternately, and has high potential energy, so that electrons can be blocked, and electron overflow is reduced. The second superlattice layer comprises a P-type GaN layer and a P-type InN layer which are periodically and alternately grown, the second superlattice layer can provide holes, the energy loss of the holes provided by the P-type semiconductor layer in a depletion region is reduced, and the number of the holes in the active layer is increased, so that the radiation recombination efficiency of electrons and holes is improved. And the electric potential of the first superlattice layer and the second superlattice layer is from high to low, so that holes in the P-type semiconductor layer can enter the active layer more easily, the number of holes is further increased, the radiation recombination efficiency of electrons and holes is improved, and finally the internal quantum efficiency of the light-emitting diode is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an LED epitaxial wafer provided by the present invention;
fig. 2 is another schematic structural diagram of the LED epitaxial wafer provided by the present invention;
FIG. 3 is a schematic diagram of an N-type semiconductor layer according to the present invention;
FIG. 4 is a schematic diagram of a structure of a P-type semiconductor layer according to the present invention;
FIG. 5 is a schematic diagram of another N-type semiconductor layer according to the present invention;
FIG. 6 is a schematic diagram of another P-type semiconductor layer according to the present invention;
fig. 7 is a schematic structural diagram of an LED epitaxial wafer according to embodiment 2 of the present invention;
fig. 8 is a schematic structural diagram of an LED epitaxial wafer according to embodiment 3 of the present invention.
Reference numerals:
1-a substrate; a 2-N type semiconductor layer; 201-a low temperature GaN buffer layer;
202-an undoped GaN layer; 203-an N-type 3-active layer doped with N-type impurities;
a GaN layer;
4-depletion region layer; 41-a first superlattice layer; 42-a second superlattice layer;
a 43-P type GaN transition layer; a 5-P type semiconductor layer; 501-a low-temperature P-type InAlGaN layer;
502-AlGaN electron blocking layer; 503-P type doped with P type impurity
And a GaN layer.
Detailed Description
The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and detailed description, but it will be understood by those skilled in the art that the examples described below are some, but not all, examples of the present invention, and are intended to be illustrative of the present invention only and should not be construed as limiting the scope of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. The specific conditions are not noted in the examples and are carried out according to conventional conditions or conditions recommended by the manufacturer. The reagents or apparatus used were conventional products commercially available without the manufacturer's attention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of an LED epitaxial wafer provided by the present invention; fig. 2 is another schematic structural diagram of the LED epitaxial wafer provided by the present invention; FIG. 3 is a schematic diagram of an N-type semiconductor layer according to the present invention; FIG. 4 is a schematic diagram of a structure of a P-type semiconductor layer according to the present invention; FIG. 5 is a schematic diagram of another N-type semiconductor layer according to the present invention; FIG. 6 is a schematic diagram of another P-type semiconductor layer according to the present invention; fig. 7 is a schematic structural diagram of an LED epitaxial wafer according to embodiment 2 of the present invention; fig. 8 is a schematic structural diagram of an LED epitaxial wafer according to embodiment 3 of the present invention.
As shown in fig. 1, the LED epitaxial wafer provided by the present invention includes an N-type semiconductor layer 2, an active layer 3, a depletion region layer 4, and a P-type semiconductor layer 5, which are sequentially stacked on the surface of a substrate 1.
Wherein the depletion region layer 4 includes a first superlattice layer 41 and a second superlattice layer 42 which are sequentially stacked.
The first superlattice layer 41 includes an AlN layer and a P-type AlGaN layer that are alternately grown periodically.
The second superlattice layer 42 includes a periodically alternating grown P-type GaN layer and P-type InN layer.
The present invention provides a depletion region layer 4 between an active layer 3 and a P-type semiconductor layer 5, the depletion region layer 4 including a first superlattice layer 41 and a second superlattice layer 42 stacked in this order. Wherein, the potential energy of the first superlattice layer 41 is high, which can play roles of blocking electrons and reducing electron overflow; the second superlattice layer 42 may provide holes, and reduce energy loss of the holes provided by the P-type semiconductor layer 5 in the depletion region, thereby increasing the number of holes in the active layer 3, and further increasing the radiative recombination efficiency of electrons and holes.
And, the potential of the first superlattice layer 41 in the depletion region layer 4 is higher than that of the second superlattice layer 42, so that holes in the P-type semiconductor layer 5 can enter the active layer 3 more easily, the number of holes is further increased, the radiation recombination efficiency of electrons and holes is improved, and finally the internal quantum efficiency of the light emitting diode is improved.
As shown in fig. 2, in some specific embodiments of the present invention, a P-type GaN transition layer 43 is further disposed between the first superlattice layer 41 and the second superlattice layer 42.
Since the energy bands of the AlN layer and the P-type AlGaN layer are larger than those of the P-type GaN layer and the P-type InN layer, the P-type GaN transition layer 43 is used as a transition layer from high potential energy to low potential energy, and since the energy bands of the first superlattice layer 41 and the second superlattice layer 42 are greatly different, the effect of reducing the energy band tilt can be achieved.
Preferably, the thickness of the P-type GaN transition layer 43 is 1-2 nm, including but not limited to any one of 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm, or a range between any two.
The thickness of the P-type GaN transition layer 43 is set within the above range, and first, the P-layer holes are facilitated to be more unobstructed from low potential energy to high potential energy. Second, the P-type GaN transition layer 43 prevents a part of electrons from crossing the first superlattice layer 41 into the P-type semiconductor layer 5 or the depletion region layer 4 to generate non-radiative recombination with holes. The effect of preventing part of electrons from crossing the first superlattice layer 41 and entering the P-type semiconductor layer 5 or the highly doped part of the depletion region layer 4 to generate non-radiative recombination with holes cannot be achieved due to the thin thickness, and energy loss is caused due to the large thickness resistance. Third, since the first superlattice layer 41 and the second superlattice layer 42 have large energy band differences, an effect of reducing the energy band tilt can be achieved.
In some embodiments of the present invention, the period of alternate growth of the first superlattice layer 41 is 2 to 5 periods; including but not limited to a point value of any one of 3 cycles, 4 cycles, or a range value between any two.
Preferably, the thickness of the first superlattice layer 41 is 3-6 nm, including but not limited to any one of 3.5nm, 4nm, 4.5nm, 5nm, 5.5nm, or a range between any two.
In some embodiments of the present invention, the period of alternate growth of the second superlattice layer 42 is 2-5 periods; including but not limited to a point value of any one of 3 cycles, 4 cycles, or a range value between any two.
Preferably, the thickness of the second superlattice layer 42 is 10-15 nm, including but not limited to a point value of any one of 10.5nm, 11nm, 12nm, 13nm, 14nm, 14.5nm, or a range value between any two.
And the first superlattice layer and the second superlattice layer in the growth period and the thickness range adopt superlattice growth to facilitate current diffusion, so that the lateral expansion capability of current can be improved under different current densities. The first superlattice layer 41 has a high growth energy band, is biased to three-dimensional growth, is too thick to easily generate cracks, affects the growth quality of the epitaxial layer, is too thin to play a role in limiting electrons, and is easy to generate non-radiative recombination. Due to the P-type GaN transition layer 43, the second superlattice layer 42 may be grown thicker than the first superlattice layer 41, so as to obtain more holes.
In some embodiments of the present invention, the doping concentration of the P-type impurity used in the first superlattice layer 41 (i.e., the doping concentration of the P-type impurity used in the P-type AlGaN layer in the first superlattice layer) is 5×10 17 ～5×10 18 atom/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the Including but not limited to 6 x 10 17 atom/cm 3 、7×10 17 atom/cm 3 、8×10 17 atom/cm 3 、9×10 17 atom/cm 3 、1×10 18 atom/cm 3 、2×10 18 atom/cm 3 、3×10 18 atom/cm 3 、4×10 18 atom/cm 3 Any one of the point values or a range value between any two.
And/or;
the doping concentration of the P-type impurity used in the second superlattice layer 42 (i.e., the doping concentration of the P-type impurity used in the P-type GaN layer and/or the P-type InN layer in the second superlattice layer) is 5×10 18 ～2×10 20 atom/cm 3 Including but not limited to 6 x 10 18 atom/cm 3 、7×10 18 atom/cm 3 、8×10 18 atom/cm 3 、9×10 18 atom/cm 3 、1×10 19 atom/cm 3 、3×10 19 atom/cm 3 、5×10 19 atom/cm 3 、7×10 19 atom/cm 3 、9×10 19 atom/cm 3 、1×10 20 atom/cm 3 Any one of the point values or a range value between any two.
By setting the doping concentration of the specific P-type impurity, the doping concentration of the P-type impurity is gradually increased, so that more holes can be provided to compensate the energy loss of the P-type semiconductor layer 5 in the depletion region layer 4; on the other hand, a part of electrons can be prevented from crossing the P-type GaN transition layer 43 to reach the P-type semiconductor layer 5 and the highly doped part of the second superlattice layer 42 without radiative recombination.
In some specific embodiments of the present invention, the active layer 3 includes InGaN well layers and GaN barrier layers grown in periodic alternating layers; the depletion region layer 4 is provided as a last layer barrier layer on the surface of the InGaN well layer or the GaN barrier layer.
Fig. 3 is a schematic structural diagram of an N-type semiconductor layer 2 according to the present invention. In some specific embodiments of the present invention, the N-type semiconductor layer 2 includes an undoped GaN layer 202 and/or an N-type GaN layer 203 doped with N-type impurities, which are stacked.
In some specific embodiments of the present invention, the thickness of the N-type semiconductor layer 2 is 1 to 8 μm, including but not limited to a dot value of any one of 2 μm, 3 μm, 4 μm, 5 μm, 6 μm or 7 μm or a range value between any two.
In some specific embodiments of the present invention, the N-type impurity comprises Si.
Preferably, the Si source comprises SiH 4 。
Preferably, the doping concentration of the N-type impurity is 1×10 19 ～1×10 20 atom/cm 3 。
In a specific embodiment of the present invention, the active layer 3 includes a GaN barrier layer and an InGaN well layer which are stacked.
Preferably, the active layer 3 comprises a GaN/InGaN superlattice structure, wherein the GaN layer and the InGaN layer are grown periodically and alternately.
Preferably, the growth period of the active layer 3 is 8 to 15 periods.
Preferably, the thickness of the active layer 3 is 1 to 3 μm, and 2 μm may be selected. The thickness range is beneficial to ensuring brightness and controlling cost.
In some specific embodiments of the present invention, the thickness of the depletion layer 4 is 5-40 nm, including but not limited to a point value of any one of 7nm, 9nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 38nm or a range value between any two.
And/or;
as shown in fig. 4, the P-type semiconductor layer 5 includes a low-temperature P-type InAlGaN layer 501 and/or a P-type GaN layer 503 doped with P-type impurities, which are stacked.
In some preferred embodiments of the present invention, the thickness of the P-type semiconductor layer 5 is 20 to 260nm, including but not limited to a point value of any one of 30nm, 50nm, 60nm, 70nm, 90nm, 100nm, 150nm, 160nm, 180nm, 200nm, 220nm, 240nm, or a range value between any two.
In some preferred embodiments of the invention, the P-type impurity comprises Mg.
Preferably, the Mg source comprises CP 2 Mg。
Preferably, the doping concentration of the P-type impurity is 1×10 19 ～1×10 20 atom/cm 3 。
In a preferred embodiment of the present invention, as shown in fig. 5, the LED epitaxial wafer further includes a low temperature GaN buffer layer 201. The low temperature GaN buffer layer 201 is disposed between the substrate and the undoped GaN layer 202.
In a preferred embodiment of the present invention, as shown in fig. 6, the LED epitaxial wafer further includes an AlGaN electron blocking layer 502, and the AlGaN electron blocking layer 502 is disposed between the low temperature P-type InAlGaN layer 501 and the P-type impurity doped P-type GaN layer 503.
Preferably, the thickness of the AlGaN electron blocking layer 502 is 20 to 30nm.
The invention also provides a preparation method of the LED epitaxial wafer, which comprises the following steps:
and an N-type semiconductor layer 2, an active layer 3, a depletion region layer 4 and a P-type semiconductor layer 5 are sequentially grown on the surface of the substrate 1 by adopting an MOCVD method, so that the LED epitaxial wafer is obtained.
Wherein the depletion region layer 4 includes a first superlattice layer 41 and a second superlattice layer 42 sequentially grown on the surface of the active layer.
The first superlattice layer 41 includes an AlN layer and a P-type AlGaN layer that are alternately grown periodically.
The second superlattice layer 42 includes a periodically alternating grown P-type GaN layer and P-type InN layer.
Among them, MOCVD is a novel vapor phase epitaxy technique which is a thin single crystal material in which organic compounds of group iii and group ii elements, hydrides of group V and group vi elements, and the like are used as crystal growth source materials, vapor phase epitaxy is performed on a substrate by a thermal decomposition reaction method, and various group iii-V, group ii-vi compound semiconductors, and a multiple solid solution thereof are grown.
The invention can reduce the energy loss of the depletion region by growing the depletion region layer 4 between the active layer 3 and the P-type semiconductor layer 5, thereby improving the light emitting efficiency of the GaN white light LED.
In a specific embodiment of the present invention, the substrate 1 is a patterned substrate.
Preferably, the patterned substrate comprises at least one of sapphire, alN, siC and Si.
In some specific embodiments of the present invention, a P-type GaN transition layer 43 is further included between the first superlattice layer 41 and the second superlattice layer 42.
Preferably, the growth temperature of the P-type GaN transition layer 43 is 800-850 ℃, including but not limited to any one of 810 ℃, 820 ℃, 830 ℃, 840 ℃ or a range between any two.
Preferably, the growth pressure of the P-type GaN transition layer 43 is 200-300 mbar, including but not limited to any one of 210mbar, 230mbar, 250mbar, 270mbar, 290mbar or a range between any two.
In some specific embodiments of the present invention, the growth temperature of the first superlattice layer 41 is 800-850 ℃; including but not limited to a point value of any one of 810 c, 820 c, 830 c, 840 c or a range value between any two.
And/or, the growth temperature of the second superlattice layer 42 is 850-900 ℃; including but not limited to any one of a point value or a range value between any two of 860 ℃, 870 ℃, 880 ℃, 890 ℃.
Preferably, the growth pressure of the first superlattice layer 41 and/or the second superlattice layer 42 is 200-300 mbar, including but not limited to a point value of any one of 210mbar, 230mbar, 250mbar, 270mbar, 290mbar, or a range value between any two.
In some specific embodiments of the present invention, the carrier gas used in the process of preparing the LED epitaxial wafer includes hydrogen and/or nitrogen.
Preferably, the flow rate of the nitrogen gas is 0-300L/min, including but not limited to any one of 50L/min, 100L/min, 150L/min, 200L/min and 250L/min, or a range value between any two.
Preferably, the flow rate of the hydrogen gas is 75-200L/min, including but not limited to any one of the point values or the range values between any two of 100L/min, 120L/min, 150L/min and 180L/min.
Preferably, the nitrogen source used in the process of preparing the LED epitaxial wafer comprises ammonia.
Preferably, the gallium source used in the process of preparing the LED epitaxial wafer includes TMGa (trimethylgallium) and/or TEGa (triethylgallium).
Preferably, the indium source used in the process of preparing the LED epitaxial wafer includes TMIn (trimethylindium) and/or TEIn (triethylindium).
Preferably, the aluminum source used in the process of preparing the LED epitaxial wafer includes TMAl (trimethylaluminum) and/or TEAl (triethylaluminum).
Preferably, in the process of preparing the LED epitaxial wafer, the pressure of the reaction cavity is 130-600 mbar, including but not limited to a point value of any one of 150mbar, 200mbar, 250mbar, 300mbar, 350mbar, 400mbar, 450mbar, 500mbar and 550mbar or a range value between any two.
Preferably, the growth temperature of the N-type semiconductor layer 2 is 500 to 1200 ℃, including but not limited to 550 ℃, 600 ℃, 650 ℃, 700 ℃, 800 ℃, 900 ℃, 1000 ℃, 1100 ℃ or any one of the point values or any range value between the two; the reaction chamber pressure is 200-600 mbar, including but not limited to a point value of any one of 250mbar, 300mbar, 350mbar, 400mbar, 450mbar, 500mbar, 550mbar or a range value between any two.
Preferably, in the process of growing the N-type semiconductor layer 2, the flow rate of the hydrogen (carrier gas) is 150-200L/min, including but not limited to a point value of any one of 160L/min, 170L/min, 180L/min, 190L/min or a range value between any two.
Preferably, in the process of growing the N-type GaN layer 203 doped with the N-type impurity, the flow rate of the N-type impurity is 30-1200 sccm, including, but not limited to, a point value of any one of 40sccm, 50sccm, 60sccm, 80sccm, 100sccm, 160sccm, 200sccm, 300sccm, 400sccm, 500sccm, 700sccm, 800sccm, 1000sccm, 1100sccm, or a range value between any two of them.
In a specific embodiment of the present invention, the growth temperature of the active layer 3 is 750 to 800 ℃, including but not limited to, a point value of any one of 760 ℃, 770 ℃, 780 ℃, 790 ℃ or a range value between any two; the reaction chamber pressure is 200-300 mbar, including but not limited to a point value of any one of 210mbar, 230mbar, 250mbar, 270mbar, 280mbar, 290mbar or a range value between any two.
Preferably, the hydrogen (carrier gas) is introduced at a flow rate of 150-200L/min during the growth of the active layer 3, including but not limited to a point value of any one of 160L/min, 170L/min, 180L/min, 190L/min or a range value between any two.
In a specific embodiment of the present invention, the growth temperature of the P-type semiconductor layer 5 is 750-1050 ℃, including, but not limited to, any one of 800 ℃, 850 ℃, 900 ℃, 950 ℃, 1000 ℃, 1030 ℃ or a range between any two; the reaction chamber pressure is 100-500 mbar, including but not limited to a point value of any one of 150mbar, 200mbar, 250mbar, 300mbar, 350mbar, 400mbar, 450mbar or a range value between any two.
Preferably, in the process of growing the P-type semiconductor layer 5, the flow rate of the hydrogen (as the carrier gas) is 100-150L/min, including but not limited to a point value of any one of 110L/min, 120L/min, 130L/min, 140L/min or a range value between any two.
Preferably, in the process of growing the P-type semiconductor layer 5, the flow rate of the P-type impurity is 50 to 2500sccm, including, but not limited to, a point value of any one of 80sccm, 100sccm, 150sccm, 200sccm, 250sccm, 300sccm, 400sccm, 500sccm, 600sccm, 800sccm, 1000sccm, 1200sccm, 1400sccm, 1500sccm, 1700sccm, 1900sccm, 2000sccm, 2300sccm, 2400sccm, or a range value between any two of them.
Preferably, after the N-type semiconductor layer 2, the active layer 3, the depletion region layer 4, and the P-type semiconductor layer 5 are sequentially grown, a cooling step is further included.
The invention also provides an LED chip, which comprises the LED epitaxial wafer. The LED chip has high internal quantum efficiency and good luminous performance.
Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only for illustrating the present invention and should not be construed as limiting the scope of the present invention. The specific conditions are not noted in the examples and are carried out according to conventional conditions or conditions recommended by the manufacturer. The reagents or apparatus used were conventional products commercially available without the manufacturer's attention.
Example 1
The LED epitaxial wafer provided in this embodiment refers to fig. 1, which includes an N-type semiconductor layer (Si-doped N-type GaN layer) 2, an active layer 3 (GaN barrier layer and InGaN well layer), a depletion region layer 4, and an N-type semiconductor layer (Mg-doped P-type GaN layer) 5, which are sequentially stacked on the surface of a sapphire substrate 1.
Wherein the depletion region layer 4 comprises a first superlattice layer 41 (periodically and alternately grown AlN layer and P-type AlGaN layer with thickness of 4 nm) and a second superlattice layer 42 (periodically and alternately grown P-type GaN layer and P-type InN layer with thickness of 12 nm) which are sequentially stacked;
the preparation method of the LED epitaxial wafer provided by the embodiment adopts an MOCVD method and adopts high-purity H 2 As carrier gas, high purity NH 3 As an N source, TEGa as a gallium source, TEAl as an aluminum source.
The preparation method specifically comprises the following steps:
(1) A sapphire (AlN-plated) substrate 1, which is a PSS substrate, is processed, and an AlN layer is deposited on the PSS pattern: at 1000-1200 DEG CThe pressure of the reaction cavity is 100-300 mbar, and 75-150L/min H is introduced 2 And (3) treating for 2-5 min under the condition.
(2) Growing an N-type semiconductor layer (Si-doped N-type GaN layer) 2: at the temperature of 1000-1200 ℃, the pressure of the reaction cavity is 300-600 mbar, H of 150-200L/min 2 Under the condition of introducing 45000-60000 sccm of NH 3 The inflow rate of TEGa is 800-1200 sccm, siH 4 The flow rate of the mixture is 30-80 sccm, and the doping concentration of Si is 1 multiplied by 10 19 ～1×10 20 atom/cm 3 Is grown under the condition of (2).
(3) Growing an active layer 3: growing InGaN well layer, controlling the pressure of the reaction cavity at 200-300 mbar, controlling the temperature at 750-800 ℃, and introducing NH with the flow rate of 65000-75000 sccm 3 The inflow rate of TEGa is 400-800 sccm, N 2 The flow rate is 50000-70000 sccm. Growing GaN barrier layer, growing to 850-900 deg.C, N 2 Flow rate 30000-50000 sccm, H 2 The flow rate is 10000-30000 sccm, the inflow rate of TEGa is 800-1200 sccm, siH 4 The flow rate of the gas is 5-20 sccm, and the growth cycle number is 8-15.
(4) Growing a depletion region layer 4: the temperature of the reaction cavity is regulated to 800-850 ℃, other conditions are kept unchanged, an AlN/P type AlGaN superlattice structure is grown, the growth period is 2-5 periods, wherein the doping concentration of Mg (namely P type impurities used in the P type AlGaN) is 5 multiplied by 10 17 Uniformly increase to 5×10 18 atom/cm 3 ；
Then, the temperature of the reaction cavity is increased to 850-900 ℃ (other conditions are not changed), the P-type GaN/P-type InN superlattice structure is grown, the growth period is 2-5 periods, wherein the doping concentration of Mg (namely P-type impurities used in the P-type GaN/P-type InN superlattice structure) is 5 multiplied by 10 18 atom/cm 3 Uniformly increase to 2×10 20 atom/cm 3 。
(5) Growing a P-type semiconductor layer 5 (Mg-doped P-type GaN layer): introducing NH of 50000-70000 sccm into the reaction chamber at 950-1000deg.C and 200-500 mbar 3 1500-2500 sccm TEGa, 1000-2000 sccm CP 2 Growing under Mg condition; wherein the doping concentration of Mg is 1 multiplied by 10 19 atom/cm 3 ～1×10 20 atom/cm 3 。
(6) And cooling to obtain the LED epitaxial wafer.
Example 2
The LED epitaxial wafer provided in this embodiment refers to fig. 7, which includes an N-type semiconductor layer 2, an active layer 3, a depletion region layer 4, and a P-type semiconductor layer 5 stacked in order on the surface of a sapphire substrate 1.
Wherein the N-type semiconductor layer 2 includes a low-temperature GaN buffer layer 201, an undoped GaN layer 202, and an N-type GaN layer doped with N-type impurities (Si-doped N-type GaN layer) 203, which are stacked in this order;
the active layer 3 is a GaN/InGaN superlattice structure layer (GaN and InGaN are grown periodically alternately);
the depletion region layer 4 includes a first superlattice layer 41 (periodically and alternately grown AlN layer and P-type AlGaN layer, with a thickness of 6 nm), a P-type GaN transition layer 43 (periodically and alternately grown P-type GaN layer and P-type InN layer, with a thickness of 15 nm) and a second superlattice layer 42 (periodically and alternately grown GaN layer and P-type InN layer) stacked in this order;
the P-type semiconductor layer 5 includes a low-temperature P-type InAlGaN layer (In and Al doped low-temperature P-type GaN layer) 501 (40 nm In thickness), an AlGaN electron blocking layer 502 (25 nm In thickness) and a P-type impurity doped P-type GaN layer (Mg doped P-type GaN layer) 503 (100 nm In thickness) stacked In this order.
The preparation method of the LED epitaxial wafer provided by the embodiment adopts an MOCVD method and adopts high-purity H 2 As carrier gas, high purity NH 3 As N source, TMGa (TMGa) as a metal organic source, TMIn as an indium source, TMAL as an aluminum source, CP 2 Mg as P-type dopant, siH 4 As the N-type dopant, an N-type semiconductor layer 2, an active layer 3, a depletion region layer 4, and a P-type semiconductor layer 5 are grown in this order on the surface of the substrate 1.
The preparation method specifically comprises the following steps:
(1) A sapphire (AlN-plated) substrate 1, which is a PSS substrate, is processed, and an AlN layer is deposited on the PSS pattern: at the temperature of 1000-1200 ℃, the pressure of the reaction cavity is 100-300 mbar, 75-150L/min H is introduced 2 And (3) treating for 2-5 min under the condition.
(2) Low temperature GaN buffer layer 201 (low temperature undoped N-type GaN buffer layer) is grown: introducing NH of 15000-30000 sccm at 500-800 deg.C and reaction chamber pressure of 200-500 mbar 3 And 150 to 200L/min of H 2 Under the condition, a small island is formed on the low-temperature undoped N-type GaN buffer layer.
(3) Growing an undoped GaN layer 202 (undoped N-type GaN layer): introducing 45000-60000 sccm NH at 1000-1200deg.C and 300-600 mbar pressure in the reaction chamber 3 The inflow rate of TMGa is 200-700 sccm, H is 150-200L/min 2 And growing an undoped N-type GaN layer under the condition.
(4) Growing an N-type GaN layer 203 doped with N-type impurities (Si-doped N-type GaN layer), maintaining the pressure, temperature, and H of step (3) 2 Under the condition of 45000-70000 sccm NH 3 The inflow rate of TMGa is 800-1200 sccm, siH 4 The flow rate of the mixture is 30-80 sccm, and the doping concentration of Si is 1 multiplied by 10 19 ～1×10 20 atom/cm 3 。
(5) Growing an active layer 3: the growth of quantum well (InGaN) controls the pressure of the reaction cavity at 200-300 mbar, the temperature at 750-800 ℃ and the NH with the flow rate of 65000-75000 sccm is introduced 3 ，N 2 The flow rate is 50000-70000 sccm, and the inflow rate of TMGa is 400-800 sccm; the growth of quantum barrier (GaN) increases the temperature to 850-900 ℃ and N 2 The flow rate is set to 30000-50000 sccm, H 2 The flow rate is set to 10000-30000 sccm, the inflow rate of TMGa is 800-1200 sccm, siH 4 The flow rate of the gas is 5-20 sccm, and the growth cycle number is 8-15.
(6) The first superlattice layer 41 is grown: the temperature of the reaction cavity is regulated to 800-850 ℃, other conditions are kept unchanged (the same as that of the step (5)), an AlN/P AlGaN superlattice structure is grown, the growth period is 2-5 periods, wherein the doping concentration of Mg is 5 multiplied by 10 within 10-60 seconds 17 atom/cm 3 Uniformly increase to 5×10 18 atom/cm 3 。
(7) Growing a P-type GaN transition layer 43: the reaction chamber conditions were unchanged (same as in step (6)), and a P-type GaN transition layer 43 was grown.
(8) Growth of secondSuperlattice layer 42: the temperature of the reaction cavity is increased to 850-900 ℃ (other conditions are the same as those in the step (7)), the superlattice structure of the P-type GaN/P-type InN layer is grown, the growth period is 2-5 periods, and the doping concentration of Mg is 5 multiplied by 10 18 atom/cm 3 Uniformly increase to 2×10 20 atom/cm 3 。
(9) A low temperature P-type InAlGaN layer (Mg as P-type impurity) 501 is grown: the temperature is reduced to 750 to 800 ℃, the pressure of a reaction cavity is regulated to 200 to 300mbar, and NH of 50000 to 70000sccm is introduced 3 TMGa of 1500-2000 sccm, H of 100-150L/min 2 Obtaining a low-temperature P-type InAlGaN layer under the conditions of 50-150 sccm TMAL and 500-800 sccm TMIn; wherein the doping concentration of Mg is 5×10 within 10-60 s 19 atom/cm 3 To 1X 10 20 atom/cm 3 。
(10) Growth of AlGaN electron blocking layer 502: introducing NH of 50000-70000 sccm at 950-1050 deg.C and 100-200 mbar pressure in the reaction chamber 3 800-1500 sccm TMGa, 100-150L/min H 2 And growing an AlGaN electron blocking layer under the condition of TMAL of 100-200 sccm.
(11) A P-type GaN layer 503 doped with P-type impurities (Mg-doped P-type GaN layer) is grown: introducing NH of 50000-70000 sccm into the reaction chamber at 950-1000deg.C and 200-500 mbar 3 1500-2500 sccm TMGa and 1000-2000 sccm CP 2 Growing under Mg condition; wherein the doping concentration of Mg is 1 multiplied by 10 19 atom/cm 3 ～1×10 20 atom/cm 3 。
(12) And cooling to obtain the LED epitaxial wafer.
Example 3
The LED epitaxial wafer provided in this embodiment refers to fig. 8, which includes an N-type semiconductor layer 2, an active layer 3, a depletion region layer 4, and a P-type semiconductor layer 5 stacked in order on the surface of a sapphire substrate 1.
Wherein the N-type semiconductor layer 2 comprises a low-temperature GaN buffer layer 201, an undoped GaN layer 202, and an N-type GaN layer (Si-doped N-type GaN layer) 203 (thickness of 3 μm) doped with N-type impurities, which are stacked in this order;
the active layer 3 is a GaN/InGaN superlattice structure layer, namely an InGaN well layer and a GaN barrier layer are grown periodically and alternately;
the depletion region layer 4 is the last barrier layer of the active layer 3 and is located on the InGaN well layer or the GaN barrier layer. The depletion region layer 4 is preferably located on the GaN barrier layer in this embodiment, and includes a first superlattice layer 41 and a second superlattice layer 42 that are stacked in this order.
Wherein the thickness of the first superlattice layer 41 is 3nm, and the first superlattice layer comprises an AlN layer and a P-type AlGaN layer which are periodically and alternately grown; the second superlattice layer 42 has a thickness of 10nm and includes periodically and alternately grown P-type GaN layers and P-type InN layers.
The P-type semiconductor layer 5 includes a low-temperature P-type InAlGaN layer (In and Al doped low-temperature P-type GaN layer) 501, an algan electron blocking layer 502, and a P-type impurity doped P-type GaN layer (Mg doped P-type GaN layer) 503, which are stacked In this order.
The method for manufacturing the LED epitaxial wafer according to this embodiment is substantially the same as that of embodiment 2, except that step (7) is not included (i.e., the P-type GaN transition layer 43 is not grown), but the second superlattice layer 42 is directly grown after the first superlattice layer 41 is obtained. Wherein the TMAL flow rate is 50-80 sccm when the first superlattice layer 41 is grown.
The potential energy of a first superlattice structure formed by alternately stacking the AlN layer and the P-type AlGaN layer in the depletion region is higher than that of the GaN barrier layer and the low-temperature P-type AlInGaN layer, so that electrons can be blocked more effectively, and electron overflow is reduced. The second superlattice structure formed by alternately stacking the P-type doped GaN layers and the InN layers aims to supplement the capacity loss of holes in the depletion region, improve the number of holes in the active layer and further improve the electron-hole recombination radiation efficiency. In addition, the AlN layer, the AlGaN layer, the GaN layer and the InN layer which are sequentially arranged in the depletion region have the potential gradually reduced from high to low, so that the cavity in the P-type layer can enter the active layer more easily, the cavity concentration in the active layer is improved, and the internal quantum efficiency of the light-emitting diode is further improved.
While the invention has been illustrated and described with reference to specific embodiments, it is to be understood that the above embodiments are merely illustrative of the technical aspects of the invention and not restrictive thereof; those of ordinary skill in the art will appreciate that: modifications may be made to the technical solutions described in the foregoing embodiments, or equivalents may be substituted for some or all of the technical features thereof, without departing from the spirit and scope of the present invention; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions; it is therefore intended to cover in the appended claims all such alternatives and modifications as fall within the scope of the invention.
Claims (16)
1. An LED epitaxial wafer is characterized by comprising an N-type semiconductor layer, an active layer, a depletion region layer and a P-type semiconductor layer which are sequentially stacked on the surface of a substrate;
the depletion region layer comprises a first superlattice layer and a second superlattice layer which are sequentially stacked; the first superlattice layer is arranged on the top of the active layer, and the second superlattice layer is arranged on the top of the first superlattice layer;
the first superlattice layer comprises an AlN layer and a P-type AlGaN layer which are grown periodically and alternately;
the second superlattice layer comprises a P-type GaN layer and a P-type InN layer which are periodically and alternately grown.
2. The LED epitaxial wafer of claim 1, wherein a P-type GaN transition layer is further disposed between the first superlattice layer and the second superlattice layer.
3. The LED epitaxial wafer of claim 2, wherein the thickness of the P-type GaN transition layer is 1-2 nm.
4. The LED epitaxial wafer of claim 1, wherein the period of alternate growth of the first superlattice layer is 2-5 periods.
5. The LED epitaxial wafer of claim 1, wherein the thickness of the first superlattice layer is 3-6 nm.
6. The LED epitaxial wafer of claim 1, wherein the period of alternate growth of the second superlattice layer is 2-5 periods.
7. The LED epitaxial wafer of claim 1, wherein the thickness of the second superlattice layer is 10-15 nm.
8. The LED epitaxial wafer of claim 1, wherein the P-type impurity used in the first superlattice layer has a doping concentration of 5 x 10 17 ~5×10 18 atom/cm 3 ；
And/or;
the doping concentration of the P-type impurity used in the second superlattice layer is 5×10 18 ~2×10 20 atom/cm 3 。
9. The LED epitaxial wafer of claim 1, wherein the active layer comprises InGaN well layers and GaN barrier layers grown in periodic alternating layers; the depletion region layer is the last barrier layer and is arranged on the surface of the InGaN well layer or the GaN barrier layer.
10. The LED epitaxial wafer of claim 1, wherein the depletion region layer has a thickness of 5-40 nm.
11. The method for preparing the LED epitaxial wafer according to any one of claims 1 to 10, characterized by comprising the steps of:
an MOCVD method is adopted, an N-type semiconductor layer, an active layer, a depletion region layer and a P-type semiconductor layer are sequentially grown on the surface of a substrate, and the LED epitaxial wafer is obtained;
the depletion region layer comprises a first superlattice layer and a second superlattice layer which are sequentially grown on the surface of the active layer;
the first superlattice layer comprises an AlN layer and a P-type AlGaN layer which are grown periodically and alternately;
the second superlattice layer comprises a P-type GaN layer and a P-type InN layer which are periodically and alternately grown.
12. The method of claim 11, further comprising a P-type GaN transition layer between the first superlattice layer and the second superlattice layer.
13. The method for preparing the LED epitaxial wafer according to claim 12, wherein the growth temperature of the P-type GaN transition layer is 800-850 ℃ and the growth pressure is 200-300 mbar.
14. The method for preparing the LED epitaxial wafer according to claim 11, wherein the growth temperature of the first superlattice layer is 800-850 ℃;
and/or the growth temperature of the second superlattice layer is 850-900 ℃.
15. The method for manufacturing an LED epitaxial wafer according to claim 11, wherein the growth pressure of the first superlattice layer and/or the second superlattice layer is 200-300 mbar.
16. An LED chip comprising the LED epitaxial wafer according to any one of claims 1 to 10.
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