CN218351492U

CN218351492U - Epitaxial wafer and light emitting diode

Info

Publication number: CN218351492U
Application number: CN202221232215.2U
Authority: CN
Inventors: 曹斌斌; 胡加辉; 金从龙
Original assignee: Jiangxi Zhao Chi Semiconductor Co Ltd
Current assignee: Jiangxi Zhao Chi Semiconductor Co Ltd
Priority date: 2022-05-20
Filing date: 2022-05-20
Publication date: 2023-01-20
Anticipated expiration: 2032-05-20

Abstract

The utility model provides an epitaxial wafer and emitting diode, epitaxial wafer include the substrate, still include in proper order range upon range of buffer lamination, N type semiconductor layer, active luminescent layer, electron on the substrate and block stromatolite and P type semiconductor layer; the buffer lamination layer comprises a first buffer sublayer, a second buffer sublayer and a third buffer sublayer which are sequentially laminated on the substrate, the first buffer sublayer and the second buffer sublayer are InN layers, the third buffer sublayer is an N-type doped InGaN layer, and the In content of the third buffer sublayer decreases In sequence along the direction far away from the substrate. The utility model provides an epitaxial wafer is through setting up the buffer lamination to reduce the lattice mismatch between substrate and the epitaxial layer, reduce epitaxial growth defect, and then improve epitaxial growth crystalline quality, thereby improve luminous efficacy.

Description

Epitaxial wafer and light emitting diode

Technical Field

The utility model relates to the field of semiconductor technology, in particular to epitaxial wafer and emitting diode.

Background

In recent years, the application field of the light emitting diode is becoming wider and the market demand is expanding, and the light emitting diode has been widely applied to the fields of displays, television lighting and decoration and illumination. The epitaxial wafer in the led is a core part of the led, and therefore, the development of the epitaxial wafer of the led is receiving much attention.

The epitaxial structure of the light emitting diode generally comprises a substrate and an epitaxial layer grown on the substrate, and because the substrate is made of materials generally containing silicon, and huge lattice mismatch exists between the silicon and GaN in the epitaxial layer, and the epitaxial layer influences the crystal growth quality due to thermal expansion in the growth process, the epitaxial growth defect is caused, and the light emitting efficiency of the light emitting diode is further low.

SUMMERY OF THE UTILITY MODEL

Based on this, the utility model provides an epitaxial wafer to reduce the lattice mismatch between substrate and the epitaxial layer, reduce epitaxial growth defect, and then improve epitaxial growth crystalline quality, thereby improve luminous efficacy.

An epitaxial wafer comprises a substrate, and further comprises a buffer lamination layer, an N-type semiconductor layer, an active light emitting layer, an electron blocking lamination layer and a P-type semiconductor layer which are sequentially laminated on the substrate;

the buffer lamination layer comprises a first buffer sub-layer, a second buffer sub-layer and a third buffer sub-layer which are sequentially stacked on the substrate, the first buffer sub-layer and the second buffer sub-layer are InN layers, the third buffer sub-layer is an N-type doped InGaN layer, and the In content of the N-type doped InGaN layer is sequentially decreased In the direction away from the substrate.

In summary, according to the above-mentioned epitaxial wafer, the buffer stack is additionally added between the substrate and the epitaxial layer, and the lattice mismatch between the buffer stack and the epitaxial layer is low, so as to ensure the growth quality of the epitaxial layer and achieve the purpose of improving the light emitting efficiency. Specifically, the buffer lamination comprises a first buffer sublayer, a second buffer sublayer and a third buffer sublayer, and the dislocation density between the substrate and the epitaxial layer can be relieved by arranging the first buffer sublayer and the second buffer sublayer, so that the epitaxial crystal growth quality is improved; the third buffer sublayer directly contacts with the N-type semiconductor layer In the epitaxial layer at the moment, so that the lattice mismatch between the second buffer sublayer and the subsequent epitaxial layer can be reduced through the decreased In content In the third buffer sublayer, the phenomenon that the lattice mismatch is large due to the direct contact between the siliceous substrate and the epitaxial layer is avoided, the epitaxial growth defects are reduced, the epitaxial crystal quality is improved, more electrons can be provided through the N-type doping In the third buffer sublayer, the electron density In the active light-emitting layer is increased, the recombination probability is improved, the light-emitting efficiency can be further improved, and the problem that the light-emitting efficiency is influenced due to the huge lattice mismatch between the substrate and the epitaxial layer In the traditional epitaxial structure is solved.

Further, the electron blocking lamination layer comprises a first electron blocking sublayer and a second electron blocking sublayer which are periodically and alternately laminated on the active light emitting layer in sequence, the first electron blocking sublayer is a GaN layer, any one of the second electron blocking sublayers is a P-type doped AlGaN layer, and the Al content of the AlGaN layer is gradually reduced in sequence along the direction far away from the active light emitting layer.

Further, the thickness of any first electron blocking sublayer decreases in sequence along the direction away from the active light emitting layer.

Furthermore, the P-type doping concentration of the second electron blocking sub-layer increases progressively in sequence along the direction far away from the active light emitting layer and is smaller than that of the P-type semiconductor layer.

Furthermore, the doping sources of the second electron blocking sublayer and the P-type semiconductor layer are both Mg, and the second electron blocking sublayer is a P-type AlGaN layer doped with Mg.

Further, the N-type doping concentration of the third buffer sublayer sequentially increases progressively along the direction far away from the substrate and is smaller than the N-type doping concentration of the N-type semiconductor layer.

Furthermore, the doping sources of the third buffer sublayer and the N-type semiconductor layer are Si, and the third buffer sublayer is an Si-doped N-type InGaN layer.

Further, the thickness of the second buffer sublayer is 20-60 nm.

Further, the thickness of the first buffer sublayer is 5-40 nm.

The utility model discloses another aspect still provides a light emitting diode, light emitting diode includes as above-mentioned epitaxial wafer.

Drawings

Fig. 1 is a schematic structural diagram of an epitaxial wafer according to an embodiment of the present invention.

Description of the main element symbols:

10. substrate, 20, buffer stack, 201, first buffer sublayer, 202, second buffer sublayer, 203, third buffer sublayer, 30, N-type semiconductor layer, 40, active light emitting layer, 50, electron blocking stack, 501, first electron blocking sublayer, 502, second electron blocking stack, 60, P-type semiconductor layer

The following detailed description of the invention will be further described in conjunction with the above-identified drawings.

Detailed Description

In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. Several embodiments of the invention are presented in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Referring to fig. 1, a schematic structural diagram of an epitaxial wafer according to a first embodiment of the present invention is shown, the epitaxial wafer includes a substrate 10, and a buffer stack 20 and an epitaxial layer sequentially stacked on the substrate 10, wherein:

the epitaxial layer sequentially comprises an N-type semiconductor layer 30, an active light emitting layer 40, an electron blocking stack 50 and a P-type semiconductor layer 60 from bottom to top, the N-type semiconductor layer 30 is stacked on the buffer stack 20, that is, in order to avoid a larger lattice mismatch caused by direct contact between the silicon substrate 10 and the epitaxial layer, a buffer stack 20 is newly added between the substrate 10 and the epitaxial layer, the buffer stack 20 comprises a first buffer sublayer 201, a second buffer sublayer 202 and a third buffer sublayer 203 which are sequentially stacked on the substrate 10, in this embodiment, the first buffer sublayer 201 and the second buffer sublayer 202 are both InN layers, the third buffer sublayer 203 is an N-type doped InGaN layer, and the In content of the N-type doped InGaN layer is sequentially decreased along a direction away from the substrate 10, that is, the In content of the third buffer sublayer is lower In a direction closer to the N-type semiconductor layer 30, so as to avoid that the epitaxial growth quality is affected by the too large lattice mismatch when the epitaxial layer is grown, the problem of the epitaxial growth quality is avoided being decreased, and the light emitting efficiency is further improved.

The growth temperature of the first buffer sub-layer 201 is 300-550 ℃, the growth pressure is 200-300 Torr, the growth thickness is 5-40 nm, the growth temperature of the first buffer sub-layer 201 can be set to 300 ℃, 400 ℃, 500 ℃ and the like so as to ensure that the growth temperature of the first buffer sub-layer 201 is at a low temperature level, the growth pressure of the first buffer sub-layer 201 can be set to 200Torr, 250Torr, 300Torr and the like so as to ensure that the growth pressure of the first buffer sub-layer 201 is at a high pressure level, and under the growth conditions of low temperature and high pressure, the first buffer sub-layer 201 with the thickness of 5nm, 10nm, 20nm and the like is obtained, the first buffer sub-layer 201 adopts a three-dimensional growth mode, the surface of the first buffer sub-layer is rough, partial dislocation between the first buffer sub-layer 201 and the second buffer sub-layer 202 can be relieved, and the dislocation density is further reduced.

Further, the second buffer sub-layer 202 has a growth temperature of 550 to 700 ℃, a growth pressure of 100to 200Torr, and a growth thickness of 20 to 60nm. By way of example and not limitation, the growth temperature of the second buffer sub-layer 202 may be set to 550 ℃, 600 ℃, 650 ℃, and the like, so as to ensure that the growth temperature of the second buffer sub-layer 202 is at a high temperature level, and the growth pressure of the second buffer sub-layer 202 may be set to 100Torr, 150Torr, 200Torr, and the like, so as to ensure that the growth pressure of the second buffer sub-layer 202 is at a low pressure level, and by growing the second buffer sub-layer 202 with a thickness of 20nm, 30nm, 40nm, and the like at a high temperature and a low pressure level, the second buffer sub-layer 202 is grown in a three-dimensional growth mode to obtain a corresponding InN layer, at this time, the surface of the second buffer sub-layer 202 is relatively flat, on one hand, the relatively flat second buffer sub-layer 202 can fill up the rough surface of the first buffer sub-layer 201, and on the other hand, the rough surface of the first buffer sub-layer 201 can increase the contact area with the second buffer layer, so as to improve the bonding force between the first buffer sub-layer 201 and the second buffer sub-layer 202, thereby facilitating to improve the crystal growth quality of the buffer stack 20, that is improved.

The N-type doping concentration of the third buffer sublayer 203 sequentially increases along the direction away from the substrate 10 and is less than the N-type doping concentration of the N-type semiconductor layer 30. In this embodiment, electrons can be additionally provided through the third buffer sublayer 203, and the N-type doping concentration of a portion of the third buffer sublayer 203 closer to the N-type semiconductor layer 30 is higher, and meanwhile, the N-type doping concentration of a portion of the third buffer sublayer 203 closest to the N-type semiconductor layer 30 is the highest, and the highest N-type doping concentration of the third buffer sublayer 203 is smaller than the N-type doping concentration of the N-type semiconductor layer 30, so that the third buffer sublayer 203 can further expand current, reduce voltage, and improve product performance while increasing electron density and improving recombination efficiency.

Specifically, the doping sources of the third buffer sublayer 203 and the N-type semiconductor layer 30 are both Si, the third buffer sublayer 203 is an Si-doped N-type InGaN layer, the N-type semiconductor layer 30 is an Si-doped N-type GaN layer, when the N-type semiconductor layer 30 is grown, high-purity N2 and H2 are used as carrier gases to bring reactants TMGa, siH4 and NH3 into a reaction chamber, the reaction temperature is controlled to be 1000-1200 ℃, the pressure in the reaction chamber is 100-300torr, the thickness of the N-type gallium nitride layer is 1000-250nm, N-type doping is derived from SiH4, the N-type semiconductor layer 30 can be grown to serve as an electron supply, and the N-type semiconductor layer 30 serves as an electron supply.

The active light emitting layer 40 comprises InGaN multi-quantum well layers and GaN multi-quantum barrier layers which grow alternately, the period is 3-20, namely the InGaN multi-quantum well layers and the GaN multi-quantum barrier layers both comprise 3-20 layers, N2 is required to be introduced as carrier gas when the InGaN quantum well layers grow, N2 and NH3 are required to be introduced as carrier gas when the GaN multi-quantum barrier layers grow, the thickness of the well layers is 3-7nm, and the thickness of the barrier layers is 5-11nm. The In component content of the InGaN multi-quantum well layer is 0.2 to 0.5, the growth pressure of the InGaN multi-quantum well layer is 100to 300Torr, and the growth temperature of the InGaN multi-quantum well layer is 700 to 800 ℃. The growth pressure of the GaN multi-quantum barrier layer is 100-300Torr, and the growth temperature is 700-900 ℃. The InGaN/GaN multi-quantum well layer is a region where electrons and holes are radiated and recombined to release photons.

The electron blocking laminate 50 includes a first electron blocking sublayer 501 and a second electron blocking sublayer 502 alternately laminated on the active light emitting layer 40 periodically, the first electron blocking sublayer 501 is a GaN layer, each of the second electron blocking sublayers 502 in the electron blocking laminate 50 is a P-type doped AlGaN layer, and the Al content of the second electron blocking sublayer decreases sequentially along a direction away from the active light emitting layer 40. In this embodiment, the lattice mismatch between the second electron blocking sublayer 502 and the quantum barrier is reduced by the first electron blocking sublayer 501, the generation of defects is reduced, and the epitaxial growth quality is further improved.

The thickness of each first electron blocking sublayer 501 in the electron blocking stack 50 decreases in sequence in a direction away from the active light emitting layer 40. In this embodiment, the thickness of each first electron blocking sublayer 501 in the electron blocking stack 50 decreases gradually and then increases gradually along the direction away from the active light emitting layer 40, so that the input of raw materials can be reduced on the basis of reducing the lattice mismatch between the second electron blocking sublayer 502 and the quantum barrier.

In the electronic barrier stack 50, the P-type doping concentration of each second electronic barrier sublayer 502 increases gradually and is smaller than the P-type doping concentration of the P-type semiconductor layer 60 in the direction away from the active light emitting layer 40.

Specifically, the doping sources of the second electron blocking sublayer 502 and the P-type semiconductor layer 60 are Mg, the second electron blocking sublayer 502 is a P-type AlGaN layer doped with Mg, the P-type semiconductor layer 60 is a P-type GaN layer doped with Mg, in the process of growing the P-type gallium nitride layer, cp2Mg, TEGa and NH3 are used as reactants, carrier gas is high-purity N2 and H2, the growth temperature of the P-type gallium nitride layer is 700-1100 ℃, and the growth pressure is 100-400Torr.

The present invention further provides a light emitting diode, which includes all the structures of the epitaxial wafer in the above embodiments in this embodiment, and therefore has all the advantages of the epitaxial wafer in the above embodiments, and the description thereof will not be repeated.

The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. The epitaxial wafer comprises a substrate and is characterized by further comprising a buffer lamination layer, an N-type semiconductor layer, an active light emitting layer, an electron blocking lamination layer and a P-type semiconductor layer which are sequentially laminated on the substrate;

2. The epitaxial wafer of claim 1, wherein the electron blocking stack comprises a first electron blocking sublayer and a second electron blocking sublayer, which are periodically and alternately stacked on the active light emitting layer in sequence, wherein the first electron blocking sublayer is a GaN layer, any one of the second electron blocking sublayers is a P-type doped AlGaN layer, and the Al content of the AlGaN layer decreases in sequence in a direction away from the active light emitting layer.

3. The epitaxial wafer of claim 2, wherein the thickness of any of the first electron blocking sublayers decreases in a direction away from the active light emitting layer.

4. The epitaxial wafer of claim 3, wherein the P-type doping concentration of the second electron blocking sublayer increases in sequence in a direction away from the active light emitting layer and is less than the P-type doping concentration of the P-type semiconductor layer.

5. The epitaxial wafer of claim 1, wherein the active light emitting layer comprises InGaN multi-quantum well layers and GaN multi-quantum barrier layers which are alternately grown, and the period of the InGaN multi-quantum well layers and the GaN multi-quantum barrier layers is 3-20.

6. The epitaxial wafer of claim 1, wherein the N-type doping concentration of the third buffer sublayer increases in sequence in a direction away from the substrate and is less than the N-type doping concentration of the N-type semiconductor layer.

7. The epitaxial wafer of claim 5, wherein the thickness of the InGaN multi-quantum well layer is 3-7nm and the thickness of the GaN multi-quantum barrier layer is 5-11nm.

8. The epitaxial wafer of claim 1, wherein the thickness of the second buffer sublayer is 20 to 60nm.

9. The epitaxial wafer of claim 1, wherein the first buffer sublayer has a thickness of 5 to 40nm.

10. A light emitting diode comprising the epitaxial wafer of any one of claims 1 to 9.