CN114335273A

CN114335273A - LED epitaxial wafer, preparation method thereof and LED chip

Info

Publication number: CN114335273A
Application number: CN202111655190.7A
Authority: CN
Inventors: 吕腾飞; 展望; 芦玲
Original assignee: Huaian Aucksun Optoelectronics Technology Co Ltd
Current assignee: Huaian Aucksun Optoelectronics Technology Co Ltd
Priority date: 2021-12-30
Filing date: 2021-12-30
Publication date: 2022-04-12
Anticipated expiration: 2041-12-30
Also published as: CN114335273B

Abstract

The invention relates to the technical field of light emitting diode epitaxial wafers, in particular to an LED epitaxial wafer, a preparation method thereof and an LED chip. The LED epitaxial wafer comprises an N-type semiconductor layer, an active layer, a depletion region layer and a P-type semiconductor layer which are sequentially stacked on the surface of a substrate; the depletion region layer comprises a first superlattice layer and a second superlattice layer which are sequentially stacked; the first superlattice layer comprises AlN layers and P-type AlGaN layers which are periodically and alternately grown; the second superlattice layer comprises P-type GaN layers and P-type InN layers which are periodically and alternately grown. The potential energy of the first superlattice layer is high, electrons can be blocked, and overflow of the electrons is reduced; the second superlattice layer provides holes to reduce energy loss of the holes provided by the P-type semiconductor layer in a depletion region, so that the number of the holes in the active layer is increased, and the radiation recombination efficiency of electrons and the holes is improved.

Description

LED epitaxial wafer, preparation method thereof and LED chip

Technical Field

The invention relates to the technical field of light emitting diode epitaxial wafers, in particular to an LED epitaxial wafer, a preparation method thereof and an LED chip.

Background

Because of its advantages of long lifetime, low power consumption, and no pollution, gallium nitride (GaN) -based Light Emitting Diodes (LEDs) are widely used in many fields such as display and lighting. Among them, GaN is a wide band gap compound semiconductor material, which has the characteristics of emitting blue light, high temperature, high frequency, high voltage, high power, acid, alkali and corrosion resistance, etc., and is an important semiconductor material following germanium, silicon and gallium arsenide, which makes it play an important role in the technical field of blue light and ultraviolet optoelectronics, and is also an ideal material for manufacturing high-temperature and high-power semiconductor devices.

The LED epitaxial wafer refers to a specific single crystal thin film grown on a substrate heated to an appropriate temperature. The epitaxial wafer is positioned in the upstream link of an LED industrial chain, and is the link which has the highest technical content in the semiconductor lighting industry and has the greatest influence on the quality and cost control of a final product.

Although GaN-based LEDs have been industrialized, high brightness epitaxial wafers are critical for LEDs. The epitaxial wafer capable of improving the brightness of the GaN-based LED has important significance.

In view of the above, the present invention is particularly proposed.

Disclosure of Invention

The first purpose of the invention is to provide an LED epitaxial wafer, wherein a depletion region layer is arranged between an active layer and a P-type semiconductor layer, and the potential energy of a first superlattice layer of the depletion region layer is high, so that electrons can be blocked, and the overflow of the electrons is reduced; the second superlattice layer of the depletion region layer provides holes so as to reduce the energy loss of the holes provided by the P-type semiconductor layer in the depletion region, thereby increasing the number of the holes in the active layer and further improving the radiation recombination efficiency of electrons and holes. And the potential in the depletion region layer is changed from high to low, so that holes in the P-type semiconductor layer can easily enter the active layer, the number of the holes is further increased, the radiation recombination efficiency of electrons and the holes is improved, and the internal quantum efficiency of the light-emitting diode is finally improved.

The second purpose of the present invention is to provide a method for preparing the LED epitaxial wafer, where the LED epitaxial wafer prepared by the method can improve the internal quantum efficiency of the light emitting diode.

A third object of the present invention is to provide an LED chip having high internal quantum efficiency and good light emission performance.

In order to achieve the above purpose of the present invention, the following technical solutions are adopted:

the invention provides an LED epitaxial wafer, which comprises an N-type semiconductor layer, an active layer, a depletion region layer and a P-type semiconductor layer which are sequentially stacked on the surface of a substrate;

the depletion region layer comprises a first superlattice layer and a second superlattice layer which are sequentially stacked;

the first superlattice layer comprises AlN layers and P-type AlGaN layers which are periodically and alternately grown;

the second superlattice layer comprises P-type GaN layers and P-type InN layers which are periodically and alternately grown.

Preferably, a P-type GaN transition layer is further disposed between the first superlattice layer and the second superlattice layer;

preferably, the thickness of the P-type GaN transition layer is 1-2 nm.

Preferably, the period of the alternate growth of the first superlattice layer is 2-5 periods;

preferably, the thickness of the first superlattice layer is 3-6 nm.

Preferably, the period of the alternate growth of the second superlattice layer is 2-5 periods;

preferably, the thickness of the second superlattice layer is 10-15 nm.

Preferably, the doping concentration of the P-type impurity used in the first superlattice layer is 5 × 10¹⁷～5×10¹⁸atom/cm³；

And/or;

the doping concentration of the P-type impurity used in the second superlattice layer is 5 x 10¹⁸～2×10²⁰atom/cm³。

Preferably, the active layer comprises InGaN well layers and GaN barrier layers which are periodically and alternately grown in a laminated mode; the depletion region layer is the last barrier layer and is arranged on the surface of the InGaN potential well layer or the GaN barrier layer.

Preferably, the thickness of the depletion region layer is 5-40 nm.

The invention also provides a preparation method of the LED epitaxial wafer, which comprises the following steps:

growing an N-type semiconductor layer, an active layer, a depletion region layer and a P-type semiconductor layer on the surface of the substrate in sequence by adopting an MOCVD (metal organic chemical vapor deposition) method to obtain the LED epitaxial wafer;

wherein the depletion region layer comprises a first superlattice layer and a second superlattice layer which are sequentially grown on the surface of the active layer;

Preferably, a P-type GaN transition layer is further included between the first superlattice layer and the second superlattice layer;

preferably, the growth temperature of the P-type GaN transition layer is 800-850 ℃, and the growth pressure is 200-300 mbar.

Preferably, the growth temperature of the first superlattice layer is 800-850 ℃;

and/or the growth temperature of the second superlattice layer is 850-900 ℃;

preferably, the growth pressure of the first superlattice layer and/or the second superlattice layer is 200-300 mbar.

The invention also provides an LED chip comprising the LED epitaxial wafer.

Compared with the prior art, the invention has the beneficial effects that:

according to the LED epitaxial wafer provided by the invention, the depletion region layer is arranged between the active layer and the P-type semiconductor layer, and the depletion region layer comprises the first superlattice layer and the second superlattice layer which are sequentially stacked; the first superlattice layer comprises AlN layers and P-type AlGaN layers which are periodically and alternately grown, and the potential energy of the first superlattice layer is high, so that electrons can be blocked, and the overflow of the electrons is reduced. The second superlattice layer comprises a P-type GaN layer and a P-type InN layer which are periodically and alternately grown, can provide holes, reduces the energy loss of the holes provided by the P-type semiconductor layer in a depletion region, and increases the number of the holes in the active layer, thereby improving the radiation recombination efficiency of electrons and holes. And the electric potentials of the first superlattice layer and the second superlattice layer are changed from high to low, so that holes in the P-type semiconductor layer can easily enter the active layer, the number of the holes is further increased, the radiation recombination efficiency of electrons and the holes is improved, and finally the internal quantum efficiency of the light-emitting diode is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic structural diagram of an LED epitaxial wafer according to the present invention;

fig. 2 is another schematic structural diagram of an LED epitaxial wafer according to the present invention;

FIG. 3 is a schematic structural diagram of an N-type semiconductor layer according to the present invention;

FIG. 4 is a schematic structural diagram of a P-type semiconductor layer provided in the present invention;

FIG. 5 is a schematic structural view of another N-type semiconductor layer provided in the present invention;

FIG. 6 is a schematic structural view of another P-type semiconductor layer provided in the present invention;

fig. 7 is a schematic structural diagram of an LED epitaxial wafer according to embodiment 2 of the present invention;

fig. 8 is a schematic structural diagram of an LED epitaxial wafer according to embodiment 3 of the present invention.

Reference numerals:

1-a substrate; a 2-N type semiconductor layer; 201-low temperature GaN buffer layer;

202-an undoped GaN layer; 203-an N-type 3-active layer doped with N-type impurities;

a GaN layer;

4-depletion region layer; 41-a first superlattice layer; 42-a second superlattice layer;

a 43-P type GaN transition layer; a 5-P type semiconductor layer; 501-a low-temperature P-type InAlGaN layer;

502-AlGaN electron blocking layers; 503-P type doped with P type impurities

And a GaN layer.

Detailed Description

The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings and the detailed description, but those skilled in the art will understand that the following described embodiments are some, not all, of the embodiments of the present invention, and are only used for illustrating the present invention, and should not be construed as limiting the scope of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Fig. 1 is a schematic structural diagram of an LED epitaxial wafer according to the present invention; fig. 2 is another schematic structural diagram of an LED epitaxial wafer according to the present invention; FIG. 3 is a schematic structural diagram of an N-type semiconductor layer according to the present invention; FIG. 4 is a schematic structural diagram of a P-type semiconductor layer provided in the present invention; FIG. 5 is a schematic structural view of another N-type semiconductor layer provided in the present invention; FIG. 6 is a schematic structural view of another P-type semiconductor layer provided in the present invention; fig. 7 is a schematic structural diagram of an LED epitaxial wafer according to embodiment 2 of the present invention; fig. 8 is a schematic structural diagram of an LED epitaxial wafer according to embodiment 3 of the present invention.

As shown in fig. 1, the LED epitaxial wafer provided by the present invention includes an N-type semiconductor layer 2, an active layer 3, a depletion region layer 4, and a P-type semiconductor layer 5, which are sequentially stacked on a surface of a substrate 1.

The depletion region layer 4 includes a first superlattice layer 41 and a second superlattice layer 42 stacked in this order.

The first superlattice layer 41 includes AlN layers and P-type AlGaN layers that are alternately grown periodically.

The second superlattice layer 42 includes P-type GaN layers and P-type InN layers alternately grown periodically.

In the present invention, a depletion region layer 4 is provided between an active layer 3 and a P-type semiconductor layer 5, and the depletion region layer 4 includes a first superlattice layer 41 and a second superlattice layer 42 which are stacked in this order. The potential energy of the first superlattice layer 41 is high, and the first superlattice layer can block electrons and reduce overflow of electrons; the second superlattice layer 42 may provide holes, and reduce energy loss of the holes provided from the P-type semiconductor layer 5 in a depletion region, thereby increasing the number of holes in the active layer 3, and thus increasing radiative recombination efficiency of electrons and holes.

And, the potential of the first superlattice layer 41 in the depletion region layer 4 is higher than that of the second superlattice layer 42, so that holes in the P-type semiconductor layer 5 can easily enter the active layer 3, the number of holes is further increased, the radiation recombination efficiency of electrons and holes is improved, and finally, the internal quantum efficiency of the light emitting diode is improved.

As shown in fig. 2, in some specific embodiments of the present invention, a P-type GaN transition layer 43 is further disposed between the first superlattice layer 41 and the second superlattice layer 42.

Since the energy bands of the AlN layer and the P-type AlGaN layer are larger than the energy bands of the P-type GaN layer and the P-type InN layer, the P-type GaN transition layer 43 is used as a transition layer from high potential energy to low potential energy, and since the energy band difference between the first superlattice layer 41 and the second superlattice layer 42 is large, the effect of reducing the energy band tilt can be achieved.

Preferably, the thickness of the P-type GaN transition layer 43 is 1-2 nm, including but not limited to any value of 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm or a range value between any two.

The thickness of the P-type GaN transition layer 43 is set within the above range, and firstly, the P-type GaN transition layer is beneficial to the smoothness of the P-layer cavity from low potential energy to high potential energy. Second, the P-type GaN buffer layer 43 prevents a part of electrons from entering the P-type semiconductor layer 5 or the depletion region layer 4 beyond the first superlattice layer 41 from non-radiative recombination with holes. The thickness is thin, which cannot prevent part of electrons from entering the P-type semiconductor layer 5 beyond the first superlattice layer 41 or the high-doped part of the depletion region layer 4 from non-radiative recombination with holes, and the energy loss is caused by the increased resistance due to the thick thickness. Third, since the first superlattice layer 41 and the second superlattice layer 42 have a large energy band difference, an effect of reducing the band tilt can be obtained.

In some embodiments of the present invention, the period of the alternating growth of the first superlattice layer 41 is 2-5 periods; including but not limited to a point value of any of 3 cycles, 4 cycles, or a range of values between any two.

Preferably, the thickness of the first superlattice layer 41 is 3-6 nm, including but not limited to any one of 3.5nm, 4nm, 4.5nm, 5nm, 5.5nm, or a range therebetween.

In some embodiments of the present invention, the period of the alternating growth of the second superlattice layer 42 is 2-5 periods; including but not limited to a point value of any of 3 cycles, 4 cycles, or a range of values between any two.

Preferably, the thickness of the second superlattice layer 42 is 10-15 nm, including but not limited to the values of any one of 10.5nm, 11nm, 12nm, 13nm, 14nm, 14.5nm, or the range between any two.

In the first superlattice layer and the second superlattice layer within the growth period and the thickness range, superlattice growth is adopted to facilitate current diffusion, and the transverse expansion capability of current can be improved under different current densities. The first superlattice layer 41 has a high growth energy band, is biased to three-dimensional growth, is too thick and is easy to crack, affects the growth quality of an epitaxial layer, and is too thin to play a role in limiting electrons, so that non-radiative recombination is easy to generate. Due to the effect of the P-type GaN transition layer 43, the growth of the second superlattice layer 42 may be thickened relative to the growth of the first superlattice layer 41, so as to obtain more holes.

In some specific embodiments of the present invention, the doping concentration of the P-type impurity used in the first superlattice layer 41 (i.e., the doping concentration of the P-type impurity used in the P-type AlGaN layer in the first superlattice layer) is 5 × 10¹⁷～5×10¹⁸atom/cm³(ii) a Including but not limited to 6 x 10¹⁷atom/cm³、7×10¹⁷atom/cm³、8×10¹⁷atom/cm³、9×10¹⁷atom/cm³、1×10¹⁸atom/cm³、2×10¹⁸atom/cm³、3×10¹⁸atom/cm³、4×10¹⁸atom/cm³A point value of any one of them, or a range value between any two.

And/or;

the doping concentration of the P-type impurity used in the second superlattice layer 42 (i.e., the doping concentration of the P-type impurity used in the P-type GaN layer and/or the P-type InN layer in the second superlattice layer) is 5 × 10¹⁸～2×10²⁰atom/cm³Including but not limited to 6 x 10¹⁸atom/cm³、7×10¹⁸atom/cm³、8×10¹⁸atom/cm³、9×10¹⁸atom/cm³、1×10¹⁹atom/cm³、3×10¹⁹atom/cm³、5×10¹⁹atom/cm³、7×10¹⁹atom/cm³、9×10¹⁹atom/cm³、1×10²⁰atom/cm³A point value of any one of them, or a range value between any two.

By setting the doping concentration of the specific P-type impurity and gradually increasing the doping concentration close to the P-type impurity, on one hand, more holes can be provided to make up for the energy loss of the P-type semiconductor layer 5 in the depletion region layer 4; on the other hand, part of electrons can be prevented from passing through the P-type GaN transition layer 43 to reach the P-type semiconductor layer 5 and the highly doped part of the second superlattice layer 42 for non-radiative recombination.

In some specific embodiments of the present invention, the active layer 3 includes InGaN well layers and GaN barrier layers grown in a periodic alternating stack; the depletion region layer 4 is used as the last barrier layer and is arranged on the surface of the InGaN well layer or the GaN barrier layer.

Fig. 3 is a schematic structural diagram of the N-type semiconductor layer 2 according to the present invention. In some specific embodiments of the present invention, the N-type semiconductor layer 2 includes a non-doped GaN layer 202 and/or an N-type GaN layer 203 doped with N-type impurities, which are stacked.

In some specific embodiments of the present invention, the thickness of the N-type semiconductor layer 2 is 1-8 μm, including but not limited to any one or any range of values between 2 μm, 3 μm, 4 μm, 5 μm, 6 μm or 7 μm.

In some specific embodiments of the present invention, the N-type impurity includes Si.

Preferably, the Si source comprises SiH₄。

Preferably, the doping concentration of the N-type impurity is 1 × 10¹⁹～1×10²⁰atom/cm³。

In a specific embodiment of the present invention, the active layer 3 includes a GaN barrier layer and an InGaN well layer which are stacked.

Preferably, the active layer 3 includes a GaN/InGaN superlattice structure in which GaN layers and InGaN layers are alternately grown periodically.

Preferably, the growth period of the active layer 3 is 8 to 15 periods.

Preferably, the thickness of the active layer 3 is 1 to 3 μm, and 2 μm can be selected. The adoption of the thickness range is not only beneficial to ensuring the brightness, but also controls the cost.

In some specific embodiments of the present invention, the thickness of the depletion region layer 4 is 5 to 40nm, including but not limited to any one of 7nm, 9nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, and 38nm or a range therebetween.

And/or;

as shown in fig. 4, the P-type semiconductor layer 5 includes a stacked low-temperature P-type InAlGaN layer 501 and/or a P-type GaN layer 503 doped with P-type impurities.

In some preferred embodiments of the present invention, the thickness of the P-type semiconductor layer 5 is 20 to 260nm, including but not limited to any one of 30nm, 50nm, 60nm, 70nm, 90nm, 100nm, 150nm, 160nm, 180nm, 200nm, 220nm, and 240nm, or any value in a range between any two.

In some preferred embodiments of the present invention, the P-type impurity includes Mg.

Preferably, the Mg source comprises CP₂Mg。

Preferably, the doping concentration of the P-type impurity is 1 × 10¹⁹～1×10²⁰atom/cm³。

In a preferred embodiment of the present invention, as shown in fig. 5, the LED epitaxial wafer further includes a low-temperature GaN buffer layer 201. The low-temperature GaN buffer layer 201 is disposed between the substrate and the undoped GaN layer 202.

In a preferred embodiment of the present invention, as shown in fig. 6, the LED epitaxial wafer further includes an AlGaN electron blocking layer 502, and the AlGaN electron blocking layer 502 is disposed between the low-temperature P-type InAlGaN layer 501 and the P-type GaN layer 503 doped with P-type impurities.

Preferably, the thickness of the AlGaN electron blocking layer 502 is 20 to 30 nm.

and sequentially growing an N-type semiconductor layer 2, an active layer 3, a depletion region layer 4 and a P-type semiconductor layer 5 on the surface of the substrate 1 by adopting an MOCVD method to obtain the LED epitaxial wafer.

Wherein the depletion region layer 4 includes a first superlattice layer 41 and a second superlattice layer 42 sequentially grown on the surface of the active layer.

MOCVD is a new type of vapor phase epitaxy growth technique, which uses organic compounds of III group and II group elements and hydrides of V group and VI group elements as crystal growth source materials, and carries out vapor phase epitaxy on a substrate in a thermal decomposition reaction mode to grow thin layer single crystal materials of various III-V main group and II-VI sub group compound semiconductors and their multiple solid solutions.

According to the invention, the depletion region layer 4 is grown between the active layer 3 and the P-type semiconductor layer 5, so that the energy loss of the depletion region can be reduced, and the luminous efficiency of the GaN white LED is improved.

In a specific embodiment of the present invention, the substrate 1 is a patterned substrate.

Preferably, the material of the patterned substrate comprises at least one of sapphire, AlN, SiC and Si.

In some specific embodiments of the present invention, a P-type GaN transition layer 43 is further included between the first superlattice layer 41 and the second superlattice layer 42.

Preferably, the growth temperature of the P-type GaN transition layer 43 is 800-850 ℃, including but not limited to any one of 810 ℃, 820 ℃, 830 ℃, 840 ℃ or a range between any two.

Preferably, the growth pressure of the P-type GaN transition layer 43 is 200-300 mbar, including but not limited to any one of 210mbar, 230mbar, 250mbar, 270mbar, 290mbar, or any range therebetween.

In some embodiments of the present invention, the growth temperature of the first superlattice layer 41 is 800-850 ℃; including but not limited to, a point value of any one of 810 deg.C, 820 deg.C, 830 deg.C, 840 deg.C, or a range value between any two.

And/or the growth temperature of the second superlattice layer 42 is 850-900 ℃; including but not limited to, a point value of any one of 860 deg.C, 870 deg.C, 880 deg.C, 890 deg.C, or a range value between any two.

Preferably, the growth pressure of the first superlattice layer 41 and/or the second superlattice layer 42 is 200-300 mbar, including but not limited to any one of 210mbar, 230mbar, 250mbar, 270mbar, 290mbar or a range between any two of them.

In some embodiments of the present invention, the carrier gas used in the preparation of the LED epitaxial wafer comprises hydrogen and/or nitrogen.

Preferably, the flow rate of the nitrogen is 0-300L/min, including but not limited to the point value of any one of 50L/min, 100L/min, 150L/min, 200L/min and 250L/min or the range value between any two.

Preferably, the flow rate of the introduced hydrogen is 75-200L/min, including but not limited to any one of 100L/min, 120L/min, 150L/min and 180L/min or any range value between the two.

Preferably, the nitrogen source used in the preparation of the LED epitaxial wafer comprises ammonia gas.

Preferably, the gallium source used in the preparation of the LED epitaxial wafer comprises TMGa (trimethylgallium) and/or TEGa (triethylgallium).

Preferably, the indium source used in the preparation of the LED epitaxial wafer comprises TMIn (trimethylindium) and/or TEIn (triethylindium).

Preferably, the aluminum source used in the preparation of the LED epitaxial wafer comprises TMAl (trimethylaluminum) and/or TEAl (triethylaluminum).

Preferably, in the process of preparing the LED epitaxial wafer, the pressure of the reaction chamber is 130-600 mbar, including but not limited to any one of 150mbar, 200mbar, 250mbar, 300mbar, 350mbar, 400mbar, 450mbar, 500mbar, 550mbar or any range value therebetween.

Preferably, the growth temperature of the N-type semiconductor layer 2 is 500 to 1200 ℃, including but not limited to, the value of any one of 550 ℃, 600 ℃, 650 ℃, 700 ℃, 800 ℃, 900 ℃, 1000 ℃, 1100 ℃, or the range value between any two; the reaction chamber pressure is 200-600 mbar, including but not limited to any one of 250mbar, 300mbar, 350mbar, 400mbar, 450mbar, 500mbar, 550mbar or a range between any two.

Preferably, the flow rate of the hydrogen (carrier gas) during the growth of the N-type semiconductor layer 2 is 150-200L/min, including but not limited to any one of 160L/min, 170L/min, 180L/min and 190L/min or a range therebetween.

Preferably, in the process of growing the N-type GaN layer 203 doped with N-type impurities, the flow rate of the N-type impurities is 30 to 1200sccm, including but not limited to any one of 40sccm, 50sccm, 60sccm, 80sccm, 100sccm, 160sccm, 200sccm, 300sccm, 400sccm, 500sccm, 700sccm, 800sccm, 1000sccm, 1100sccm, or any range therebetween.

In a specific embodiment of the present invention, the growth temperature of the active layer 3 is 750 to 800 ℃, including but not limited to any one of 760 ℃, 770 ℃, 780 ℃ and 790 ℃, or a range between any two thereof; the pressure of the reaction cavity is 200-300 mbar, including but not limited to any one of 210mbar, 230mbar, 250mbar, 270mbar, 280mbar and 290mbar or a range between any two of the above.

Preferably, the flow rate of hydrogen (carrier gas) during the growth of the active layer 3 is 150-200L/min, including but not limited to any one of 160L/min, 170L/min, 180L/min, 190L/min or a range therebetween.

In a specific embodiment of the invention, the growth temperature of the P-type semiconductor layer 5 is 750 to 1050 ℃, including but not limited to any one of 800 ℃, 850 ℃, 900 ℃, 950 ℃, 1000 ℃ and 1030 ℃ or a range between any two of them; the pressure of the reaction chamber is 100-500 mbar, including but not limited to any one of 150mbar, 200mbar, 250mbar, 300mbar, 350mbar, 400mbar, 450mbar or a range between any two.

Preferably, during the growth of the P-type semiconductor layer 5, the flow rate of the hydrogen (as a carrier gas) is 100 to 150L/min, including but not limited to any one of 110L/min, 120L/min, 130L/min and 140L/min or a range value between any two.

Preferably, in the process of growing the P-type semiconductor layer 5, the flow rate of the P-type impurity is 50 to 2500sccm, including but not limited to any one of 80sccm, 100sccm, 150sccm, 200sccm, 250sccm, 300sccm, 400sccm, 500sccm, 600sccm, 800sccm, 1000sccm, 1200sccm, 1400sccm, 1500sccm, 1700sccm, 1900sccm, 2000sccm, 2300sccm, 2400sccm, or any range therebetween.

Preferably, after the N-type semiconductor layer 2, the active layer 3, the depletion region layer 4 and the P-type semiconductor layer 5 are sequentially grown, a cooling step is further included.

The invention also provides an LED chip comprising the LED epitaxial wafer. The LED chip has high internal quantum efficiency and good luminous performance.

Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only illustrative of the present invention and should not be construed as limiting the scope of the present invention. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products commercially available.

Example 1

The LED epitaxial wafer provided in this embodiment is referred to fig. 1, and includes an N-type semiconductor layer (Si-doped N-type GaN layer) 2, an active layer 3(GaN barrier layer and InGaN well layer), a depletion region layer 4, and an N-type semiconductor layer (Mg-doped P-type GaN layer) 5, which are sequentially stacked on a surface of a sapphire substrate 1.

The depletion region layer 4 comprises a first superlattice layer 41 (an AlN layer and a P-type AlGaN layer which alternately grow periodically and have a thickness of 4nm) and a second superlattice layer 42 (a P-type GaN layer and a P-type InN layer which alternately grow periodically and have a thickness of 12nm) which are sequentially stacked;

the preparation method of the LED epitaxial wafer provided in this embodiment adopts an MOCVD method to prepare high-purity H₂As carrier gas, high purity NH₃As N source, TEGa was used as gallium source and TEAl was used as aluminum source.

The preparation method specifically comprises the following steps:

(1) processing a sapphire (AlN-plated) substrate 1, wherein the substrate is a PSS substrate, and an AlN layer is deposited on a PSS pattern: introducing 75-150L/min H at the temperature of 1000-1200 ℃ and the pressure of a reaction cavity of 100-300 mbar₂And treating for 2-5 min under the condition.

(2) Growth of an N-type semiconductor layer (Si-doped N-type GaN layer) 2: h at the temperature of 1000-1200 ℃, the pressure of a reaction cavity of 300-600 mbar and 150-200L/min₂Under the condition, introducing NH of 45000-60000 sccm₃The flow rate of introducing TEGa is 800-1200 sccm and SiH₄The flow rate of the silicon source is 30-80 sccm, and the doping concentration of Si is 1 x 10¹⁹～1×10²⁰atom/cm³And (3) growth under the conditions of (1).

(3) Growing the active layer 3: growing InGaN potential well layer, controlling the pressure of the reaction cavity at 200-300 mbar and the temperature at 750-800 ℃, and introducing NH with the flow rate of 65000-75000 sccm₃The flow rate of introducing TEGa is 400-800 sccm, N₂The flow rate is 50000-70000 sccm. Growing a GaN barrier layer, growing the GaN barrier layer to 850-900 ℃, and growing N₂Flow rate of 30000-50000 sccm, H₂10000-30000 sccm for flow rate, 800-1200 sccm for introducing TEGa, SiH₄The flow rate of the gas is 5-20 sccm, and the number of growth cycles is 8-15.

(4) Growth of depletion region layer 4: adjusting the temperature of the reaction cavity to 800-850 ℃, keeping other conditions unchanged, and growing an AlN/P type AlGaN superlattice structure with a growth period of 2-5 periods, wherein Mg (namely P type impurities used in P type AlGaN) is dopedThe impurity concentration is from 5X 10¹⁷Uniformly increased to 5 × 10¹⁸atom/cm³；

Then, the temperature of the reaction cavity is increased to 850-900 ℃ (other conditions are unchanged), a P-type GaN/P-type InN superlattice structure grows in a growth period of 2-5 periods, wherein the doping concentration of Mg (namely P-type impurities used in the P-type GaN/P-type InN superlattice structure) is 5 multiplied by 10¹⁸atom/cm³Uniformly increased to 2 × 10²⁰atom/cm³。

(5) Growth of P-type semiconductor layer 5 (Mg-doped P-type GaN layer): introducing 50000-70000 sccm NH into the reaction chamber at the temperature of 950-1000 ℃ and the pressure of 200-500 mbar₃TEGa of 1500-2500 sccm, CP of 1000-2000 sccm₂Growing under Mg condition; wherein the Mg doping concentration is 1 × 10¹⁹atom/cm³～1×10²⁰atom/cm³。

(6) And cooling to obtain the LED epitaxial wafer.

Example 2

The LED epitaxial wafer provided in this embodiment is referred to fig. 7, and includes an N-type semiconductor layer 2, an active layer 3, a depletion region layer 4, and a P-type semiconductor layer 5, which are sequentially stacked on a surface of a sapphire substrate 1.

Wherein the N-type semiconductor layer 2 comprises a low-temperature GaN buffer layer 201, an undoped GaN layer 202 and an N-type GaN layer (Si-doped N-type GaN layer) 203 doped with N-type impurities, which are sequentially stacked;

the active layer 3 is a GaN/InGaN superlattice structure layer (GaN and InGaN are periodically and alternately grown);

the depletion region layer 4 comprises a first superlattice layer 41 (AlN layers and P-type AlGaN layers which grow periodically and alternately and have the thickness of 6nm), a P-type GaN transition layer 43 (the thickness of 2nm) and a second superlattice layer 42 (P-type GaN layers and P-type InN layers which grow periodically and alternately and have the thickness of 15nm) which are sequentially stacked;

the P-type semiconductor layer 5 comprises a low-temperature P-type InAlGaN layer (a low-temperature P-type GaN layer doped with In and Al) 501 (the thickness is 40nm), an AlGaN electron blocking layer 502 (the thickness is 25nm) and a P-type GaN layer doped with P-type impurities (a P-type GaN layer doped with Mg) 503 (the thickness is 100nm) which are sequentially stacked.

The preparation method of the LED epitaxial wafer provided in this embodiment adopts an MOCVD method to prepare high-purity H₂As carrier gas, high purity NH₃As N source, organometallic source trimethylgallium (TMGa) as gallium source, TMIn as indium source, TMAl as aluminum source, CP₂Mg as a P-type dopant, SiH₄As an N-type dopant, an N-type semiconductor layer 2, an active layer 3, a depletion region layer 4, and a P-type semiconductor layer 5 are grown in this order on the surface of a substrate 1.

The preparation method specifically comprises the following steps:

(2) Growing a low-temperature GaN buffer layer 201 (low-temperature undoped N-type GaN buffer layer): introducing NH of 15000 to 30000sccm at a temperature of 500 to 800 ℃ and a pressure of 200 to 500mbar in a reaction chamber₃And H of 150-200L/min₂And under the condition, growing a small island on the low-temperature non-doped N-type GaN buffer layer.

(3) Growing the undoped GaN layer 202 (undoped N-type GaN layer): introducing 45000-60000 sccm NH into the reaction chamber at the temperature of 1000-1200 ℃ and the pressure of the reaction chamber of 300-600 mbar₃The flow rate of TMGa is 200-700 sccm, and the flow rate of H is 150-200L/min₂And growing an undoped N-type GaN layer under the condition.

(4) Growing an N-type GaN layer 203 doped with N-type impurities (Si-doped N-type GaN layer), maintaining the pressure, temperature, and H of step (3)₂Under the condition of introducing 45000-70000 sccm NH₃The flow rate of TMGa is 800-1200 sccm and SiH₄The flow rate of the silicon source is 30-80 sccm, and the doping concentration of Si is 1 x 10¹⁹～1×10²⁰atom/cm³。

(5) Growing the active layer 3: the growth of quantum well (InGaN) controls the pressure of reaction cavity at 200-300 mbar, the temperature is 750-800 ℃, NH with flow rate of 65000-75000 sccm is introduced₃，N₂The flow rate is 50000-70000 sccm, and the introduction flow rate of TMGa is 400-800 sccm; raising the temperature to 850-900 ℃ by quantum barrier (GaN) growth, and N₂The flow rate is set to be 30000-50000 sccm, H₂The flow rate is set to 10000-30000 sccm, the flow rate of introducing TMGa is 800-1200 sccm, and SiH₄The flow rate of the gas is 5-20 sccm, and the number of growth cycles is 8-15.

(6) Growing the first superlattice layer 41: adjusting the temperature of the reaction cavity to 800-850 ℃, keeping the other conditions unchanged (same as the step (5)), growing an AlN/P type AlGaN superlattice structure with a growth period of 2-5 periods, wherein the Mg doping concentration is 5 multiplied by 10 within 10-60 s¹⁷atom/cm³Uniformly increased to 5 × 10¹⁸atom/cm³。

(7) Growing the P-type GaN transition layer 43: the reaction chamber conditions were unchanged (same as in step (6)), and the P-type GaN transition layer 43 was grown.

(8) Growing the second superlattice layer 42: raising the temperature of the reaction cavity to 850-900 ℃ (the other conditions are the same as those in the step (7)), growing a P-type GaN/P-type InN layer superlattice structure, wherein the growth period is 2-5 periods, and the Mg doping concentration is 5 multiplied by 10¹⁸atom/cm³Uniformly increased to 2 × 10²⁰atom/cm³。

(9) Growing a low-temperature P-type InAlGaN layer (the P-type impurity is Mg) 501: reducing the temperature to 750-800 ℃, adjusting the pressure of the reaction cavity to 200-300 mbar, and introducing 50000-70000 sccm NH₃1500-2000 sccm of TMGa, 100-150L/min of H₂Obtaining a low-temperature P-type InAlGaN layer under the conditions of 50-150 sccm of TMAl and 500-800 sccm of TMIn; wherein the doping concentration of Mg is 5 multiplied by 10 within 10 to 60s¹⁹atom/cm³Increase to 1 × 10²⁰atom/cm³。

(10) Growing the AlGaN electron blocking layer 502: introducing 50000-70000 sccm of NH into the reaction chamber at the temperature of 950-1050 ℃ and the pressure of the reaction chamber of 100-200 mbar₃800 to 1500sccm of TMGa, 100 to 150L/min of H₂Growing the AlGaN electron blocking layer under the condition of 100-200 sccm of TMAl.

(11) Growing a P-type GaN layer 503 doped with P-type impurities (Mg-doped P-type GaN layer): introducing 50000-70000 sccm NH into the reaction chamber at the temperature of 950-1000 ℃ and the pressure of 200-500 mbar₃1500-2500 sccm of TMGa, 1CP of 000-2000 sccm₂Growing under Mg condition; wherein the Mg doping concentration is 1 × 10¹⁹atom/cm³～1×10²⁰atom/cm³。

(12) And cooling to obtain the LED epitaxial wafer.

Example 3

Referring to fig. 8, the LED epitaxial wafer provided in this embodiment includes an N-type semiconductor layer 2, an active layer 3, a depletion region layer 4, and a P-type semiconductor layer 5, which are sequentially stacked on a surface of a sapphire substrate 1.

Wherein the N-type semiconductor layer 2 comprises a low-temperature GaN buffer layer 201, an undoped GaN layer 202 and an N-type GaN layer (Si-doped N-type GaN layer) 203 (thickness of 3 μm) doped with N-type impurities, which are sequentially stacked;

the active layer 3 is a GaN/InGaN superlattice structure layer, namely an InGaN potential well layer and a GaN barrier layer are alternately grown periodically;

the depletion region layer 4 is the last barrier layer of the active layer 3 and is positioned on the InGaN well layer or the GaN barrier layer. In this embodiment, the depletion region layer 4 is preferably provided on the GaN barrier layer, and includes a first superlattice layer 41 and a second superlattice layer 42 stacked in this order.

The first superlattice layer 41 is 3nm thick and comprises AlN layers and P-type AlGaN layers which alternately grow periodically; the second superlattice layer 42 has a thickness of 10nm and includes P-type GaN layers and P-type InN layers alternately grown periodically.

The P-type semiconductor layer 5 includes a low-temperature P-type InAlGaN layer (a low-temperature P-type GaN layer doped with In and Al) 501, an AlGaN electron blocking layer 502, and a P-type GaN layer doped with P-type impurities (a P-type GaN layer doped with Mg) 503, which are sequentially stacked.

The method for manufacturing the LED epitaxial wafer according to this embodiment is substantially the same as that of embodiment 2, except that step (7) is not included (i.e., the P-type GaN buffer layer 43 is not grown), and the second superlattice layer 42 is grown directly after the first superlattice layer 41 is obtained. Wherein, the flow rate of TMAl is 50-80 sccm when the first superlattice layer 41 is grown.

The potential energy of the first superlattice structure formed by alternately laminating the AlN layer and the P-type AlGaN layer in the depletion region is higher than that of the GaN barrier layer and the low-temperature P-type AlInGaN layer, so that electrons can be blocked more effectively, and the overflow of electrons is reduced. The second superlattice structure is formed by alternately stacking the P-type doped GaN layer and the InN layer, and aims to supplement the loss of the capacity of holes in the depletion region, improve the number of the holes in the active layer and further improve the electron-hole recombination radiation efficiency. In addition, the potential of the AlN layer, the AlGaN layer, the GaN layer and the InN layer which are sequentially arranged in the depletion region is gradually reduced from high to low, so that holes in the P-type layer can easily enter the active layer, the hole concentration in the active layer is improved, and the internal quantum efficiency of the light-emitting diode is improved.

While particular embodiments of the present invention have been illustrated and described, it will be appreciated that the above embodiments are merely illustrative of the technical solution of the present invention and are not restrictive; those of ordinary skill in the art will understand that: modifications may be made to the above-described embodiments, or equivalents may be substituted for some or all of the features thereof without departing from the spirit and scope of the present invention; the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention; it is therefore intended to cover in the appended claims all such alternatives and modifications that are within the scope of the invention.

Claims

1. The LED epitaxial wafer is characterized by comprising an N-type semiconductor layer, an active layer, a depletion region layer and a P-type semiconductor layer which are sequentially stacked on the surface of a substrate;

2. The LED epitaxial wafer according to claim 1, wherein a P-type GaN transition layer is further disposed between the first superlattice layer and the second superlattice layer;

preferably, the thickness of the P-type GaN transition layer is 1-2 nm.

3. The LED epitaxial wafer according to claim 1, wherein the period of the alternating growth of the first superlattice layer is 2-5 periods;

preferably, the thickness of the first superlattice layer is 3-6 nm.

4. The LED epitaxial wafer according to claim 1, wherein the period of the alternate growth of the second superlattice layer is 2-5 periods;

preferably, the thickness of the second superlattice layer is 10-15 nm.

5. The LED epitaxial wafer of claim 1, wherein the doping concentration of the P-type impurity used in the first superlattice layer is 5 x 10¹⁷～5×10¹⁸atom/cm³；

And/or;

6. The LED epitaxial wafer of claim 1, wherein the active layer comprises InGaN well layers and GaN barrier layers grown in a periodic alternating stack; the depletion region layer is the last barrier layer and is arranged on the surface of the InGaN potential well layer or the GaN barrier layer.

7. The LED epitaxial wafer according to any one of claims 1 to 6, wherein the thickness of the depletion region layer is 5 to 40 nm.

8. The method for preparing the LED epitaxial wafer according to any one of claims 1 to 7, comprising the following steps:

9. The method for preparing the LED epitaxial wafer according to claim 8, wherein a P-type GaN transition layer is further included between the first superlattice layer and the second superlattice layer;

10. The method for preparing the LED epitaxial wafer according to claim 8, wherein the growth temperature of the first superlattice layer is 800-850 ℃;

and/or the growth temperature of the second superlattice layer is 850-900 ℃;

11. An LED chip comprising the LED epitaxial wafer as claimed in any one of claims 1 to 7.