CN114325965A - Optical chip and electric chip packaging structure and preparation method thereof - Google Patents
Optical chip and electric chip packaging structure and preparation method thereof Download PDFInfo
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- CN114325965A CN114325965A CN202111626150.XA CN202111626150A CN114325965A CN 114325965 A CN114325965 A CN 114325965A CN 202111626150 A CN202111626150 A CN 202111626150A CN 114325965 A CN114325965 A CN 114325965A
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- 230000003287 optical effect Effects 0.000 title claims abstract description 121
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 56
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 230000008878 coupling Effects 0.000 claims abstract description 63
- 238000010168 coupling process Methods 0.000 claims abstract description 63
- 238000005859 coupling reaction Methods 0.000 claims abstract description 63
- 239000004033 plastic Substances 0.000 claims abstract description 50
- 239000013307 optical fiber Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 18
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- 229910000679 solder Inorganic materials 0.000 claims description 9
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Abstract
An optical chip and electric chip packaging structure and a preparation method thereof are provided, wherein the optical chip and electric chip packaging structure comprises: a first rewiring structure; the optical chip and the electric chip are positioned on one side of the first heavy wiring structure, the optical chip is positioned on the side part of the electric chip, the front surface of the optical chip is provided with a coupling area, the front surface of the optical chip is electrically connected with the first heavy wiring structure through a first conductive connecting piece, the front surface of the electric chip is electrically connected with the first heavy wiring structure through a second conductive connecting piece, and at least part of the coupling area transversely extends outwards relative to the first heavy wiring structure; the supporting piece is positioned between the first heavy wiring structure and part of the optical chip and positioned on the side part of the first conductive connecting piece, and one side of the supporting piece, which is far away from the first conductive connecting piece, is exposed out of at least part of the coupling area; and the plastic packaging layer is positioned on one side of the first rewiring structure and covers the electric chip and part of the optical chip, and the plastic packaging layer is exposed out of the coupling area. The coupling area of the packaging structure of the optical chip and the electric chip can be accurately aligned with the optical fiber.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging structure of an optical chip and an electric chip and a preparation method thereof.
Background
Optical communication is a communication method using light waves as carriers. With the development of technology, the amount of communication data is larger and larger, and thus the transmission rate of the optical communication module is required to be higher and higher. The package structure of the optical chip and the electrical chip is a core component of the optical communication module. One side edge of the optical chip is provided with a coupling area, and the coupling area is used for coupling with the optical fiber, however, in the prior art, the packaging structure of the optical chip and the electrical chip has the problem that the alignment of the optical chip and the optical fiber is not accurate.
Thus, the package structure of the optical chip and the electrical chip in the prior art still needs to be improved.
Disclosure of Invention
The invention aims to solve the technical problem of inaccurate alignment of the optical chip and the electric chip packaging structure and the optical fiber in the prior art.
In order to solve the above technical problem, the present invention provides a package structure of an optical chip and an electrical chip, comprising: a first rewiring structure; the optical chip and the electric chip are positioned on one side of the first redistribution structure, the optical chip is positioned on the side of the electric chip, the front surface of the optical chip is provided with a coupling area, the front surface of the optical chip is electrically connected with the first redistribution structure through a first conductive connecting piece, the front surface of the electric chip is electrically connected with the first redistribution structure through a second conductive connecting piece, and at least part of the coupling area transversely extends outwards relative to the first redistribution structure; a support member located between the first redistribution structure and a portion of the optical chip and located at a side of the first conductive connection member, wherein a side of the support member facing away from the first conductive connection member exposes at least a portion of the coupling region; and the plastic packaging layer is positioned on one side of the first rewiring structure and coats the electric chip and the partial optical chip, and the plastic packaging layer is exposed out of the coupling area.
Optionally, the material of the support comprises a ceramic.
Optionally, the height of the support member is 50 um-80 um.
Optionally, the first redistribution layer structure includes a first dielectric layer and a first redistribution layer located in the first dielectric layer, and the support is in contact with the first dielectric layer; the first conductive connector is in contact with the first redistribution layer and the second conductive connector is in contact with the first redistribution layer.
Optionally, the method further includes: an underfill layer positioned between the optical chip and the first redistribution structure and covering a sidewall of the first conductive connector, the underfill layer also positioned between the electrical chip and the first redistribution structure and covering a sidewall of the second conductive connector; the plastic package layer also covers one side of the underfill layer, which is far away from the first rewiring structure.
Optionally, the support is located on a portion of the surface of the coupling region.
Optionally, the method further includes: and the side wall of the optical fiber is fixed with the side wall of one side of the support member, which is far away from the first conductive connecting piece, and one end face of the optical fiber faces to part of the surface of the coupling area.
Optionally, the method further includes: the conductive column penetrates through the plastic packaging layer on the side part of the electric chip and is electrically connected with the first rewiring structure; the second rewiring structure is positioned on one side, away from the first rewiring structure, of the plastic packaging layer, and the second rewiring structure is electrically connected with the conductive columns; and the solder balls are positioned on the surface of the first heavy wiring structure.
The invention also provides a preparation method of the packaging structure of the optical chip and the electric chip, which comprises the following steps: forming a first rewiring structure; arranging an initial support member on one side of part of the first heavy wiring structure; providing an electric chip and an initial optical chip, wherein the front surface of the initial optical chip is provided with a coupling area, the electric chip and the initial optical chip are attached to one side of the first re-wiring structure, the front surface of the initial optical chip is electrically connected with the first re-wiring structure through a first conductive connecting piece, and the front surface of the electric chip is electrically connected with the first re-wiring structure through a second conductive connecting piece; the initial support is positioned between the first heavy wiring structure and part of the initial optical chip and positioned at the side part of the first conductive connecting piece, and the initial support surrounds at least part of the coupling region; forming a plastic packaging layer on one side of the first rewiring structure, wherein the plastic packaging layer wraps the electric chip and part of the initial optical chip; the initial support isolates the plastic packaging layer from the coupling region surrounded by the initial support; scribing and cutting the plastic packaging layer, the initial optical chip and the initial support piece to enable the initial optical chip to form an optical chip and enable the initial support piece to form a support piece, wherein one side of the support piece, which is far away from the first conductive connecting piece, is exposed out of at least part of the coupling area; after the dicing cut, removing a portion of the first redistribution structure such that at least a portion of the coupling region extends laterally outward relative to the first redistribution structure.
Optionally, the method further includes: before forming the plastic package layer, forming an underfill layer between the initial optical chip and the first redistribution structure and between the electrical chip and the first redistribution structure, the underfill layer coating sidewalls of the first conductive connector and sidewalls of the second conductive connector; after the plastic packaging layer is formed, the plastic packaging layer also covers the bottom filling layer.
Optionally, the method further includes: forming a conductive pillar on one side of the first redistribution structure, the conductive pillar being electrically connected to the first redistribution structure, the conductive pillar being located on a side of the electrical chip; after the plastic packaging layer is formed, the conductive posts penetrate through the plastic packaging layer; thinning one side of the plastic packaging layer, which is far away from the first rewiring structure, until the conductive columns are exposed out of the plastic packaging layer; after thinning one side of the plastic packaging layer, which is far away from the first rewiring structure, a second rewiring structure is formed on one side of the plastic packaging layer, which is far away from the first rewiring structure, and the second rewiring structure is electrically connected with the conductive columns; and arranging solder balls on the surface of the first heavy wiring structure.
The technical scheme of the invention has the following advantages:
in the optical chip and electrical chip package structure provided by the technical scheme of the invention, the front surface of the optical chip is provided with the coupling region, at least part of the coupling region extends outwards in a transverse direction relative to the first redistribution structure, and because part of the coupling region extends outwards in a transverse direction relative to the first redistribution structure, at least part of the coupling region is exposed out of one side of the support member, which is far away from the first conductive connecting member, so that the optical fiber can be directly aligned to the part of the coupling region extending outwards in a transverse direction relative to the first redistribution structure on the side wall of the support member.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a package structure of an optical chip and an electrical chip according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for fabricating a package structure for an optical chip and an electrical chip according to an embodiment of the present invention;
fig. 3 to 10 are schematic structural diagrams illustrating a manufacturing process of a package structure of an optical chip and an electrical chip according to an embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The present invention provides a package structure of an optical chip and an electrical chip, referring to fig. 1, including:
a first rewiring structure 1;
the optical chip 2 and the electric chip 3 are positioned on one side of the first redistribution structure 1, the optical chip 2 is positioned on the side of the electric chip 3, the front surface of the optical chip 2 is provided with a coupling region 4, the front surface of the optical chip 2 is electrically connected with the first redistribution structure 1 through a first conductive connecting piece 5, the front surface of the electric chip 3 is electrically connected with the first redistribution structure 1 through a second conductive connecting piece 6, and at least part of the coupling region 4 transversely extends outwards relative to the first redistribution structure 1;
a support 7 located between the first redistribution structure 1 and a portion of the optical chip 2 and located at a side of the first conductive connector 5, wherein a side of the support 7 facing away from the first conductive connector 5 exposes at least a portion of the coupling region 4;
and the plastic packaging layer 8 is positioned on one side of the first rewiring structure 1 and coats the electric chip 3 and the partial optical chip 2, and the plastic packaging layer 8 is exposed out of the coupling area 4.
In this embodiment, the front surface of the optical chip has a coupling region 4, at least a portion of the coupling region 4 extends laterally outward relative to the first redistribution layer structure 1, and because a portion of the coupling region 4 extends laterally outward relative to the first redistribution layer structure 1, and at least a portion of the coupling region 4 is exposed on a side of the support 7 away from the first conductive connection element 5, an optical fiber can be aligned directly on a side wall of the support 7 with respect to the portion of the coupling region 4 extending laterally outward relative to the first redistribution layer structure 1.
In one embodiment, the first rewiring structure 1 includes a first dielectric layer and a first rewiring layer located in the first dielectric layer, and the support 7 is in contact with the first dielectric layer; the first conductive connecting member 5 is in contact with the first rewired layer, and the second conductive connecting member 6 is in contact with the first rewired layer.
In one embodiment, the material of the support 7 comprises ceramic; in other embodiments, the material of the supporting member 7 may also be other insulating materials that can play a supporting role.
In one embodiment, the support 7 has a height of 50 um-80 um, such as 60 um; if the height of the supporting member 7 is less than 50um, the space formed above the optical chip 2 and the electrical chip 3 for accommodating the first conductive connecting member 5 and the second conductive connecting member 6 is too small, and the positioning effect of the supporting member 7 on the optical fiber is weakened; if the height of the supporting member 7 is greater than 80um, the surface of the finally formed packaging structure of the optical chip and the electric chip is uneven, and the volume of the finally formed packaging structure of the optical chip and the electric chip is too large.
In one embodiment, the supporting element 7 is located on a portion of the surface of the coupling region 4, the supporting element 7 extends a portion of the coupling region 4 laterally outward relative to the first redistribution structure 1, and the optical fiber can be aligned directly on a sidewall of the supporting element 7 at a portion of the coupling region 4 extending laterally outward relative to the first redistribution structure 1, while the supporting element 7 also supports the first redistribution structure 1.
In one embodiment, the package structure of the optical chip and the electrical chip further includes: and the bottom filling layer 9, the bottom filling layer 9 is positioned between the optical chip 2 and the first heavy wiring structure 1 and coats the side wall of the first conductive connecting piece 5, and the bottom filling layer 9 is also positioned between the electric chip 3 and the first heavy wiring structure 1 and coats the side wall of the second conductive connecting piece 6.
In one embodiment, the material of the underfill layer 9 comprises epoxy.
In one embodiment, the molding layer 8 also covers a side of the underfill layer 9 facing away from the first redistribution structure 1.
In this embodiment, the package structure of the optical chip and the electrical chip further includes: an optical fiber 10, the side wall of the optical fiber 10 being fixed to the side wall of the support 7 on the side facing away from the first conductive connector 5, an end face of the optical fiber 10 facing a portion of the surface of the coupling region 4. In this embodiment, the package structure of the optical chip and the electrical chip further includes: and the conductive column 11 penetrates through the plastic packaging layer 8 at the side part of the electric chip 3 and is electrically connected with the first rewiring structure 1.
In this embodiment, the package structure of the optical chip and the electrical chip further includes: and the second redistribution structure 12 is positioned on one side of the plastic package layer 8, which is far away from the first redistribution structure 1, and the second redistribution structure 12 is electrically connected with the conductive column 11.
In this embodiment, the package structure of the optical chip and the electrical chip further includes: and the solder balls 13, wherein the solder balls 13 are positioned on the surface of the first heavy wiring structure 1.
According to the packaging structure of the optical chip and the electric chip, the front surface of the optical chip 2 is electrically connected with the first re-wiring structure 1 through the first conductive connecting piece 5, the front surface of the electric chip 3 is electrically connected with the first re-wiring structure 1 through the second conductive connecting piece 6, the optical chip 2 and the electric chip 3 realize fan-out through the first re-wiring structure 1, the first re-wiring structure 1 is provided with a plurality of input ports and output ports, the number of the input ports and the output ports is large, and the communication density of the packaging structure of the optical chip and the electric chip is improved.
In this embodiment, the optical chip 2 includes a dielectric layer and an optical structure located in the dielectric layer, the optical structure includes a waveguide structure, the coupling region 4 includes the waveguide structure, and the optical chip does not have a base substrate. Compared with the scheme that the optical chip adopts the base substrate in the prior art, the cost is reduced.
Another embodiment of the present invention further provides a method for manufacturing a package structure of an optical chip and an electrical chip, referring to fig. 2, including the following steps:
step S1: forming a first rewiring structure;
step S2: arranging an initial support member on one side of part of the first heavy wiring structure;
step S3: providing an electric chip and an initial optical chip, wherein the front surface of the initial optical chip is provided with a coupling area, the electric chip and the initial optical chip are attached to one side of the first re-wiring structure, the front surface of the initial optical chip is electrically connected with the first re-wiring structure through a first conductive connecting piece, and the front surface of the electric chip is electrically connected with the first re-wiring structure through a second conductive connecting piece; the initial support is positioned between the first heavy wiring structure and part of the initial optical chip and positioned at the side part of the first conductive connecting piece, and the initial support surrounds at least part of the coupling region;
step S4: forming a plastic packaging layer on one side of the first rewiring structure, wherein the plastic packaging layer wraps the electric chip and part of the initial optical chip; the initial support isolates the plastic packaging layer from the coupling region surrounded by the initial support;
step S5: scribing and cutting the plastic packaging layer, the initial optical chip and the initial support piece to enable the initial optical chip to form an optical chip and enable the initial support piece to form a support piece, wherein one side of the support piece, which is far away from the first conductive connecting piece, is exposed out of at least part of the coupling area;
step S6: after the dicing cut, removing a portion of the first redistribution structure such that at least a portion of the coupling region extends laterally outward relative to the first redistribution structure.
In step S1, specifically, referring to fig. 3, the first redistribution layer structure 1 includes a first dielectric layer and a first redistribution layer located in the first dielectric layer.
In one embodiment, the process of forming the first rewiring structure 1 includes: photolithography, electroplating, and etching processes.
In one embodiment, the material of the first dielectric layer comprises photoresist.
In one embodiment, the material of the first redistribution layer is a metal, such as copper.
In one embodiment, with continued reference to fig. 3, before forming the first rewiring structure 1, further comprising: providing a substrate layer 14, wherein the material of the substrate layer 14 comprises glass, then forming a bonding layer 15 on the substrate layer 14, and after forming the bonding layer 15, forming the first rewiring structure 1 on a side of the bonding layer 15 facing away from the substrate layer 14.
In step S2, referring to fig. 4, an initial support 701 is provided at one side of a portion of the first rewiring structure 1. Specifically, an initial support 701 is disposed on a side of a portion of the first rewiring structure 1 facing away from the bonding layer 15.
In one embodiment, the structure of the initial support 701 is a ring structure, and may specifically be a ring structure or a rectangular ring structure, and may also be a ring structure of another shape.
In one embodiment, the material of the initial support 701 comprises a ceramic; in other embodiments, the material of the initial support 701 may also be other insulating materials that can serve as a support.
In step S3, specifically, referring to fig. 5, an electric chip 3 and an initial optical chip 201 are provided, the front surface of the initial optical chip 201 has a coupling area 4, the electric chip 3 and the initial optical chip 201 are attached to one side of the first redistribution structure 1, the front surface of the initial optical chip 201 is electrically connected to the first redistribution structure 1 through a first conductive connection element 5, and the front surface of the electric chip 3 is electrically connected to the first redistribution structure 1 through a second conductive connection element 6; the initial support 701 is located between the first redistribution structure 1 and a portion of the initial optical chip 201 and at a side of the first conductive connection element 5, and the initial support 701 surrounds at least a portion of the coupling region 4.
In one embodiment, with continued reference to fig. 5, the method for manufacturing the package structure of the optical chip and the electrical chip further includes: and forming a conductive column 11 positioned at the side part of the electric chip 3 at one side of the first redistribution structure 1, wherein the conductive column 11 is electrically connected with the first redistribution structure 1.
In one embodiment, the process of forming the conductive pillars 11 includes electroplating.
In one embodiment, the material of the conductive post 11 is a metal, such as copper.
In step S4, specifically, referring to fig. 6, a molding layer 8 is formed on one side of the first redistribution structure 1, and the molding layer 8 covers the electrical chip 3 and a part of the initial optical chip 201; the initial support 701 isolates the molding layer 8 from the coupling region 4 surrounded by the initial support.
In one embodiment, the material of the molding layer 8 includes an epoxy resin and additives including hardeners, fillers, flame retardants, and the like.
In one embodiment, with continued reference to fig. 6, before forming the molding layer 8, an underfill layer 9 is formed between the initial optical chip 201 and the first redistribution structure 1 and between the electrical chip 3 and the first redistribution structure 1, and the underfill layer 9 covers the sidewalls of the first conductive connection element 5 and the sidewalls of the second conductive connection element 6.
In one embodiment, the material of the underfill layer 9 comprises epoxy.
In one embodiment, after the molding layer 8 is formed, the molding layer 8 also covers a side of the underfill layer 9 facing away from the first redistribution structure; after the molding layer 8 is formed, the conductive posts 11 penetrate through the molding layer 8.
Referring to fig. 7, the method for manufacturing the package structure of the optical chip and the electrical chip further includes: it is right the plastic envelope layer 8 deviates from one side of first rewiring structure 1 carries out the attenuate, until the plastic envelope layer 8 exposes it leads electrical pillar 11.
Referring to fig. 8, the method for manufacturing the package structure of the optical chip and the electrical chip further includes: it is right the plastic envelope 8 deviates from after the attenuate is carried out to one side of first rewiring structure 1 the plastic envelope 8 deviates from first rewiring structure 1 one side forms second rewiring structure 12, second rewiring structure 12 with it is connected to lead electrical pillar 11.
In one embodiment, referring to fig. 9, solder balls 13 are disposed on the surface of the first redistribution structure 1.
Specifically, after the second rewiring structure 12 is formed, the first rewiring structure 1 and the bonding layer 15 are unbonded, and after the first rewiring structure 1 and the bonding layer 15 are unbonded, the solder balls 13 are disposed on the surface of the first rewiring structure 1.
In one embodiment, the solder balls 13 are used to make interconnections to a circuit board.
In step S5, specifically, with reference to fig. 9, the molding layer 8, the initial optical chip 201, and the initial supporting member 701 are diced to form the initial optical chip 201 as the optical chip 2 and the initial supporting member 701 as the supporting member 7, where a side of the supporting member 7 facing away from the first conductive connecting member 5 exposes at least a portion of the coupling region 4.
In this embodiment, the scribing and cutting process includes laser cutting, and the first dielectric layer can be ablated to the side wall of the support 7 by controlling the energy intensity and the energy range of the laser.
In step S6, specifically, referring to fig. 10, after the dicing cut, a portion of the first rewiring structure 1 is removed, so that at least a portion of the coupling region 4 extends laterally outward with respect to the first rewiring structure 1.
In one embodiment, the side wall of the optical fiber 10 is fixed to the side wall of the support 7 on the side facing away from the first conductive connector 5, and the end surface of the optical fiber 10 faces a portion of the surface of the coupling region 4, so that the optical fiber 10 and the coupling region 4 can be precisely aligned due to at least a portion of the coupling region 4 extending laterally outward relative to the first redistribution structure 1.
In the scheme, the structure of the initial support member 701 is an annular structure, and after scribing and cutting are adopted, part of the coupling region 4 can be directly exposed, so that the process is simplified, and the preparation method of the packaging structure of the optical chip and the electric chip is low in cost.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (11)
1. An optical chip and electrical chip package comprising:
a first rewiring structure;
the optical chip and the electric chip are positioned on one side of the first redistribution structure, the optical chip is positioned on the side of the electric chip, the front surface of the optical chip is provided with a coupling area, the front surface of the optical chip is electrically connected with the first redistribution structure through a first conductive connecting piece, the front surface of the electric chip is electrically connected with the first redistribution structure through a second conductive connecting piece, and at least part of the coupling area transversely extends outwards relative to the first redistribution structure;
a support member located between the first redistribution structure and a portion of the optical chip and located at a side of the first conductive connection member, wherein a side of the support member facing away from the first conductive connection member exposes at least a portion of the coupling region;
and the plastic packaging layer is positioned on one side of the first rewiring structure and coats the electric chip and the partial optical chip, and the plastic packaging layer is exposed out of the coupling area.
2. The optical and electrical chip package of claim 1, wherein the material of the support comprises a ceramic.
3. The package structure of the optical and electrical chips of claim 1, wherein the support member has a height of 50 um-80 um.
4. The optical and electrical chip package structure of claim 1, wherein the first rewiring structure includes a first dielectric layer and a first rewiring layer in the first dielectric layer, the support being in contact with the first dielectric layer; the first conductive connector is in contact with the first redistribution layer and the second conductive connector is in contact with the first redistribution layer.
5. The optical and electrical chip package structure of claim 1, further comprising: an underfill layer positioned between the optical chip and the first redistribution structure and covering a sidewall of the first conductive connector, the underfill layer also positioned between the electrical chip and the first redistribution structure and covering a sidewall of the second conductive connector;
the plastic package layer also covers one side of the underfill layer, which is far away from the first rewiring structure.
6. The optical and electrical chip package of claim 1, wherein the support is located at a portion of the surface of the coupling region.
7. The optical and electrical chip package structure of claim 1 or 6, further comprising: and the side wall of the optical fiber is fixed with the side wall of one side of the support member, which is far away from the first conductive connecting piece, and one end face of the optical fiber faces to part of the surface of the coupling area.
8. The optical and electrical chip package structure of claim 1, further comprising: the conductive column penetrates through the plastic packaging layer on the side part of the electric chip and is electrically connected with the first rewiring structure; the second rewiring structure is positioned on one side, away from the first rewiring structure, of the plastic packaging layer, and the second rewiring structure is electrically connected with the conductive columns;
and the solder balls are positioned on the surface of the first heavy wiring structure.
9. A method for manufacturing a package structure of an optical chip and an electrical chip, comprising:
forming a first rewiring structure;
arranging an initial support member on one side of part of the first heavy wiring structure;
providing an electric chip and an initial optical chip, wherein the front surface of the initial optical chip is provided with a coupling area, the electric chip and the initial optical chip are attached to one side of the first re-wiring structure, the front surface of the initial optical chip is electrically connected with the first re-wiring structure through a first conductive connecting piece, and the front surface of the electric chip is electrically connected with the first re-wiring structure through a second conductive connecting piece; the initial support is positioned between the first heavy wiring structure and part of the initial optical chip and positioned at the side part of the first conductive connecting piece, and the initial support surrounds at least part of the coupling region;
forming a plastic packaging layer on one side of the first rewiring structure, wherein the plastic packaging layer wraps the electric chip and part of the initial optical chip; the initial support isolates the plastic packaging layer from the coupling region surrounded by the initial support;
scribing and cutting the plastic packaging layer, the initial optical chip and the initial support piece to enable the initial optical chip to form an optical chip and enable the initial support piece to form a support piece, wherein one side of the support piece, which is far away from the first conductive connecting piece, is exposed out of at least part of the coupling area;
after the dicing cut, removing a portion of the first redistribution structure such that at least a portion of the coupling region extends laterally outward relative to the first redistribution structure.
10. The method of claim 9, further comprising:
before forming the plastic package layer, forming an underfill layer between the initial optical chip and the first redistribution structure and between the electrical chip and the first redistribution structure, the underfill layer coating sidewalls of the first conductive connector and sidewalls of the second conductive connector;
after the plastic packaging layer is formed, the plastic packaging layer also covers one side, away from the first rewiring structure, of the underfill layer.
11. The method of claim 9, further comprising: forming a conductive pillar on one side of the first redistribution structure, the conductive pillar being electrically connected to the first redistribution structure, the conductive pillar being located on a side of the electrical chip; after the plastic packaging layer is formed, the conductive posts penetrate through the plastic packaging layer; thinning one side of the plastic packaging layer, which is far away from the first rewiring structure, until the conductive columns are exposed out of the plastic packaging layer; after thinning one side of the plastic packaging layer, which is far away from the first rewiring structure, a second rewiring structure is formed on one side of the plastic packaging layer, which is far away from the first rewiring structure, and the second rewiring structure is electrically connected with the conductive columns; and arranging solder balls on the surface of the first heavy wiring structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN116165753A (en) * | 2023-04-14 | 2023-05-26 | 之江实验室 | Optical chip, chip packaging structure and packaging performance detection method |
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