CN114256810B - Battery protection control circuit and related chip - Google Patents
Battery protection control circuit and related chip Download PDFInfo
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- CN114256810B CN114256810B CN202110266234.0A CN202110266234A CN114256810B CN 114256810 B CN114256810 B CN 114256810B CN 202110266234 A CN202110266234 A CN 202110266234A CN 114256810 B CN114256810 B CN 114256810B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/18—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for batteries; for accumulators
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
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Abstract
The application discloses a battery protection control circuit and a related chip, wherein the battery protection control circuit comprises a VDD port, GND, R1, a cascading MOS tube module, N1, N2 and R2, a preset protection circuit, an MCU, a CO port, a DO port and a VM port; the VDD port is connected with the first end of the R1, the second end of the R1 is connected with the cascade MOS tube module, the cascade MOS tube module is connected with the grid electrode of the N1, the grid electrode of the N2 and the first end of the R3, and the source electrode of the N1, the second end of the R3 and the source electrode and the drain electrode of the N2 are grounded; the second end of R1 is used as a VDDA port and is also connected with a preset protection circuit and an MCU, and the MCU is connected with a CO port, a DO port and a VM port. The battery protection control circuit provided by the application is beneficial to avoiding the burning of the battery protection circuit in the battery circuit due to overlarge voltage.
Description
Technical Field
The present application relates to battery chips, and particularly to a battery protection control circuit, a battery protection control chip, and an electronic device.
Background
Currently, lithium batteries are widely used in various portable devices such as mobile phones, video cameras, notebook computers, electric tools, remote controls, or electric toys, etc., with their excellent characteristics.
The lithium battery can be repeatedly used after being charged, and the charging equipment is usually used for taking electricity from the power grid to charge the lithium battery, but the voltage of the electricity taken from the power grid is far greater than the working voltage of the lithium battery, so that the charging equipment is required to be used for reducing the voltage to the working voltage of the lithium battery so as to charge the lithium battery. However, since the grid voltage may vary greatly in an instant, the charging device cannot reduce the instant voltage to the operating voltage of the lithium battery, resulting in burning the protection circuit of the lithium battery. Or during the discharging process of the lithium battery, the output voltage is unstable during the discharging process, so that the lithium battery protection circuit is easy to burn when the voltage is higher than a preset value.
Disclosure of Invention
The application provides a battery protection control circuit, a chip and an electronic device, so as to prevent the battery protection circuit in the battery circuit from being burnt out due to overlarge voltage.
In a first aspect, an embodiment of the present application provides a battery protection control circuit, including a positive voltage VDD port, a ground port GND, a first resistor R1, a cascaded MOS transistor module, a first NMOS transistor N1, a second NMOS transistor N2, a second resistor R2, a preset protection circuit, a micro control unit MCU, a charge protection CO port, a discharge protection DO port, and a voltage control VM port;
The positive voltage VDD port is connected with the first end of the resistor R1, the second end of the resistor R1 is connected with the cascade MOS tube module, the cascade MOS tube module is connected with the grid electrode of the first NMOS tube N1, the grid electrode of the second NMOS tube N2 and the first end of the resistor R2, and the source electrode of the first NMOS tube N1, the second end of the second resistor R2 and the source electrode and the drain electrode of the second NMOS tube N2 are all grounded;
The second end of the resistor R1 is used as an internal power supply VDDA port and is also connected with the preset protection circuit and the MCU, and the MCU is connected with the charging protection CO port, the discharging protection DO port and the voltage control VM port;
the positive voltage VDD port is used for being connected with a preset device through an EB+ port after being combined with the positive electrode of a battery, the preset device comprises a charger or a preset load, the ground port GND is used for being connected with the negative electrode of the battery, the charging protection CO port is used for being connected with the grid electrode of a third NMOS tube N3, the discharging protection DO port is used for being connected with the grid electrode N4 of a fourth NMOS tube, the voltage control VM port is used for being connected with the first end of a third resistor R3, the second end of the third resistor R3 is connected with the source electrode of the third NMOS tube N3 and the positive electrode of a first diode D1 through the EB-port after being combined, the drain electrode of the third NMOS tube N3 and the negative electrode of the first diode D1 are connected with the drain electrode of the fourth NMOS tube N4 and the negative electrode of a second diode D2 after being combined, and the source electrode of the fourth NMOS tube N4 and the positive electrode of the second diode D2 are connected with the negative electrode of the battery.
In a second aspect, an embodiment of the present application provides a battery protection control chip, where the battery protection control chip includes the battery protection control circuit according to the first aspect.
In a third aspect, an embodiment of the present application provides an electronic device, including a battery protection control chip as described in the first aspect.
In the battery protection control circuit provided by the application, the resistor R1, the cascade MOS tube module, the first NMOS tube N1, the second NMOS tube N2 and the second resistor R2 form the clamp circuit for protecting the preset protection circuit at the rear end of the internal supply VDDA port, when the positive voltage VDD port is in a normal voltage state, the first NMOS tube N1 and the second NMOS tube N2 are not conducted, the circuit works normally, when the positive voltage VDD port voltage is in an abnormally increased state, the voltage VDDA of the internal supply VDDA port is increased, the first NMOS tube N1 is conducted, the gate source voltage VGSN of the N1 is increased, the conducting current I2 of the N1 is increased, the voltage drop VR1 on the first resistor R1 is increased due to the increase of the combined current (I2 + the internal supply VDDA port rear end load circuit I1), the VR1 is increased to promote the reduction of the VDDA, and finally the clamp control of the VDDA is completed, so that the battery protection circuit in the battery circuit is prevented from being burnt due to overlarge voltage.
Drawings
Fig. 1 is a schematic diagram of a circuit composition of a battery protection control circuit according to the present application;
FIG. 2 is a schematic diagram of a preset protection circuit according to the present application;
FIG. 3 is a schematic diagram of an overvoltage protection circuit according to the present application;
FIG. 4 is a schematic diagram of an under-voltage protection circuit according to the present application;
FIG. 5 is a schematic diagram of an over-temperature protection circuit according to the present application;
FIG. 6 is a schematic diagram of an over-discharge current protection circuit according to the present application;
fig. 7 is a schematic diagram of the composition of an overcharge current protection circuit provided by the application;
Fig. 8 is a schematic diagram of circuit composition of a cascaded MOS transistor module provided by the present application;
fig. 9 is a schematic circuit diagram of another cascaded MOS transistor module according to the present application;
Fig. 10 is a schematic diagram of a circuit composition of a battery protection control chip according to the present application;
Fig. 11 is a schematic diagram of an electronic device according to the present application.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It is noted that the terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
As shown in fig. 1, the embodiment of the application provides a battery protection control circuit, which comprises a positive voltage VDD port, a ground port GND, a first resistor R1, a cascaded field effect transistor MOS transistor module, a first NMOS transistor N1, a second NMOS transistor N2, a second resistor R2, a preset protection circuit, a micro control unit MCU, a charge protection CO port, a discharge protection DO port, and a voltage control VM port;
The positive voltage VDD port is connected with the first end of the resistor R1, the second end of the resistor R1 is connected with the cascade MOS tube module, the cascade MOS tube module is connected with the grid electrode of the first NMOS tube N1, the grid electrode of the second NMOS tube N2 and the first end of the resistor R2, and the source electrode of the first NMOS tube N1, the second end of the second resistor R2 and the source electrode and the drain electrode of the second NMOS tube N2 are all grounded;
The second end of the resistor R1 is used as an internal power supply VDDA port and is also connected with the preset protection circuit and the MCU, and the MCU is connected with the charging protection CO port, the discharging protection DO port and the voltage control VM port;
The positive voltage VDD port is used for being connected with an EB+ port of a preset device after being combined with the positive electrode of a battery, the preset device comprises a charger or a preset load, the ground port GND is used for being connected with the negative electrode of the battery, the charging protection CO port is used for being connected with the grid electrode of a third NMOS tube N3, the discharging protection DO port is used for being connected with the grid electrode N4 of a fourth NMOS tube, the voltage control VM port is used for being connected with the first end of a third resistor R3, the second end of the third resistor R3 is connected with the source electrode of the third NMOS tube N3 and the positive electrode of a first diode D1 after being combined, the drain electrode of the third NMOS tube N3 and the negative electrode of the first diode D1 are connected with the drain electrode of the fourth NMOS tube N4 and the negative electrode of a second diode D2 after being combined, and the source electrode of the fourth NMOS tube N4 and the positive electrode of the second diode D2 are connected with the negative electrode of the battery.
The charger may be an on-vehicle charger in a vehicle battery system, such as a direct current-to-direct current DC/DC lithium battery charger, and the preset load may be an in-vehicle load, such as a sound box.
The second NMOS transistor N2 is used as a MOS capacitor, and is mainly used for filtering, so as to avoid misleading the first NMOS transistor N1 due to voltage glitches.
Wherein, the resistance of R2 is larger than a preset resistance, such as 10 Kohm. The resistance value of R2 is set to be large enough to enable the leakage power consumption of the voltage-resistant resistor R1 to be small, and the energy consumption waste is reduced.
In this possible example, as shown in fig. 2, the preset protection circuit includes at least one of the following: an overvoltage protection circuit, an undervoltage protection circuit, an over-temperature protection circuit, an over-discharge current protection circuit and an over-charge current protection circuit.
The overvoltage protection circuit and the overcharge current protection circuit are used for protecting the preset protection circuit at the rear end of the internal power supply VDDA port in a charging state of the battery (namely, when the preset device is a charger), the overtemperature protection circuit is used for protecting the temperature state of the preset protection circuit at the rear end of the internal power supply VDDA port in a charging state or a discharging state of the battery, and the undervoltage protection circuit and the overdischarge current protection circuit are used for protecting the preset protection circuit at the rear end of the internal power supply VDDA port in a discharging state.
In this possible example, as shown in fig. 3, the overvoltage protection circuit includes a fifth resistor R5, a sixth resistor R6, and a first voltage comparator Av1; the positive voltage VDD port is connected to the first end of the fifth resistor R5, the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the positive electrode port of the first voltage comparator Av1, the second end of the sixth resistor R6 is connected to the ground port GND, and the internal reference voltage port (shown as Vref 1) and the output port of the first voltage comparator Av1 are connected to the MCU; the MCU is used for closing the third NMOS tube N3 of the charging protection CO port when the overvoltage protection circuit detects an overvoltage state.
As shown in fig. 4, the under-voltage protection circuit includes a seventh resistor R7, an eighth resistor R8, and a second voltage comparator Av2; the positive voltage VDD port is connected to the first end of the seventh resistor R7, the second end of the seventh resistor R7 is connected to the first end of the eighth resistor R8 and the positive port of the second voltage comparator Av2, the second end of the eighth resistor R8 is connected to the ground port GND, and the internal reference voltage port (shown as Vref 2) and the output port of the second voltage comparator Av2 are connected to the MCU; the MCU is used for closing the fourth NMOS tube N4 of the discharge protection DO port when the undervoltage protection circuit detects an undervoltage state.
As shown in fig. 5, the over-temperature protection circuit includes a current source, a triode and a third voltage comparator Av3; the positive electrode of the current source is connected with the positive voltage VDD port, the negative electrode of the current source is connected with the emitter of the triode and the positive electrode port of the third voltage comparator Av3, the base electrode and the collector electrode of the triode are both connected with the grounding port GND, and the internal reference voltage port (shown as Vref 3) and the output port of the first voltage comparator Av1 are connected with the MCU; the MCU is used for closing the third NMOS tube N3 of the charging protection CO port when the over-temperature protection circuit detects that the charging is in an over-temperature state, and closing the fourth NMOS tube N4 of the discharging protection DO port when the over-temperature protection circuit detects that the discharging is in an over-temperature state.
As shown in fig. 6, the over-discharge current protection circuit includes a ninth resistor R9 and a second current comparator Ai2, wherein the positive voltage VDD port is connected to the positive port of the second current comparator Ai2, the negative port of the second current comparator Ai2 is connected in series with the ninth resistor R9 and then is connected to the ground port GND, and the output port of the second current comparator Ai2 is connected to the MCU; the MCU is used for closing the fourth NMOS tube N4 of the discharge protection DO port when the discharge overcurrent state is detected through the overdischarge current protection circuit.
As shown in fig. 7, the overcharge current protection circuit includes a tenth resistor R10 and a third current comparator, where an anode of the third current comparator is connected to the ground port GND, a cathode of the third current comparator is connected in series with the tenth resistor R10 and then connected to the voltage control VM port, and an output port of the third current comparator is connected to the MCU; the MCU is used for closing the third NMOS tube N3 of the discharge protection CO port when the discharge overcurrent state is detected through the overcharge current protection circuit.
In the battery protection control circuit provided by the application, the resistor R1, the cascaded field effect transistor MOS transistor module, the first NMOS transistor N1, the second NMOS transistor N2 and the second resistor R2 form the clamp circuit for protecting the preset protection circuit at the rear end of the internal supply VDDA port, when the positive voltage VDD port is in a normal voltage state, the first NMOS transistor N1 and the second NMOS transistor N2 are not conducted, the circuit normally works, when the positive voltage VDD port is in an abnormally increased state, the voltage VDDA of the internal supply VDDA port is increased, the first NMOS transistor N1 is conducted, the gate-source voltage VGSN of the N1 is increased, the conducting current I2 of the N1 is increased, the voltage drop VR1 on the first resistor R1 is increased due to the increase of the combined current (I < 2+ > internal supply VDDA port rear end load circuit I1), the VR1 is increased to promote the decrease of the VDDA, and finally the control of the VDDA is finished, so that the battery protection circuit in the battery protection circuit is prevented from being burnt due to overlarge voltage.
In this possible example, if the preset device is the charger, the MCU is configured to turn on the third NMOS transistor N3 through the charging protection CO port in a normal charging state to achieve charging, and turn off the third NMOS transistor N3 through the charging protection CO port in an overcharging state or an overtemperature state to achieve stopping charging;
If the preset device is the load, the MCU is configured to conduct the fourth NMOS N4 through the discharge protection DO port in a normal discharge state to achieve discharge, and to cut off the fourth NMOS N4 through the discharge protection DO port in an overdischarge state or an overtemperature state, and pull up the voltage of the voltage control VM port to achieve stopping discharge.
Therefore, the battery protection control circuit of the example can detect and protect and control the voltage and the current in the charge and discharge state, and the signal detection circuit and the MCU are powered by the circuit with the clamping control function, so that the abnormal state can be prevented from being burnt.
In this possible example, the first NMOS transistor N1 is configured to discharge the internal supply VDDA port when turned on to clamp the voltage VDDA to a preset voltage value.
The preset voltage value may be less than or equal to the rated operating voltage of the MCU and the preset protection circuit at the rear end of the internal supply VDDA port.
In this possible example, as shown in fig. 8, the cascaded MOS transistor module includes a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3;
The second end of the first resistor R1 is connected with the source electrode of the first PMOS tube P1, the grid electrode and the drain electrode of the first PMOS tube P1 are connected with the source electrode of the second PMOS tube P2, the grid electrode and the drain electrode of the second PMOS tube P3 are connected with the source electrode of the third PMOS tube, and the grid electrode and the drain electrode of the third PMOS tube are connected with the grid electrode of the first NMOS tube N1, the grid electrode of the second NMOS tube N2 and the first end of the second resistor R2.
The number of the MOS in the cascaded MOS tube module is not limited only, and the cascaded MOS tube module can be specifically set according to the application requirements of an actual circuit.
The voltage of the positive voltage VDD port should be greater than or equal to the sum of the gate-source voltages of all the MOS transistors in the cascaded MOS transistor module and the gate-source voltage of the first NMOS transistor N1.
In this possible example, as shown in fig. 9, the cascaded MOS transistor module includes a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7;
The second end of the first resistor R1 is connected to the drain electrode and the gate electrode of the fifth NMOS transistor N5, the source electrode of the fifth NMOS transistor N5 is connected to the drain electrode and the gate electrode of the sixth NMOS transistor N6, the source electrode of the sixth NMOS transistor N6 is connected to the drain electrode and the gate electrode of the seventh NMOS transistor N7, and the source electrode of the seventh NMOS transistor N7 is connected to the gate electrode of the first NMOS transistor N1, the gate electrode of the second NMOS transistor N2, and the first end of the second resistor R2.
The three MOS transistors are cascaded so that the on threshold voltage is greater than or equal to the sum of gate source voltages of the three MOS transistors.
In this possible example, the resistance value of the first resistor R1 is set by the following formula,
R1＝min(R1max1，R1max2)，
R1max1＝ΔV1÷I1min＝(VDDmax1－VDDA1)÷I1min，
R1max2＝ΔV2÷(I1min+I2)＝(VDDmax2－VDDA2)÷(I1min+I2)，
I2＝(1÷2)×(W÷L)×μ×Cox×(VGSN1－VTH)2，
VDDA2＝VGS1+VGS2+VGS3+VGSN1，
Wherein, R1max1 is the maximum reference resistance of the first resistor R1 in the normal working state of the system (i.e. the working state of the first NMOS case N1 which is not conducted), and R1max2 is the maximum reference resistance of the first resistor R1 in the overvoltage working state of the system (i.e. the working state of the first NMOS case N1 which is conducted);
Wherein Δv1 is the maximum voltage drop of the first resistor R1 in the normal operation state of the system, I1min is the minimum input current of the internal supply VDDA port in the normal operation state of the system, VDDmax1 is the maximum input voltage of the positive voltage VDD port in the normal operation state of the system, and VDDA1 is the input voltage of the internal supply VDDA port in the normal operation state of the system;
wherein Δv2 is the maximum voltage drop of the first resistor R1 in the system overvoltage working state, I2 is the on current of the first NMOS transistor in the system overvoltage working state, VDDmax2 is the maximum voltage of the positive voltage VDD port in the system overvoltage working state, and VDDA2 is the working voltage of the internal power supply VDDA port in the system overvoltage working state;
wherein, W is the gate width of the MOS transistor in the physical parameter, L is the channel length of the MOS transistor in the physical parameter, W and L are preset according to the empirical value, u is the carrier mobility, VGSN1 is the gate-source voltage of the first NMOS transistor N1, VTH is the voltage threshold;
Wherein VGS1 is the gate-source voltage of the first PMOS transistor P1, VGS2 is the gate-source voltage of the second PMOS transistor P2, VGS3 is the gate-source voltage of the third PMOS transistor P3, or VGS1 is the gate-source voltage of the fifth NMOS transistor N5, VGS2 is the gate-source voltage of the sixth NMOS transistor N6, and VGS3 is the gate-source voltage of the seventh NMOS transistor N7.
Under normal working state, the battery protection control circuit has an equality relation because the cascaded MOS tube module, the first NMOS tube N1 and the second NMOS tube N2 are not conducted, so that the current passing through R1 can directly flow into the rear load of the internal power supply VDDA port
R1max1×i1min=Δv1=vddmax1-VDDA 1, and after conversion, the formula is remembered,
R1max1＝ΔV1÷I1min＝(VDDmax1－VDDA1)÷I1min，
The maximum withstand voltage resistance value allowed to be designed by R1 in a normal working state can be determined through a calculation formula (VDDmax 1-VDDA 1)/(I1 min), in an overvoltage working state, the resistance value of R2 is set to be large enough so that the current flowing through the cascade MOS tube module and R2 is small enough to be ignored, the current flowing through the R1 is (I1min+I2), the conduction current of the I2 serving as a first NMOS tube can be determined based on calculation of preset device physical parameters, and the maximum voltage drop and the combined current of the R1 in the overvoltage working state are calculated, and the maximum reference resistance value of the R1 in the overvoltage working state can be calculated.
Therefore, in this example, the developer may set the first NMOS preferentially based on the design experience, and then calculate the resistance value of R1 according to the formula in this example, so as to improve the stability and efficiency of the design of the battery protection control circuit.
In this possible example, the value of the voltage-withstanding resistor R1 may be optimized according to the normal power consumption requirement of the system. If the power consumption of the low-voltage module of the chip is large, the value of the voltage-resistant resistor R1 can be relatively small to reduce the voltage drop on the low-voltage module, and if the power consumption of the low-voltage module of the chip is small, the value of R1 can be relatively large to ensure that the high voltage is not seen by the low-voltage module.
The resistance of the first resistor R1 is optimized by the following formula,
R1’＝α×R1recharge+β×R1discharge
R1recharge＝R1+(P1－P1recharge)÷I12
R1discharge＝R1+(P1－P1discharge)÷I12
α＝Trecharge÷(Trecharge+Tdischarge)
β＝Tdischarge÷(Trecharge+Tdischarge)
Wherein R1' is an updated resistance value of the first resistor R1, α is a charging weight coefficient, β is a discharging weight coefficient, R1recharge is a reference resistor of the first resistor R1 in a state that the internal supply VDDA port is powered under a first load condition, the first load condition is a working load of a device at the rear end of the internal supply VDDA port in a state that a preset device is the charger, R1discharge is a reference resistor of the first resistor R1 in a state that the internal supply VDDA port is powered under a second load condition, and the second load condition is a working load of a device at the rear end of the internal supply VDDA port in a state that the preset device is the preset load;
wherein, P1recharge is the power consumption of the internal supply VDDA port in the power supply state for the first load condition, P1 is the reference power consumption of the device at the back end of the internal supply VDDA port, and P1discharge is the power consumption of the internal supply VDDA port in the power supply state for the second load condition;
Wherein TRECHARGE is the counted charge reference time of the system, and tdicharge is the counted discharge reference time of the system.
In this example, the battery may dynamically switch between a charging state and a discharging state, and the preset protection circuit at the rear end of the internal supply VDDA port and the MCU in the charging state are in a first load condition (where the preset protection circuit actually enabled in this condition includes at least one of the foregoing overvoltage protection circuit, the over-temperature protection circuit, and the overshoot current protection circuit), and the preset protection circuit at the rear end of the internal supply VDDA port and the MCU in the discharging state are in a second load condition (where the preset protection circuit actually enabled in this condition includes at least one of the foregoing under-voltage protection circuit, over-temperature protection circuit, and over-discharge current protection circuit), so that there is a relatively large probability that there is a relatively large difference between the first load condition and the second load condition, and in the case that the R1 organization setting is not sufficiently refined, there may be a situation that the energy consumption utilization rate is relatively low (such as the R1 resistance value is relatively large, resulting in a relatively low power consumption efficiency of the internal supply VDDA port, or the overall energy consumption is relatively high, etc.), so that the energy consumption rate of the R1 resistance value is designed to effectively improve the energy consumption rate of the circuit.
In this possible example, the physical parameters of the first MOS transistor N1 are set by the following formula,
(W÷L)＝(2×I2 max)÷[μ×Cox×(VGSN1－VTH)2]，
I2max＝Imax－I1min，
Imax＝(VDDmax2－VDDA2)÷R1min，
VDDA2＝VGS1+VGS2+VGS3+VGSN1，
R1min＝(VDD min 1－VDDA1)÷I1max，
Wherein, W is the gate width of the MOS transistor in the physical parameter, L is the channel length of the MOS transistor in the physical parameter, I2 max is the maximum on current of the first NOS transistor N1 in the overvoltage operation state of the system, u is the carrier mobility, VGSN1 is the gate-source voltage of the first NMOS transistor N1, and VTH is the voltage threshold;
wherein Imax is the maximum input current of the positive voltage VDD port in the overvoltage working state of the system, and I1min is the minimum input current of the internal power supply VDDA port in the normal working state of the system;
Wherein VDD max 2 is the maximum input voltage of the positive voltage VDD port in the overvoltage operation state of the system, and VDDA2 is the input voltage of the internal power supply VDDA port in the overvoltage operation state of the system;
Wherein VGS1 is the gate-source voltage of the first PMOS transistor P1, VGS2 is the gate-source voltage of the second PMOS transistor P2, VGS3 is the gate-source voltage of the third PMOS transistor P3, or VGS1 is the gate-source voltage of the fifth NMOS transistor N5, VGS2 is the gate-source voltage of the sixth NMOS transistor N6, and VGS3 is the gate-source voltage of the seventh NMOS transistor N7;
Wherein VDDmin1 is the minimum input voltage of the positive voltage VDD port in the normal operation state of the system, and VDDA1 is the input voltage of the internal power supply VDDA port in the normal operation state of the system.
The minimum resistance of the battery protection control circuit can be calculated based on the equation r1min×i1max= (VDD min 1-VDDA 1) in a normal working state, i2max=imax-I1 min, imax= (vddma2-VDDA 2)/(R1 min), vdda2=vgs 1+vgs2+vgs3+ VGSN1 in an overvoltage working state, so as to calculate I2max, and finally, based on the device parameter equivalent relationship i2max= (1/2) × (W/L) ×μ×cox× (VGSN-VTH) 2 of the first NMOS transistor N1, the physical parameter of N1 is calculated.
It can be seen that, in this example, the resistance of the voltage-withstanding resistor R1 in the battery protection control circuit may be set based on the circuit signal relationship in the normal working state, and then the physical parameter of the first NMOS transistor N1 is further calculated through the determined resistance of R1 and the circuit signal relationship in the overvoltage working state.
As shown in fig. 10, an embodiment of the present application further provides a battery protection control chip, where the battery protection control chip includes the battery protection control circuit described in the foregoing embodiment.
As shown in fig. 11, an embodiment of the present application further provides an electronic device, which includes the battery protection control circuit according to the above embodiment.
The foregoing is only a partial embodiment of the present application, and it should be noted that it will be apparent to those skilled in the art that modifications and adaptations can be made without departing from the principles of the present application, and such modifications and adaptations are intended to be comprehended within the scope of the present application.
Claims (10)
1. The battery protection control circuit is characterized by comprising a positive voltage VDD port, a ground port GND, a first resistor R1, a cascading MOS tube circuit, a first NMOS tube N1, a second NMOS tube N2, a second resistor R2, a preset protection circuit, a micro control unit MCU, a charging protection CO port, a discharging protection DO port and a voltage control VM port;
The positive voltage VDD port is connected with the first end of the first resistor R1, the second end of the first resistor R1 is connected with the cascade MOS tube circuit, the cascade MOS tube circuit is connected with the grid electrode of the first NMOS tube N1, the grid electrode of the second NMOS tube N2 and the first end of the second resistor R2, and the source electrode of the first NMOS tube N1, the second end of the second resistor R2 and the source electrode and the drain electrode of the second NMOS tube N2 are all grounded;
The second end of the first resistor R1 is used as an internal power supply VDDA port and is also connected with the preset protection circuit and the MCU, and the MCU is connected with the charging protection CO port, the discharging protection DO port and the voltage control VM port;
The positive voltage VDD port is used for being connected with a preset device through an EB+ port after being combined with the positive electrode of a battery, the preset device comprises a charger or a preset load, the ground port GND is used for being connected with the negative electrode of the battery, the charging protection CO port is used for being connected with the grid electrode of a third NMOS tube N3, the discharging protection DO port is used for being connected with the grid electrode of a fourth NMOS tube N4, the voltage control VM port is used for being connected with the first end of a third resistor R3, the second end of the third resistor R3 is connected with the source electrode of the third NMOS tube N3 and the positive electrode of a first diode D1 through the EB-port after being combined, the drain electrode of the third NMOS tube N3 and the negative electrode of the first diode D1 are connected with the drain electrode of the fourth NMOS tube N4 and the negative electrode of a second diode D2 after being combined, and the source electrode of the fourth NMOS tube N4 and the positive electrode of the second diode D2 are connected with the negative electrode of the battery;
the resistance of the first resistor R1 is optimized by the following formula,
R1’=α×R1recharge +β×R1discharge
R1recharge=R1+（P1－P1recharge）÷I12
R1discharge =R1+（P1－P1discharge ）÷I12
α=Trecharge÷（Trecharge+ Tdischarge）
β= Tdischarge÷（Trecharge+ Tdischarge）
Wherein R1' is an updated resistance value of the first resistor R1, α is a charging weight coefficient, β is a discharging weight coefficient, R1recharge is a reference resistor of the first resistor R1 in a state that the internal supply VDDA port is powered under a first load condition, the first load condition is a working load of a device at the rear end of the internal supply VDDA port in a state that a preset device is the charger, R1discharge is a reference resistor of the first resistor R1 in a state that the internal supply VDDA port is powered under a second load condition, and the second load condition is a working load of a device at the rear end of the internal supply VDDA port in a state that the preset device is the preset load;
wherein, P1recharge is the power consumption of the internal supply VDDA port in the power supply state for the first load condition, P1 is the reference power consumption of the device at the back end of the internal supply VDDA port, and P1discharge is the power consumption of the internal supply VDDA port in the power supply state for the second load condition;
Wherein TRECHARGE is the counted charge reference time of the system, and tdicharge is the counted discharge reference time of the system.
2. The battery protection control circuit of claim 1, wherein the preset protection circuit comprises at least one of: an overvoltage protection circuit, an undervoltage protection circuit, an over-temperature protection circuit, an over-discharge current protection circuit and an over-charge current protection circuit.
3. The battery protection control circuit according to claim 2, wherein,
The overvoltage protection circuit comprises a fifth resistor R5, a sixth resistor R6 and a first voltage comparator Av1; the positive voltage VDD port is connected to the first end of the fifth resistor R5, the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the positive electrode port of the first voltage comparator Av1, the second end of the sixth resistor R6 is connected to the ground port GND, and the internal reference voltage port and the output port of the first voltage comparator Av1 are connected to the MCU; the MCU is used for closing the third NMOS tube N3 of the charging protection CO port when the overvoltage protection circuit detects an overvoltage state;
The undervoltage protection circuit comprises a seventh resistor R7, an eighth resistor R8 and a second voltage comparator Av2; the positive voltage VDD port is connected to the first end of the seventh resistor R7, the second end of the seventh resistor R7 is connected to the first end of the eighth resistor R8 and the positive electrode port of the second voltage comparator Av2, the second end of the eighth resistor R8 is connected to the ground port GND, and the internal reference voltage port and the output port of the second voltage comparator Av2 are connected to the MCU; the MCU is used for closing the fourth NMOS tube N4 of the discharge protection DO port when the undervoltage protection circuit detects an undervoltage state;
The over-temperature protection circuit comprises a current source, a triode and a third voltage comparator Av3; the positive electrode of the current source is connected with the positive voltage VDD port, the negative electrode of the current source is connected with the emitter of the triode and the positive electrode port of the first current comparator Ai1, the base electrode and the collector electrode of the triode are both connected with the grounding port GND, and the internal reference voltage port and the output port of the first voltage comparator Av1 are connected with the MCU; the MCU is used for closing the third NMOS tube N3 of the charging protection CO port when the over-temperature protection circuit detects that the charging is in an over-temperature state, and closing the fourth NMOS tube N4 of the discharging protection DO port when the over-temperature protection circuit detects that the discharging is in an over-temperature state;
The over-discharge current protection circuit comprises a ninth resistor R9 and a second current comparator Ai2, wherein the positive voltage VDD port is connected with the positive port of the second current comparator Ai2, the negative port of the second current comparator Ai2 is connected with the ground port GND after being connected with the ninth resistor R9 in series, and the output port of the second current comparator Ai2 is connected with the MCU; the MCU is used for closing the fourth NMOS tube N4 of the discharge protection DO port when the discharge overcurrent state is detected through the overdischarge current protection circuit;
The overcharge current protection circuit comprises a tenth resistor R10 and a third current comparator, wherein the positive electrode of the third current comparator is connected with the ground port GND, the negative electrode of the third current comparator is connected with the tenth resistor R10 in series and then is connected with the voltage control VM port, and the output port of the third current comparator is connected with the MCU; the MCU is used for closing the third NMOS tube N3 of the discharge protection CO port when the discharge overcurrent state is detected through the overcharge current protection circuit.
4. The battery protection control circuit according to claim 3, wherein,
If the preset device is the charger, the MCU is configured to turn on the third NMOS N3 through the charging protection CO port in a normal charging state to achieve charging, and turn off the third NMOS N3 through the charging protection CO port in an overcharging state or an overtemperature state to achieve stopping charging;
If the preset device is the load, the MCU is configured to conduct the fourth NMOS N4 through the discharge protection DO port in a normal discharge state to achieve discharge, and to cut off the fourth NMOS N4 through the discharge protection DO port in an overdischarge state or an overtemperature state, and pull up the voltage of the voltage control VM port to achieve stopping discharge.
5. The battery protection control circuit of claim 4, wherein the first NMOS transistor N1 is configured to discharge the internal supply VDDA port when turned on to clamp the voltage VDDA at a preset voltage value.
6. The battery protection control circuit according to claim 5, wherein the cascaded MOS transistor circuit comprises a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3;
The second end of the first resistor R1 is connected with the source electrode of the first PMOS tube P1, the grid electrode and the drain electrode of the first PMOS tube P1 are connected with the source electrode of the second PMOS tube P2, the grid electrode and the drain electrode of the second PMOS tube P3 are connected with the source electrode of the third PMOS tube, and the grid electrode and the drain electrode of the third PMOS tube are connected with the grid electrode of the first NMOS tube N1, the grid electrode of the second NMOS tube N2 and the first end of the second resistor R2.
7. The battery protection control circuit according to claim 5, wherein the cascaded MOS transistor circuit comprises a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7;
The second end of the first resistor R1 is connected to the drain electrode and the gate electrode of the fifth NMOS transistor N5, the source electrode of the fifth NMOS transistor N5 is connected to the drain electrode and the gate electrode of the sixth NMOS transistor N6, the source electrode of the sixth NMOS transistor N6 is connected to the drain electrode and the gate electrode of the seventh NMOS transistor N7, and the source electrode of the seventh NMOS transistor N7 is connected to the gate electrode of the first NMOS transistor N1, the gate electrode of the second NMOS transistor N2, and the first end of the second resistor R2.
8. The battery protection control circuit according to claim 6, wherein the resistance value of the first resistor R1 is set by the following formula,
R1=min（R1max1，R1max2），
R1max1=ΔV1÷I1min=（VDDmax1－VDDA1）÷I1min，
R1max2=ΔV2÷（I1min +I2）=（VDDmax2－VDDA2）÷（I1min +I2），
I2=（1÷2）×（W÷L）×μ×Cox×（VGSN1－VTH）2，
VDDA2= VGS1+ VGS2+ VGS3+ VGSN1，
Wherein, R1max1 is the maximum reference resistance of the first resistor R1 in the normal working state of the system, and R1max2 is the maximum reference resistance of the first resistor R1 in the overvoltage working state of the system;
Wherein Δv1 is the maximum voltage drop of the first resistor R1 in the normal operation state of the system, I1min is the minimum input current of the internal supply VDDA port in the normal operation state of the system, VDDmax1 is the maximum input voltage of the positive voltage VDD port in the normal operation state of the system, and VDDA1 is the input voltage of the internal supply VDDA port in the normal operation state of the system;
wherein Δv2 is the maximum voltage drop of the first resistor R1 in the system overvoltage working state, I2 is the on current of the first NMOS transistor in the system overvoltage working state, VDDmax2 is the maximum voltage of the positive voltage VDD port in the system overvoltage working state, and VDDA2 is the working voltage of the internal power supply VDDA port in the system overvoltage working state;
Wherein W is the gate width of the MOS tube in the physical parameter, L is the channel length of the MOS tube in the physical parameter, W and L are preset according to the empirical value, u is the carrier mobility, VGSN1 is the gate-source voltage of the first NMOS tube N1, and VTH is the voltage threshold;
wherein VGS1 is the gate-source voltage of the first PMOS transistor P1, VGS2 is the gate-source voltage of the second PMOS transistor P2, VGS3 is the gate-source voltage of the third PMOS transistor P3;
Wherein the resistance of R2 is greater than 10k ohms.
9. The battery protection control circuit according to claim 6, wherein the physical parameters of the first NMOS transistor N1 are set by the following formula,
（W÷L）=（2×I2 max）÷[μ×Cox×（VGSN1－VTH）2]，
I2max=Imax－I1min，
Imax=（VDDmax2－VDDA2）÷R1min，
VDDA2= VGS1+ VGS2+ VGS3+ VGSN1，
R1min=（VDD min 1－VDDA1）÷I1max，
Wherein, W is the gate width of the MOS transistor in the physical parameter, L is the channel length of the MOS transistor in the physical parameter, I2 max is the maximum on current of the first NMOS transistor N1 in the overvoltage working state of the system, u is the carrier mobility, VGSN1 is the gate-source voltage of the first NMOS transistor N1, and VTH is the voltage threshold;
wherein Imax is the maximum input current of the positive voltage VDD port in the overvoltage working state of the system, and I1min is the minimum input current of the internal power supply VDDA port in the normal working state of the system;
Wherein VDD max 2 is the maximum input voltage of the positive voltage VDD port in the overvoltage operation state of the system, and VDDA2 is the input voltage of the internal power supply VDDA port in the overvoltage operation state of the system;
wherein VGS1 is the gate-source voltage of the first PMOS transistor P1, VGS2 is the gate-source voltage of the second PMOS transistor P2, VGS3 is the gate-source voltage of the third PMOS transistor P3;
Wherein VDDmin1 is the minimum input voltage of the positive voltage VDD port in the normal operation state of the system, and VDDA1 is the input voltage of the internal power supply VDDA port in the normal operation state of the system.
10. A battery protection control chip, characterized in that the battery protection control chip comprises the battery protection control circuit according to any one of claims 1 to 9.
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