JP2010226224A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a mounting area of a semiconductor device with a reverse connection protection function. <P>SOLUTION: A semiconductor device 50 includes an reverse connection protection circuit 1 and a signal processing unit 2. The reverse connection protection circuit 1 includes a control unit 3, a reverse connection protection diode D1, and a Pch power MOS transistor PMT1. The reverse connection protection diode D1 is a parasitic diode of the Pch power MOS transistor PMT1. A drain of the Pch power MOS transistor PMT1 is connected to a node N1, its source is connected to a node N2, and its gate inputs a signal output from the control unit 3. The control unit 3 includes a power supply 11, a current source 12, a comparator CMP1, a resistor R1, and a switch SW1; and controls on/off operation of the Pch power MOS transistor PMT1. The Pch power MOS transistor PMT1 turns off at a time that a power supply 30 instantaneously stops, or at a time of reverse connection; and turns on when the power supply 30 normally established. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a reverse connection protection circuit mounted on a semiconductor device.

  A reverse connection protection diode is provided between the load drive circuit such as a motor driver and the power supply in order to prevent malfunction of the load drive circuit that occurs when the power supply is reversely connected or when the power supply is momentarily stopped, or an excessive through current. For example, see Patent Document 1.)

  In the load driving circuit described in Patent Document 1 and the like, there is a problem that the mounting area increases because the reverse connection protection diode is externally attached. In addition, if the reverse connection protection diode is built in the load drive circuit in consideration of the mounting area, the thermal resistance increases, which causes a problem that the mounted load drive circuit is overheated.

JP 2008-92277 A (page 10, FIG. 1)

  An object of the present invention is to provide a semiconductor device incorporating a reverse connection protection circuit capable of reducing the mounting area.

  A semiconductor device according to one embodiment of the present invention is provided between a power supply and an internal circuit, and connects between the power supply and the internal circuit when turned on based on a control signal, and connects the power supply to the internal circuit when turned off. Switching means for stopping supply, an anode connected to the power supply, a cathode connected to the internal circuit, a reverse connection protection diode connected in parallel with the switching means between the power supply and the internal circuit, and the power supply Is set, the control signal in the enabled state is output to the switching means to turn on the switching means, and the control signal in the disabled state is supplied to the switching means when the power supply is momentarily stopped or reversely connected. A reverse connection protection circuit having a control unit for outputting and turning off the switching means, and the reverse connection protection circuit and the internal circuit are the same Characterized in that it is formed-up.

  Furthermore, a semiconductor device according to another aspect of the present invention is provided between a power supply and a semiconductor integrated circuit, and connects between the power supply and the semiconductor integrated circuit when turned on based on a control signal, and the semiconductor integrated circuit when turned off. Switching means for stopping the supply of the power to the anode, the anode is connected to the power supply, the cathode is connected to the semiconductor integrated circuit, and is connected in parallel with the switching means between the power supply and the semiconductor integrated circuit When the reverse connection protection diode and the power supply are set, the control signal in an enabled state is output to the switching means to turn on the switching means, and the power supply is disabled when the power supply is momentarily stopped or reversely connected. A reverse connection protection circuit having a control unit that outputs a control signal to the switching means to turn off the switching means; Wherein the serial reverse connection protection circuit semiconductor integrated circuit is characterized in that it is mounted on the same substrate.

  According to the present invention, it is possible to provide a semiconductor device including a reverse connection protection circuit capable of reducing the mounting area.

1 is a circuit diagram showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. 1 is a circuit diagram showing a semiconductor device of a comparative example according to Example 1 of the present invention. 3 is a timing chart showing the operation of the semiconductor device when the power supply according to Embodiment 1 of the present invention changes. 5 is a timing chart showing the operation of the semiconductor device of the comparative example when the power supply according to the first embodiment of the present invention is changed. FIG. 6 is a circuit diagram showing a configuration of a semiconductor device according to Example 2 of the present invention. FIG. 6 is a circuit diagram showing a configuration of a semiconductor device according to Example 3 of the invention. FIG. 6 is a circuit diagram showing a configuration of a semiconductor device according to Embodiment 4 of the present invention. FIG. 9 is a circuit diagram showing a configuration of a semiconductor device according to Example 5 of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a semiconductor device, and FIG. 2 is a circuit diagram showing a semiconductor device of a comparative example. In this embodiment, the reverse connection protection circuit is on-chip.

  As shown in FIG. 1, the semiconductor device 50 includes a reverse connection protection circuit 1 and a signal processing unit 2 as an internal circuit. The semiconductor device 50 is a load drive circuit incorporating the reverse connection protection circuit 1 (on-chip), and is applied to, for example, motor control, an inverter, a switching power supply, and the like. The semiconductor device 50 is supplied with the high potential side power supply VCC from the power supply 30, the capacitor Cin is externally attached to the power supply 30 side, and the capacitor Cout is externally attached to the signal processing unit 2 side.

  The capacitor Cin is a stabilization capacitor that has one end connected to the node N1 of the semiconductor device 50 and the other end connected to the low-potential-side power supply VSS that is the ground potential, and stabilizes the high-potential-side power supply VCC voltage. The capacitor Cout is a stabilization capacitor that has one end connected to the node N2 of the semiconductor device 50 and the other end connected to the low-potential-side power source VSS, and stabilizes the voltage at the node N2.

  The reverse connection protection circuit 1 is provided between the power supply 30 and the capacitor Cin, the signal processing unit 2 and the capacitor Cout, and the control unit 3, the reverse connection protection diode D1, and the Pch power MOS transistor PMT1 are provided. The reverse connection protection circuit 1 serves to prevent malfunctions and excessive through currents that occur in the signal processing unit 2 when the power supply 30 is momentarily stopped or when the power supply 30 is reversely connected.

  The reverse connection protection diode D1 has an anode connected to the node N1 (the power supply 30 and the capacitor Cin side) and a cathode connected to the node N2 (the capacitor Cout side). Here, as the reverse connection protection diode D1, a parasitic diode of the Pch power MOS transistor PMT1 is used, but a diode provided separately from the Pch power MOS transistor PMT1 may be used. When a diode provided separately is used, a reverse breakdown voltage or the like different from that of the Pch power MOS transistor PMT1 can be set.

  In the Pch power MOS transistor PMT1, the drain is connected to the node N1, the source is connected to the node N2, and the signal output from the control unit 3 is input to the gate, and the signal is turned on / off by this signal. Specifically, the Pch power MOS transistor PMT1 is turned on when this signal is enabled (low level), and the Pch power MOS transistor PMT1 is turned off when this signal is disabled (high level).

  The Pch power MOS transistor PMT1 functions as switching means. Here, the Pch power MOS transistor PMT1 uses LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) having a relatively high breakdown voltage and a low on-resistance, but instead a trench having a relatively high breakdown voltage and a low on-resistance. A type Pch power MOS transistor or the like may be used.

  The control unit 3 is provided with a power supply 11, a current source 12, a comparator CMP1, a resistor R1, and a switch SW1.

  The resistor R1 has one end connected to the source (node N2) of the Pch power MOS transistor PMT1 and the other end connected to the gate (node N3) of the Pch power MOS transistor PMT1. The power source 11 has a positive side connected to the negative port on the input side of the comparator CMP1, a negative side connected to the node N5 (low potential side power source VSS), and supplies the reference voltage Vr to the negative port on the input side of the comparator CMP1.

  The comparator CMP1 has a positive port on the input side connected to the source (node N2) of the Pch power MOS transistor PMT1, a reference voltage Vr is input to the negative port on the input side, and outputs a control signal S1 that is a comparatively amplified signal. . Here, when the voltage VN2 at the node N2 is lower than the reference voltage Vr, the control signal S1 is at a low level, and when the voltage VN2 at the node N2 is higher than the reference voltage Vr, the control signal S1 is at a high level.

  One end of the current source 12 is connected to the node N5 (low potential side power source VSS). Switch SW1 has one end connected to the gate (node N3) of Pch power MOS transistor PMT1 and the other end connected to the other end of current source 12. Here, the switch SW1 is turned on when the control signal S1 is at a high level, and is turned off when the control signal S1 is at a low level. When the switch SW1 is turned on, the Pch power MOS transistor PMT1 is turned on, and when the switch SW1 is turned off, the Pch power MOS transistor PMT1 is turned off.

  The signal processing unit 2 as an internal circuit is provided between the reverse connection protection circuit 1 and the capacitor Cout, receives a high potential side power supply VCC from the node N2, receives an input signal (not shown), performs signal processing, and performs signal processing. The signal is output.

  As shown in FIG. 2, the semiconductor device 60 of the comparative example, which is a load driving circuit, is supplied with the high potential side power supply VCC from the power supply 30 via the externally connected reverse connection protection diode D11, and the power supply 30 side (node N1 The capacitor Cin is externally attached to the side), and the capacitor Cout is externally attached to the node N2 side.

  The capacitor Cin is a stabilization capacitor that has one end connected to the node N1 and the other end connected to the low-potential-side power supply VSS, and stabilizes the high-potential-side power supply VCC voltage. The capacitor Cout is a stabilization capacitor that has one end connected to the node N2 and the other end connected to the low-potential-side power source VSS, and stabilizes the voltage at the node N2. The externally connected reverse protection diode D11 has an anode connected to the node N1 and a cathode connected to the node N2.

  Next, the operation of the semiconductor device when the power supply is changed will be described with reference to FIGS. FIG. 3 is a timing chart showing the operation of the semiconductor device when the power supply changes, and FIG. 4 is a timing chart showing the operation of the semiconductor device of the comparative example when the power supply changes.

  As shown in FIG. 3, in the semiconductor device 50 of this embodiment, when the power supply 30 is normally set and the high potential side power supply VCC is supplied to the semiconductor device 50, the switch SW1 is turned on and the Pch power MOS transistor PMT1 is turned on. Turns on. Since the on-resistance of the Pch power MOS transistor PMT1 is very small, the voltage VN2 at the node N2 is substantially the same as the voltage VN1 at the node N1 until the time T1 (VN1≈VN2≈VCC).

  Next, when the power supply 30 stops instantaneously at time T1 for some reason, the voltage at the node N1 and the voltage at the node N2 decrease with the same slope.

  Subsequently, at time T2, the control signal S1 output from the comparator CMP1 changes from low level to high level, the switch SW1 changes from on to off, and the Pch power MOS transistor PMT1 turns off. After the Pch power MOS transistor PMT1 is turned off, the voltage drop at the node N1 is the same as the slope between the time T1 and the time T2, but the voltage at the node N2 is lower than the node N1 due to the influence of the capacitor Cout. Is very slow. The voltage at the node N1 becomes the low potential side power supply VSS level at the time T3, while the voltage at the node N2 becomes the low potential side power supply VSS level at the time T4 that is later than the time T3.

  Then, when the instantaneous power interruption of the power supply 30 stops and the power supply 30 recovers at time T5, the Pch power MOS transistor PMT1 is turned off, so that the voltages at the nodes N1 and N2 start to increase. At this time, the voltage of the node N2 is lower than the node N1 by Vf (forward voltage) of the parasitic diode D1 of the Pch power MOS transistor PMT1 due to the influence of the parasitic diode D1 of the Pch power MOS transistor PMT1.

  Next, when the voltages at the nodes N1 and N2 are boosted and the time T6 is reached, the control signal S1 output from the comparator CMP1 changes from low level to high level, the switch SW1 changes from off to on, and Pch power The MOS transistor PMT1 is turned on.

  Subsequently, the voltages at the node N1 and the node N2 are boosted with the same slope, and at time T7, the voltage VN2 at the node N2 becomes substantially the same as the voltage VN1 at the node N1 (VN1≈VN2≈VCC).

  That is, in the semiconductor device 50 of this embodiment, when the power supply 30 is momentarily stopped, the voltage processing of the power supply 30 is not propagated to the signal processing unit 2 that is an internal circuit, and the signal processing unit 2 malfunctions or excessively penetrates. Current can be prevented. Further, even when an operator or the like mistakenly connects the power supply 30 in reverse, it is possible to prevent malfunction of the signal processing unit 2 that is an internal circuit and an excessive through current. Furthermore, when the power supply 30 is normally set and the semiconductor device 50 is operating, the voltages at the node N1 and the node N2 can be set substantially the same (the voltage at the node N2 is lowered by the on-resistance of the Pch power MOS transistor PMT1). ), The high-potential-side power supply VCC voltage can be supplied to the signal processing unit 2 which is an internal circuit.

  As shown in FIG. 4, in the semiconductor device 60 of the comparative example, when the power supply 30 is normally set and the high potential side power supply VCC is supplied to the semiconductor device 60, the voltage at the node N1 becomes the high potential side power supply VCC level. The voltage at the node N2 is set lower than the node N1 by Vf (forward voltage) of the reverse connection protection diode D11. This state is maintained until time T11.

  Next, when the power supply 30 instantaneously stops at time T11 for some reason, the voltage at the node N1 drops quickly, but the voltage at the node N2 is affected by the capacitor Cout, and the rate of decrease is much slower than that at the node N1. Become. The voltage at the node N1 becomes the low potential power source VSS level at time T12, while the voltage at the node N2 becomes the low potential power source VSS level at time T13, which is later than the time T12.

  Subsequently, when the power interruption of the power supply 30 stops and the power supply 30 recovers at time T14, the voltages at the nodes N1 and N2 start to increase. At this time, the voltage of the node N2 is lower than the node N1 by Vf (forward voltage) of the reverse connection protection diode D1 due to the influence of the reverse connection protection diode D11.

  Then, the voltages at the nodes N1 and N2 are boosted, and at time T15, the voltage at the node N1 becomes the high potential side power supply VCC level, and the voltage at the node N2 is equal to Vf (forward voltage) of the reverse connection protection diode D11. It is set lower than N1. This state is maintained after time T15.

  That is, in the semiconductor device 60 of the comparative example, when the power supply 30 is momentarily stopped, a rapid voltage fluctuation of the power supply 30 is not propagated to the semiconductor device 60, and malfunction of the semiconductor device 60 and excessive through current can be prevented. . Further, even when an operator or the like mistakenly connects the power supply 30 in reverse, the semiconductor device 60 can be prevented from malfunctioning and an excessive through current.

  However, since the reverse connection protection diode is externally attached, there arises a problem that the mounting area increases. Considering the mounting area, if the reverse connection protection diode is simply built in the semiconductor device 60 of the comparative example, the thermal resistance increases, and the mounted semiconductor device 60 of the comparative example is overheated. Furthermore, when the power supply 30 is normally set and the semiconductor device 60 is operating, the semiconductor device 60 is not connected to the high-potential-side power supply VCC voltage, but is connected to the Vf of the reverse connection protection diode D11 from the high-potential-side power supply VCC voltage. A voltage lower by the direction voltage) is supplied.

  As described above, in the semiconductor device of this embodiment, the reverse connection protection circuit 1 and the signal processing unit 2 are provided on the same chip. The reverse connection protection circuit 1 includes a control unit 3, a reverse connection protection diode D1, and a Pch power MOS transistor PMT1. The reverse connection protection diode D1 has an anode connected to the node N1 (power source 30 side) and a cathode connected to the node N2 (signal processing unit 2 side). The Pch power MOS transistor PMT1 has a very small on-resistance, the drain is connected to the node N1, the source is connected to the node N2, and the signal output from the control unit 3 is input to the gate. The control unit 3 includes a power supply 11, a current source 12, a comparator CMP1, a resistor R1, and a switch SW1, and controls the on / off operation of the Pch power MOS transistor PMT1. The Pch power MOS transistor PMT1 is turned off when the power supply 30 is momentarily stopped or reversely connected based on a signal output from the control unit 3, and is turned on when the power supply 30 is normally set.

  For this reason, when the power supply 30 is momentarily stopped or reversely connected, a sudden voltage fluctuation of the power supply 30 is not propagated to the signal processing unit 2 which is an internal circuit, and malfunction of the signal processing unit 2 and an excessive through current are prevented. be able to. Further, since the reverse connection protection diode D1 is configured by the parasitic diode of the Pch power MOS transistor PMT1, overheating of the semiconductor device 50 can be prevented. Furthermore, the high potential side power supply VCC with no voltage drop can be supplied to the signal processing unit 2.

  In this embodiment, the comparator CMP1 is used in which the input positive port is connected to the node N2 and the reference voltage Vr is input to the input negative port. Instead, the input negative port is connected to the node N2. May be used, and a comparator in which the reference voltage Vr is input to the positive port on the input side may be used.

  Next, a semiconductor device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 5 is a circuit diagram showing a configuration of the semiconductor device. In this embodiment, the configuration of the reverse connection protection circuit is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 5, the semiconductor device 51 is provided with a reverse connection protection circuit 1a and a signal processing unit 2 as an internal circuit. The semiconductor device 51 is a load drive circuit that incorporates the reverse connection protection circuit 1a (on-chip), and is applied to, for example, motor control, an inverter, a switching power supply, and the like. The semiconductor device 51 is supplied with the high potential side power supply VCC from the power supply 30, the capacitor Cin is externally attached to the power supply 30 side, and the capacitor Cout is externally attached to the signal processing unit 2 side.

  The reverse connection protection circuit 1a is provided between the power supply 30 and the capacitor Cin, the signal processing unit 2 and the capacitor Cout, and includes a control unit 3a, a reverse connection protection diode D1, and a Pch power MOS transistor PMT1. The reverse connection protection circuit 1a serves to prevent malfunctions and excessive through currents that occur in the signal processing unit 2 when the power supply 30 is momentarily stopped or when the power supply 30 is reversely connected.

  The control unit 3a is provided with a power supply 11, a comparator CMP11, a resistor R1, and an amplifier AMP1.

  The power source 11 has a positive side connected to the negative port on the input side of the comparator CMP11, a negative side connected to the node N5 (low potential side power source VSS), and supplies the reference voltage Vr to the negative port on the input side of the comparator CMP11.

  The comparator CMP11 has a positive port on the input side connected to the source (node N2) of the Pch power MOS transistor PMT1, and a reference voltage Vr is input to the negative port on the input side, and outputs a control signal that is a comparatively amplified signal. Here, when the voltage VN2 at the node N2 is smaller than the reference voltage Vr, the control signal is at a low level, and when the voltage VN2 at the node N2 is larger than the reference voltage Vr, the control signal is at a high level.

  The amplifier AMP1 is provided between the comparator CMP11 and the node N3 (the gate of the Pch power MOS transistor PMT1 and the other end of the resistor R1). The amplifier AMP1 converts the control signal output from the comparator CMP11 into a voltage / current, and outputs the amplified current. It is a current output type amplifier that outputs.

  Here, when the control signal output from the comparator CMP11 is at a low level, the Pch power MOS transistor PMT1 is turned off. When the control signal output from the comparator CMP11 is at a high level, the Pch power MOS transistor PMT1 is turned on. Note that the operation of the semiconductor device 51 when the power supply 30 is instantaneously stopped or reversely connected is the same as that of the first embodiment, and thus the description thereof is omitted.

  As described above, in the semiconductor device of this embodiment, the reverse connection protection circuit 1a and the signal processing unit 2 are provided on the same chip. The reverse connection protection circuit 1a includes a control unit 3a, a reverse connection protection diode D1, and a Pch power MOS transistor PMT1. The Pch power MOS transistor PMT1 has a very small on-resistance, the drain is connected to the node N1, the source is connected to the node N2, and the signal output from the control unit 3a is input to the gate. The control unit 3a includes a power supply 11, a comparator CMP11, a resistor R1, and an amplifier AMP1, and controls the on / off operation of the Pch power MOS transistor PMT1. The Pch power MOS transistor PMT1 is turned off when the power supply 30 is momentarily stopped or reversely connected based on a signal output from the control unit 3a, and turned on when the power supply 30 is normally set.

  For this reason, when the power supply 30 is momentarily stopped or reversely connected, a sudden voltage fluctuation of the power supply 30 is not propagated to the signal processing unit 2 which is an internal circuit, and malfunction of the signal processing unit 2 and an excessive through current are prevented. be able to. Further, since the reverse connection protection diode D1 is constituted by the parasitic diode of the Pch power MOS transistor PMT1, overheating of the semiconductor device 51 can be prevented. Furthermore, the high potential side power supply VCC with no voltage drop can be supplied to the signal processing unit 2.

  Next, a semiconductor device according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 6 is a circuit diagram showing a configuration of the semiconductor device. In this embodiment, the configuration of the reverse connection protection circuit is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 6, the semiconductor device 52 includes a reverse connection protection circuit 1b and a signal processing unit 2 as an internal circuit. The semiconductor device 52 is a load drive circuit that incorporates the reverse connection protection circuit 1b (on-chip), and is applied to, for example, motor control, an inverter, a switching power supply, and the like. The semiconductor device 52 is supplied with the high potential side power supply VCC from the power supply 30, the capacitor Cin is externally attached to the power supply 30 side, and the capacitor Cout is externally attached to the signal processing unit 2 side.

  The reverse connection protection circuit 1b is provided between the power supply 30 and the capacitor Cin, the signal processing unit 2 and the capacitor Cout, and a control unit 3b, a reverse connection protection diode D1, and a Pch power MOS transistor PMT1 are provided. The reverse connection protection circuit 1b serves to prevent malfunctions and excessive through currents that occur in the signal processing unit 2 when the power source 30 is momentarily stopped or when the power source 30 is reversely connected.

  The control unit 3b includes a power supply 11, a current source 12, a comparator CMP1, a resistor R1, a reverse connection protection diode D2, and a switch SW1.

  The power source 11 has a positive side connected to the negative port on the input side of the comparator CMP1, a negative side connected to the node N5 (low potential side power source VSS), and supplies the reference voltage Vr to the negative port on the input side of the comparator CMP1. The reverse connection protection diode D2 has an anode connected to the node N1 and a cathode connected to the plus port on the input side of the comparator CMP1.

  The comparator CMP1 has a positive port on the input side connected to the cathode of the reverse connection protection diode D2, a reference voltage Vr is input to the negative port on the input side, and outputs a control signal S1 that is a comparatively amplified signal. Here, when the voltage VN2 at the node N1 is smaller than the reference voltage Vr, the control signal S1 is at a low level, and when the voltage VN2 at the node N1 is larger than the reference voltage Vr, the control signal S1 is at a high level. Note that the operation of the semiconductor device 52 at the time of momentary power failure or reverse connection of the power supply 30 is the same as that of the first embodiment, and thus the description thereof is omitted.

  As described above, in the semiconductor device of this embodiment, the reverse connection protection circuit 1b and the signal processing unit 2 are provided on the same chip. The reverse connection protection circuit 1b is provided with a control unit 3b, a Pch power MOS transistor PMT1, and a parasitic diode D1 of the Pch power MOS transistor PMT1. The reverse connection protection diode D1 has an anode connected to the node N1 (power source 30 side) and a cathode connected to the node N2 (signal processing unit 2 side). The Pch power MOS transistor PMT1 has a very small on-resistance, the drain is connected to the node N1, the source is connected to the node N2, and the signal output from the control unit 3b is input to the gate. The control unit 3b includes a power supply 11, a current source 12, a comparator CMP1, a resistor R1, a reverse connection protection diode D2, and a switch SW1, and controls the on / off operation of the Pch power MOS transistor PMT1. The Pch power MOS transistor PMT1 is turned off when the power source 30 is momentarily stopped or reversely connected based on a signal output from the control unit 3b, and is turned on when the power source 30 is normally set.

  For this reason, when the power supply 30 is momentarily stopped or reversely connected, a sudden voltage fluctuation of the power supply 30 is not propagated to the signal processing unit 2 which is an internal circuit, and malfunction of the signal processing unit 2 and an excessive through current are prevented. be able to. Further, since the reverse connection protection diode D1 is configured by the parasitic diode of the Pch power MOS transistor PMT1, overheating of the semiconductor device 52 can be prevented. Furthermore, the high potential side power supply VCC with no voltage drop can be supplied to the signal processing unit 2.

  Next, a semiconductor device according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 7 is a circuit diagram showing a configuration of the semiconductor device. In this embodiment, the configuration of the reverse connection protection circuit is changed.

  In the following, the same components as those in the second embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 7, the semiconductor device 53 is provided with a reverse connection protection circuit 1c and a signal processing unit 2 as an internal circuit. The semiconductor device 53 is a load drive circuit that incorporates the reverse connection protection circuit 1c (on-chip), and is applied to, for example, motor control, an inverter, a switching power supply, and the like. The semiconductor device 53 is supplied with the high potential side power supply VCC from the power supply 30, the capacitor Cin is externally attached to the power supply 30 side, and the capacitor Cout is externally attached to the signal processing unit 2 side.

  The reverse connection protection circuit 1c is provided between the power supply 30 and the capacitor Cin, the signal processing unit 2 and the capacitor Cout, and includes a control unit 3c, a reverse connection protection diode D1, and a Pch power MOS transistor PMT1. The reverse connection protection circuit 1c serves to prevent malfunctions and excessive through currents that occur in the signal processing unit 2 when the power source 30 is instantaneously stopped or when the power source 30 is reversely connected.

  The control unit 3c is provided with a power supply 11, a comparator CMP11, a resistor R1, a reverse connection protection diode D2, and an amplifier AMP1.

  The power source 11 has a positive side connected to the negative port on the input side of the comparator CMP11, a negative side connected to the node N5 (low potential side power source VSS), and supplies the reference voltage Vr to the negative port on the input side of the comparator CMP11. The reverse connection protection diode D2 has an anode connected to the node N1 and a cathode connected to the plus port on the input side of the comparator CMP11.

  In the comparator CMP11, the positive port on the input side is connected to the cathode of the reverse connection protection diode D2, the reference voltage Vr is input to the negative port on the input side, and a control signal that is a comparatively amplified signal is output. Here, when the voltage VN2 at the node N1 is smaller than the reference voltage Vr, the control signal becomes low level, and when the voltage VN2 at the node N1 is larger than the reference voltage Vr, the control signal becomes high level. Note that the operation of the semiconductor device 53 when the power supply 30 is instantaneously stopped or reversely connected is the same as that of the first embodiment, and thus the description thereof is omitted.

  As described above, in the semiconductor device of this embodiment, the reverse connection protection circuit 1c and the signal processing unit 2 are provided on the same chip. The reverse connection protection circuit 1c is provided with a control unit 3c, a reverse connection protection diode D1, and a Pch power MOS transistor PMT1. The Pch power MOS transistor PMT1 has a very small on-resistance, the drain is connected to the node N1, the source is connected to the node N2, and the signal output from the control unit 3c is input to the gate. The control unit 3c includes a power source 11, a comparator CMP11, a resistor R1, a reverse connection protection diode D2, and an amplifier AMP1, and controls the on / off operation of the Pch power MOS transistor PMT1. The Pch power MOS transistor PMT1 is turned off when the power source 30 is momentarily stopped or reversely connected based on a signal output from the control unit 3c, and is turned on when the power source 30 is normally set.

  For this reason, when the power supply 30 is momentarily stopped or reversely connected, a sudden voltage fluctuation of the power supply 30 is not propagated to the signal processing unit 2 which is an internal circuit, and malfunction of the signal processing unit 2 and an excessive through current are prevented. be able to. Further, since the reverse connection protection diode D1 is constituted by the parasitic diode of the Pch power MOS transistor PMT1, overheating of the semiconductor device 53 can be prevented. Furthermore, the high potential side power supply VCC with no voltage drop can be supplied to the signal processing unit 2.

  Next, a semiconductor device according to Embodiment 5 of the present invention will be described with reference to the drawings. FIG. 8 is a circuit diagram showing a configuration of the semiconductor device. In this embodiment, the reverse connection protection circuit and the semiconductor integrated circuit are mounted on the same substrate.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 8, the semiconductor device 70 is provided with a reverse connection protection circuit 1 and a semiconductor integrated circuit 61. The semiconductor device 70 is a load drive circuit in which the reverse connection protection circuit 1 and the semiconductor integrated circuit 61 are mounted on the same substrate, and is applied to, for example, motor control, an inverter, a switching power supply, and the like. The semiconductor device 70 is supplied with the high potential side power supply VCC from the power supply 30, the capacitor Cin is externally attached to the power supply 30 side, and the capacitor Cout is externally attached to the semiconductor integrated circuit 61 side. Here, the semiconductor device 70 is a module in which the reverse connection protection circuit 1 and the semiconductor integrated circuit 61 are formed and mounted on the same substrate. In some cases, a resin-encapsulated MCP (Multi Chip Package) may be used.

  Here, since the two chips of the reverse connection protection circuit 1 and the semiconductor integrated circuit 61 are mounted on the same substrate, it is not necessary to manufacture the reverse connection protection circuit 1 and the semiconductor integrated circuit 61 in the same manufacturing process. Since each chip can be manufactured by a manufacturing process adapted to required characteristics, it is easy to realize desired characteristics, the manufacturing process can be simplified, and the manufacturing process does not become long. Note that the operation of the semiconductor device 70 when the power source 30 is instantaneously stopped or reversely connected is the same as that of the first embodiment, and thus the description thereof is omitted.

  As described above, in the semiconductor device of this embodiment, the reverse connection protection circuit 1 and the semiconductor integrated circuit 61 are mounted on the same substrate. The reverse connection protection circuit 1 includes a control unit 3, a reverse connection protection diode, and a Pch power MOS transistor PMT1. The reverse connection protection diode D1 has an anode connected to the node N1 (power supply 30 side) and a cathode connected to the node N2 (semiconductor integrated circuit 61 side). The Pch power MOS transistor PMT1 has a very small on-resistance, the drain is connected to the node N1, the source is connected to the node N2, and the signal output from the control unit 3 is input to the gate. The control unit 3 includes a power supply 11, a current source 12, a comparator CMP1, a resistor R1, and a switch SW1, and controls the on / off operation of the Pch power MOS transistor PMT1. The Pch power MOS transistor PMT1 is turned off when the power supply 30 is momentarily stopped or reversely connected based on a signal output from the control unit 3, and is turned on when the power supply 30 is normally set.

  For this reason, in addition to the effects of the first embodiment, since it is not necessary to manufacture the reverse connection protection circuit 1 and the semiconductor integrated circuit 61 by the same manufacturing process, each chip can be manufactured by a manufacturing process suitable for the required characteristics. It is easy to realize desired characteristics.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, a Pch power MOS transistor is used as the switching means, but an Nch power MOS transistor may be used instead.

The present invention can be configured as described in the following supplementary notes.
(Additional remark 1) It is provided between the power supply and the internal circuit, and a control signal is input to the gate. Based on the control signal, the power supply and the internal circuit are connected when turned on, and the internal circuit is connected when turned off. A Pch power MOS transistor for stopping supply of power, an anode connected to the power supply, a cathode connected to the internal circuit, and connected in parallel with the Pch power MOS transistor between the power supply and the internal circuit. When the first reverse connection protection diode and the power supply are set, the control signal in an enabled state is output to the Pch power MOS transistor to turn on the Pch power MOS transistor, and when the power supply is momentarily stopped or reverse connected Sometimes, the disabled control signal is output to the Pch power MOS to output the Pch power MOS transistor. A semiconductor device comprising a reverse connection protection circuit having a control unit for turning off the star, wherein the reverse connection protection circuit and the internal circuit are formed on the same chip.

(Supplementary Note 2) The control unit includes a second reverse connection protection diode having an anode connected to the power source, a positive port on the input side connected to a cathode of the second reverse connection protection diode, and a negative port on the input side. A comparator that receives a reference voltage and outputs a comparatively amplified signal, one end connected to the source of the Pch power MOS transistor, the other end connected to the gate of the Pch power MOS transistor, and one end low potential A power source connected to the side power supply, one end connected to the gate of the Pch power MOS transistor, the other end connected to the other end of the current source, and based on a signal output from the comparator, The semiconductor device according to claim 1, further comprising a switch that turns on when set and turns off when the power supply is momentarily stopped or reversely connected. .

(Supplementary Note 3) The control unit includes a second reverse connection protection diode having an anode connected to the power supply, a positive port on the input side connected to a cathode of the second reverse connection protection diode, and a negative port on the input side. A comparator that receives a reference voltage and outputs a comparatively amplified signal, a resistor having one end connected to the source of the Pch power MOS transistor and the other end connected to the gate of the Pch power MOS transistor, and an output from the comparator The semiconductor device according to appendix 1, further comprising: an amplifier that receives the amplified signal and outputs an amplified current to the gate of the Pch power MOS transistor.

DESCRIPTION OF SYMBOLS 1, 1a, 1b, 1c Reverse connection protection circuit 2 Signal processing part 3, 3a, 3b, 3c Control part 11, 30 Power supply 12 Current source 50-53, 60, 70 Semiconductor device 61 Semiconductor integrated circuit AMP1 Amplifier Cin, Cout Capacitor CMP1 , COMP11 Comparator D1, D2, D11 Reverse connection protection diode N1-N6 Node PMT1 Pch power MOS transistor R1 Resistance SW1 Switch S1 Control signal VCC High potential side power supply Vr Reference voltage VSS Low potential side power supply

Claims (5)

  A switching means provided between the power supply and the internal circuit, and connected between the power supply and the internal circuit when turned on, and based on a control signal, stops supplying the power to the internal circuit when turned off; and an anode Connected to the power supply, the cathode is connected to the internal circuit, a reverse connection protection diode connected in parallel with the switching means between the power supply and the internal circuit, and when the power supply is set, Control that outputs the control signal to the switching means to turn on the switching means, and outputs the control signal in a disabled state to the switching means to turn off the switching means at the time of an instantaneous power failure or reverse connection A reverse connection protection circuit having a portion, wherein the reverse connection protection circuit and the internal circuit are formed on the same chip. That the semiconductor device.   Switching means provided between the power supply and the semiconductor integrated circuit, which connects between the power supply and the semiconductor integrated circuit when turned on and stops the supply of the power supply to the semiconductor integrated circuit when turned off based on a control signal; The anode is connected to the power supply, the cathode is connected to the semiconductor integrated circuit, and a reverse connection protection diode connected in parallel with the switching means between the power supply and the semiconductor integrated circuit, and the power supply is set. In addition, the control signal in the enabled state is output to the switching means to turn on the switching means, and the control signal in the disabled state is output to the switching means when the power supply is momentarily stopped or reversely connected. A reverse connection protection circuit having a control unit for turning off the means, the reverse connection protection circuit and the semiconductor integrated circuit Wherein a is mounted on the same substrate.   The semiconductor device according to claim 1, wherein the switching unit is a Pch power MOS transistor.   The control unit includes a comparator having an input-side plus port connected to the cathode of the reverse connection protection diode, a reference voltage inputted to the input-side minus port, and outputting a comparatively amplified signal, and one end of the Pch power MOS transistor A resistor connected to the source of the Pch power MOS transistor, the other end connected to the gate of the Pch power MOS transistor, a current source connected to the low potential power source at one end, and one end connected to the gate of the Pch power MOS transistor, The other end is connected to the other end of the current source, and includes a switch that is turned on when the power source is set based on a signal output from the comparator and turned off when the power source is momentarily stopped or reversely connected. The semiconductor device according to claim 3.   The control unit has a positive port on the input side connected to the source of the Pch power MOS transistor, a reference voltage is input to the negative port on the input side, and outputs a comparatively amplified signal, and one end of the Pch power MOS A resistor connected to the source of the transistor and having the other end connected to the gate of the Pch power MOS transistor and a signal output from the comparator are input, and an amplified current is output to the gate of the Pch power MOS transistor. The semiconductor device according to claim 3, further comprising an amplifier.

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