CN109217276A - A kind of voltage clamping and esd protection circuit - Google Patents
A kind of voltage clamping and esd protection circuit Download PDFInfo
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- CN109217276A CN109217276A CN201811218642.3A CN201811218642A CN109217276A CN 109217276 A CN109217276 A CN 109217276A CN 201811218642 A CN201811218642 A CN 201811218642A CN 109217276 A CN109217276 A CN 109217276A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
Abstract
The present invention provides a kind of voltage clamping and esd protection circuits, including VCC voltage detection circuit, VCC detecting voltage transfer circuit, ESD circuit for detecting, ESD detecting transfer circuit and voltage absorptive unit；VCC voltage detection circuit is connected with power supply port and VCC detecting voltage transfer circuit, VCC detecting voltage transfer circuit is connected with voltage absorptive unit, ESD circuit for detecting is connected with ESD detecting transfer circuit, ESD detecting transfer circuit is connected with voltage absorptive unit, and voltage absorptive unit is connected with PWM switch control IC chip.The present invention absorbs charge excessive in excessively high voltage and esd event by having shared a voltage absorptive unit, it is ensured that internal pwm control circuit is not damaged, saves chip area.And ESD circuit for detecting can guarantee that esd event triggers RC circuit and open protective effect, and can prevent the peak voltage being superimposed in chip normal working voltage from causing false triggering to clamp circuit.
Description
Technical field
The present invention relates to integrated circuit port protection circuit field more particularly to PWM switch control integrated circuits
The voltage clamping and esd protection circuit of supply port.
Background technique
Chip operating voltage is determined by chip manufacturing process.If typical CMOS technology is mainly by PMOS and NMOS device
Part constructs chip.The chip maximum operating voltage that manufacture is completed is determined by PMOS and NMOS maximum operating voltage.It is supplied to
The operating voltage of chip must ensure within the scope of maximum operating voltage, if it exceeds maximum operating voltage meeting as defined in chip
There is expendable punch through damage in the grid oxygen breakdown or source-and-drain junction that MOS transistor device occurs.
Power tube directly obtains voltage, simultaneously meeting by power supply to PWM switch control IC chip during the work time
Spike burr voltage is generated on chip power supply port.After chip operating voltage reaches maximum operating voltage, superposition
Spike burr voltage can cause chip interior device junction breakdown or punch through, or even in some region of chip triggering SCR effect
It answers.It is therefore necessary to absorb to spike burr voltage, it is ensured that chip can be reliable under defined maximum operating voltage
Work.
ESD electrostatic in chip package, test, welding and chip system module routine all can problems faced,
It is necessary that chip internal circuits is protected not damaged by the impact of ESD static discharge charge with ESD protection circuit.
Voltage clamp circuit needs to use the power-type metal-oxide-semiconductor for absorbing due to voltage spikes burr, while esd protection circuit also needs
Use the power-type metal-oxide-semiconductor of Electro-static Driven Comb absorption.The esd protection circuit of supply port is when PWM switch control chip designs
It must be added to.And voltage clamp circuit if necessary to be added then can in addition chip occupying area is added again, such chip supplies
The protection circuit of electric port will occupy a large amount of chip area.
Summary of the invention
The present invention, which provides the new circuit of one kind, can share a power-type for voltage clamp circuit and esd protection circuit
MOS protection pipe saves chip area, while realizing supply voltage clamper and esd protection circuit, and works normally in chip
When, ESD circuit for detecting not will receive the unlatching of the peak voltage false triggering on supply voltage VCC.
To achieve the above object, the present invention provides a kind of voltage clamping and esd protection circuit, which includes VCC electricity
Press circuit for detecting, VCC detecting voltage transfer circuit, ESD circuit for detecting, ESD detecting transfer circuit and voltage absorptive unit；
The VCC voltage detection circuit is connected with power supply port and the VCC detecting voltage transfer circuit, for detecing
The voltage of power supply port is surveyed, and when the voltage of power supply port is more than setting ceiling voltage protection threshold value, it will be excessively electric
Pressure signal is transmitted to VCC detecting voltage transfer circuit；
The VCC detecting voltage transfer circuit is connected with the voltage absorptive unit, to VCC voltage detection circuit is defeated
Overvoltage signal out amplifies processing, generates the driving voltage of voltage absorptive unit work；
The ESD circuit for detecting is connected with ESD detecting transfer circuit, to detect when supply port esd event occurs
Pulse voltage, and the esd pulse voltage transmission of detecting to ESD is detected into transfer circuit, and prevent normal PWM switch control collection
The non-ESD peak voltage that port generates when working normally at circuit chip prevents voltage absorptive unit from malfunctioning；
The ESD detecting transfer circuit is connected with the voltage absorptive unit, to export ESD voltage circuit for detecting
Spike signal amplifies processing, generates the driving voltage of voltage absorptive unit work；
The voltage absorptive unit is connected with PWM switch control IC chip, to absorb the port power supply VCC
Overvoltage and esd discharge charge.
Preferably, the VCC voltage detection circuit includes concatenated diode string (D1, D2 ..., Dn) and resistance (R1),
Resistance (R1) other end is grounded (GND), and the diode (D1) of head end meets power port (VCC).
Preferably, the VCC voltage detection circuit include concatenated grid leak be shorted PMOS tube string (MP1, MP1 ...,
MPn) and resistance (R1), resistance (R1) other end are grounded (GND), and the source electrode for the PMOS tube (MP1) that the grid leak of head end is shorted connects electricity
Source port (VCC).
Preferably, the VCC voltage detection circuit includes the tandem junction combined by the PMOS tube that diode and grid leak are shorted
Structure and resistance (R1), cascaded structure and resistance (R1) also constitute cascaded structure, and resistance (R1) other end is grounded (GND), head end
The source electrode for the PMOS tube (MP1) that diode (D1) or grid leak are shorted meets power port (VCC).
It is further preferred that the VCC detecting voltage voltage threshold draws signal end by adjusting VCC voltage detection circuit
It realizes, the tie point for drawing PMOS tube string and resistance (R1) that signal end is diode string or grid leak short circuit, or is two poles
Tie point in pipe string between diode, or the tie point between the PMOS tube of grid leak short circuit in the PMOS tube string of grid leak short circuit, or
It for the tie point for the PMOS tube that diode and grid leak are shorted, or is resistance (R1) centre tap.
Preferably, the VCC detecting voltage transfer circuit includes first order common source amplifying circuit and the amplification of second level common source
Circuit,
The first order common source amplifying circuit includes resistance (R2) and NMOS tube (N2), the resistance (R2) and power port
(VCC) it is connected, the other end of resistance (R2) is connected with NMOS tube (N2) drain electrode, NMOS tube (N2) grid and VCC detecting voltage electricity
The output end on road is connected, NMOS tube (N2) source electrode ground connection；
The second level common source amplifying circuit includes resistance (R3) and PMOS tube (P2), the source electrode and power supply of PMOS tube (P2)
Port (VCC) is connected, and the grid of PMOS tube (P2) is connected with the drain electrode of NMOS tube (N2) pipe, the drain electrode of PMOS tube (P2) and resistance
(R3) one end is connected with voltage absorptive unit input terminal, and resistance (R3) other end is grounded (GND).
Preferably, the ESD circuit for detecting includes RC delay circuit and spike interference false triggering circuit, the RC delay electricity
Road includes resistance (R4) and capacitor (C1), and the spike interference false triggering circuit includes resistance (Rz) and diode (DZ1), described
Resistance one end (R4) is connected with power supply power supply port (VCC), and the other end and diode one end (DZ1) and ESD detect transfer circuit
Input terminal is connected, and the diode DZ1 other end is connected with the one end capacitor (C1), and capacitor (C1) other end is connected with ground (GND), described
Resistance (Rz) is connected in parallel on the both ends the diode (DZ1).
Preferably, the ESD circuit for detecting includes RC delay circuit and spike interference false triggering circuit, the RC delay electricity
Road includes resistance (R4) and capacitor (C1), and the spike interference false triggering circuit includes that resistance (Rz) and grid leak are shorted PMOS tube
(DP1), described resistance one end (R4) is connected with power supply power supply port (VCC), and the other end and grid leak are shorted PMOS tube (DP1) source level
It is connected and is connected with ESD detecting transfer circuit input terminal, grid leak is shorted PMOS tube (DP1) drain electrode and is connected with the one end capacitor (C1), electricity
Hold (C1) other end ground connection (GND), the resistance (Rz) is connected in parallel on grid leak and is shorted PMOS tube (DP1) source electrode and drain electrode both ends.
Preferably, ESD detecting transfer circuit includes common-source amplifier, the common-source amplifier include resistance (R3) and
The source electrode of PMOS tube (P1), the PMOS tube (P1) is connected with power port (VCC), PMOS tube (P1) grid with it is described
ESD circuit for detecting output end is connected, PMOS tube (P1) drain electrode and resistance one end (R3) and voltage absorptive unit input terminal phase
Even, resistance (R3) other end ground connection.
Preferably, the voltage absorptive unit is NMOS tube (N1) or BJT manages (Q1).
Of the invention a kind of voltage clamping and esd protection circuit, voltage absorbs after VCC voltage is more than detecting threshold voltage
Unit, which is opened, absorbs VCC too high voltages.When the end VCC is when esd event generates, voltage absorbs single after ESD circuit for detecting works
Member opens the esd discharge charge for absorbing the end VCC, absorbs excessively high voltage and ESD by having shared a voltage absorptive unit
Excessive charge in event, it is ensured that internal pwm control circuit is not damaged, saves chip area.And ESD circuit for detecting can
Protective effect is opened to guarantee that esd event triggers RC circuit, and the spike being superimposed in chip normal working voltage can be prevented
Voltage causes false triggering to clamp circuit.
Detailed description of the invention
Fig. 1 is the existing a kind of voltage clamping and esd protection circuit figure of low pressure applications；
Fig. 2 is the existing a kind of voltage clamping and esd protection circuit figure of low pressure applications；
Fig. 3 is the existing a kind of voltage clamping and esd protection circuit figure of high-voltage applications；
Fig. 4 is the voltage clamping and esd protection circuit figure of a kind of existing high-voltage applications that two-stage common-source amplifier is added；
Fig. 5 is that a kind of existing RC triggers the esd protection circuit figure that PMOS power tube absorbs；
Fig. 6 is that a kind of existing RC triggers the esd protection circuit figure that NMOS power tube absorbs；
Fig. 7 is the esd protection circuit figure that level-one common-source amplifier is added in a kind of RC triggering of the invention；
Fig. 8 is that a kind of joined of the invention prevents spike from interfering the RC of false triggering circuit and level-one common-source amplifier triggering
Esd protection circuit figure；
Fig. 9 is of the invention a kind of voltage clamping and esd protection circuit schematic diagram；
Figure 10 is another voltage clamping and esd protection circuit schematic diagram of the invention；
Figure 11 is another voltage clamping and esd protection circuit schematic diagram of the invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction in inventive embodiments
Attached drawing, the technical solution in inventive embodiments is clearly and completely described, it is clear that the embodiments described below are only
It is only invention a part of the embodiment, and not all embodiment.Based on the embodiment in invention, those of ordinary skill in the art exist
All other embodiment obtained under the premise of creative work is not made, the range of invention protection is belonged to.
Fig. 1 is the existing a kind of voltage clamping and esd protection circuit figure of low pressure applications.
As shown in Figure 1, Fig. 1 is the voltage clamp circuit constituted using the reverse-biased breakdown characteristics of low pressure diode D1, can inhale
Receiving end is made a slip of the tongue high voltage and the ESD protection for port.Diode is device the most basic in Semiconductor Physics device.Two
Pole pipe has forward conduction, the characteristic reversely ended.Forward conduction voltage is 0.7V or so, is superimposed upon two under reverse blocking state
The voltage at pole pipe both ends is not infinity, makes the reverse-biased electric field strength of PN junction be more than electrons and holes collision electricity when backward voltage reaches
When from threshold value, avalanche breakdown effects will occur, the backward voltage for being at this moment added in the both ends PN is breakdown voltage.When ESD is triggered in Fig. 1
It is positive voltage that voltage, which applies the end GND with respect to the end VCC, and ESD diode is in the conductive state, and making electric current from GND to VCC, direction is flowed
Dynamic, GND to VCC both end voltage is limited to 0.7V or so.It is positive voltage, ESD bis- when ESD trigger voltage applies the end VCC with respect to GND
Pole pipe is in reverse blocking state, and when voltage is more than breakdown voltage, electric current flows to GND, the voltage of VCC to GND from the direction VCC
It is limited to breakdown voltage VBD, in the PN junction concentration for adjusting diode, thus it is possible to vary diode reverse breakdown voltage value usually exists
In 5V technique, the gate oxide breakdown voltage of internal metal-oxide-semiconductor is 15~20V.Design port ESD diode breakdown reverse voltage be
5.8V can prevent metal-oxide-semiconductor grid oxygen from irreversible damage occurs by VCC voltage clamping in 5.8V.
The shortcomings that 1 diode carries out voltage clamping and ESD protection is used only in Fig. 1 to be had: (1) diode reverse voltage is solid
It is fixed, it adjusts breakdown voltage and implantation concentration in technique is needed to adjust, standard cure technique can not be adjusted.Voltage selects flexibility low.
(2) clamp voltage value and ESD voltage value are identical.And ESD protection trigger voltage value is needed to be higher than clamp voltage in actual circuit.
(3) diode area, which needs to reach 100um*100um, can just play good clamper and ESD protecting effect.
Fig. 2 is the existing a kind of voltage clamping and esd protection circuit figure of low pressure applications.
As shown in Fig. 2, Fig. 2 is to utilize low pressure diode D1 and resistance R1 port voltage circuit for detecting in series.Work as end
Mouthful voltage, which rises to, punctures diode D1, and when resistance R1 voltage is more than the threshold voltage of absorber power device N1, power tube
N1 make a slip of the tongue opposite end high voltage carry out absorbing clamp.The structural circuit can be to port voltage clamping and port ESD protection.Two poles
The diode area of pipe D1 no longer as shown in figure 1 is so big, only plays D1 after detecting VCC voltage is greater than D1 breakdown voltage and is connected, opens
There is current direction resistance R1 in beginning, when threshold V T HN1, N1 conducting of the voltage VR1 on resistance R1 greater than power tube N1, absorbs
Voltage from the port VCC.Power tube N1 can play certain ESD protective effect, but power tube N1 when esd event occurs
Parasitic NPN pipe be connected in esd event main function played to ESD protection, there is preferable ESD protective effect.It is adopted in Fig. 2
Played the role of to VCC voltage clamping with NMOS tube, while the parasitic NPN of N1 itself also functions to the protective action of ESD.
Voltage clamping used in Fig. 2 and esd protection circuit disadvantage are as follows: (1) ESD protects trigger voltage and voltage clamping
Trigger voltage is identical, and ESD protection trigger voltage value is needed to be higher than clamp voltage in actual circuit.(2) without amplifier to N1 function
The effect of rate tube grid voltage, voltage clamping ability when work are limited.
Fig. 3 is the existing a kind of voltage clamping and esd protection circuit figure of high-voltage applications.
As shown in figure 3, Fig. 3 be using series diode D1, D2 ..., Dn and resistance R1 drive as port voltage detecting
Dynamic high pressure absorber power device N1 is opened, and the voltage that opposite end is made a slip of the tongue high carries out absorbing clamp.The structural circuit can be to port voltage
Clamper and port ESD protection.Fig. 3 uses multiple Diode series primarily to improving VCC clamp voltage.For example, breakdown
The VCC voltage of one diode is 5.8V, then two concatenated VCC voltages of breakdown will reach 11.6V.VCC voltage is more than protection
Diode D1-Dn works in reverse breakdown state after opening threshold value.Fig. 3 is functionally consistent with Fig. 2, and only Fig. 3 can spirit
The clamp voltage of setting VCC living.The breakdown voltage of certain N1 power tube will also choose the VCC clamp voltage much higher value than setting.
Voltage clamping used in Fig. 3 and esd protection circuit disadvantage are identical as in Fig. 2, but clamper trigger voltage and ESD
Trigger voltage can be adjusted by changing number or the connection tap position of series diode.
Fig. 4 is the voltage clamping and esd protection circuit figure of a kind of existing high-voltage applications that two-stage common-source amplifier is added.
As shown in figure 4, Fig. 4 be using series diode D1, D2 ..., Dn and resistance R1 be as port voltage detecting, NMOS
Pipe N2 and resistance R2 forms first order common-source amplifier, and PMOS tube P1 and resistance R3 form second level common-source amplifier.The second level
Common-source amplifier output connection high pressure absorbs the grid of power NMOS tube N1.After VCC voltage is more than ceiling voltage protection threshold value,
The work of series diode voltage detection circuit, the first order and the overturning of second level common-source amplifier, drive high pressure absorber power device N1
It opens, the voltage that opposite end is made a slip of the tongue high carries out absorbing clamp.Since dual-stage amplifier works transmitting signal in the presence of delay, circuit master
It is used to protect port operating voltage clamper when chip works normally.
Fig. 4 increases dual-stage amplifier with respect to Fig. 3 can be with sufficiently conductive N1 power tube.N1 power tube conducting after flow through electric current with
The voltage of grid is at quadratic relationship, and when grid voltage is higher, the electric current for flowing through N1 power tube is bigger, VCC clamp voltage ability
Better.
Voltage clamping used in Fig. 4 and esd protection circuit disadvantage are as follows: (1) ESD protects trigger voltage and voltage clamping
Trigger voltage is identical, and ESD protection trigger voltage value is needed to be higher than clamp voltage in actual circuit.(2) although voltage clamping function
By playing better clamping effect after dual-stage amplifier, but detected when incuding esd event by ESD after dual-stage amplifier
Delay will increase.
Fig. 5 is that a kind of existing RC triggers the esd protection circuit figure that PMOS power tube absorbs.
As shown in figure 5, Fig. 5 is that RC delay circuit is constituted using resistance R4 and capacitor C1, it is only rapid in supply port voltage
Conducting power pipe P1 when rising, power tube P1 make a slip of the tongue opposite end high voltage carry out absorbing clamp.It is anti-that the structure is mainly used for port ESD
Shield.One esd pulse time between 1~100ns, can trigger RC network.Similarly, if circuit work normally when the end VCC
RC network can also be triggered as long as the rising edge of pulse is sufficiently fast by generating a positive sharp pulse voltage.When RC network is touched
Hair, capacitor C1 voltage remain unchanged, and trigger voltage is mainly superimposed upon on resistance R4, when VR1 voltage is greater than P1 conduction threshold
VTHP1, power tube P1 conducting absorb electric current from the end VCC, reduce the peak voltage at the end VCC.The circuit structure is only applicable to VCC
Rectify the triggering of pulsed high-frequency rate.
Fig. 6 is that a kind of existing RC triggers the esd protection circuit figure that NMOS power tube absorbs.
As shown in fig. 6, Fig. 6 is that RC delay circuit is constituted using resistance R4 and capacitor C1, it is only rapid in supply port voltage
Conducting power pipe N1 when rising, power tube N1 make a slip of the tongue opposite end high voltage carry out absorbing clamp.It is anti-that the structure is mainly used for port ESD
Shield.Principle is the same with Fig. 5, absorbs spike positive voltage using N1.One esd pulse time between 1~100ns, can trigger
RC network.Similarly, if the end VCC generates a positive sharp pulse voltage when circuit works normally, as long as the rising edge foot of pulse
It is enough fast, RC network can also be triggered.When RC network is triggered, capacitor C1 voltage remains unchanged, and trigger voltage is mainly superimposed upon electricity
It hinders on R4, when VR1 voltage is greater than N1 conduction threshold VTHN1, power tube N1 conducting absorbs electric current from the end VCC, reduces the end VCC
Peak voltage.The circuit structure is only applicable to VCC and rectifies the triggering of pulsed high-frequency rate.
Fig. 5 and Fig. 6 is frequency event detecting triggering, and principle is identical, is all the grid source that R4 two terminates MOS in structure.Touching
Power generation pressure is superimposed upon on R4, when R4 voltage is more than the threshold voltage of metal-oxide-semiconductor, metal-oxide-semiconductor conducting.Fig. 5 and Fig. 6 is only to ESD
Response has good effect, but has clamp voltage work to the end the VCC voltage changed more slowly not in chip course of normal operation
With.
Fig. 7 is the esd protection circuit figure that level-one common-source amplifier is added in a kind of RC triggering of the invention.
As shown in fig. 7, Fig. 7 is that the RC delay circuit output end constituted in resistance R4 and capacitor C1 is further added by level-one metal-oxide-semiconductor
Common-source amplifier driving power pipe N1, Fig. 7 principle and Fig. 5 that P1 and R3 is constituted, Fig. 6 is the same, though increase level-one common-source amplifier
Right increased level-one common-source amplifier can be slightly slow in speed, but can reduce the impedance of power tube N1 conducting, improves N1 power
The threshold voltage of pipe keeps N1 power tube fully on, improves the absorption charge capability of N1.It is anti-that the structure is mainly used for port ESD
Shield.The power tube N1 but the circuit peak voltage that port generates when working normally again can mislead.
Fig. 8 is that a kind of joined of the invention prevents spike from interfering the RC of false triggering circuit and level-one common-source amplifier triggering
Esd protection circuit figure.
As shown in figure 8, Schmidt trigger, PMOS tube P2 and NMOS tube N2, resistance R4 and capacitor C1 structure is added in opposite Fig. 7
At RC delay circuit, the input of the common-source amplifier of output connection metal-oxide-semiconductor P1 and R3 composition, the output connection of common-source amplifier
The grid of power tube N1.Resistance R4 connects Schmidt trigger SMIT1 with the capacitor C1 output for constituting RC delay circuit simultaneously, applies
The phase inverter that the output connection PMOS tube P2 and NMOS tube N2 of schmitt trigger SMIT1 is constituted, the output of the phase inverter connect function
The grid of rate pipe N1.Peak voltage is generated during port voltage normal power supply to touch by RC delay circuit and common-source amplifier
Power tube N1 conducting is sent out, but since the decline variation of the input voltage of Schmidt trigger SMIT1 is not above turn threshold voltage,
NMOS tube N2 conducting, when setting pulling drive ability of the drop-down driving capability of N2 greater than PMOS tube P1, power tube N1 would not
It is opened when port voltage generates spike by false triggering.
Fig. 9 is of the invention a kind of voltage clamping and esd protection circuit schematic diagram.
As shown in figure 9, series diode D1, D2 ..., Dn and resistance R1 as VCC voltage detection circuit, metal-oxide-semiconductor N2 and
Resistance R2 forms first order common-source amplifier, and metal-oxide-semiconductor P2 and resistance R3 form second level common-source amplifier.The amplification of first order common source
Device and second level amplifier constitute VCC detecting voltage transfer circuit.The power after port voltage is more than highest triggering detecting voltage
Pipe N1 conducting absorbs too high voltages.The circuit is mainly used for chip maximum operating voltage clamper.One end of capacitor C1 is connected to N1
The grid and resistance R1 of pipe constitute RC delay circuit, and resistance Rz and diode DZ1 constitute spike and interfere false triggering circuit, and RC prolongs
When circuit and spike interference false triggering circuit constitute ESD detect transfer circuit.NMOS tube N1 is as voltage absorptive unit.
The other end of capacitor C1 connects the one end diode DZ1, and the other end of diode DZ1 is connected to port VCC.Figure
The both ends diode DZ1 shown can be interchanged, can be with positively biased or reverse-biased, can also be with several Diode series positively biaseds or reverse-biased combination shape
Formula connects, and main purpose is to adjust the voltage of diode.Diode DZ1 forward conduction or reverse breakdown have electric current to pass through
Diode generates a voltage drop, and diode both end voltage drop can be relatively small when no electric current passes through.When port VCC electricity
Pressure is when rising rapidly, it is necessary first to DZ1 is connected or breakdown, the N1 grid voltage that then capacitor C1 and resistance R3 connect again with
With VCC voltage rise, when VCC voltage variety be more than diode voltage drop and power tube N1 turn-on threshold voltage after, function
Rate pipe N1 conducting absorbs the excessively high due to voltage spikes in the port VCC.The voltage drop that diode DZ1 conducting or breakdown generate can be improved
The peak voltage trigger value of port, makes original metal-oxide-semiconductor N1 threshold voltage triggering amount be increased to two poles when chip works normally
Pipe conducting or breakdown voltage add the triggering amount of a metal-oxide-semiconductor N1 threshold voltage, and power tube N1 can be prevented lesser in port
By false triggering under voltage spikes.Resistance Rz is connected in parallel on the both ends of diode DZ1, which is much larger than resistance R1 value, can be with
The voltage drop on the both sides diode DZ1 is maintained into 0V in normal work, improves due to voltage spikes activation threshold value amount.By diode DZ1,
The circuit of capacitor C1, resistance Rz, resistance R3 and power MOS pipe N1 composition is protected for port ESD, and is had and inhibited chip normal
The false triggering of port voltage spike acts on when work.
Figure 10 is of the invention a kind of voltage clamping and esd protection circuit schematic diagram.
As shown in Figure 10, of the invention a kind of voltage clamping and esd protection circuit include VCC voltage detection circuit 1,
VCC detecting voltage transfer circuit 2, ESD circuit for detecting 3, ESD detecting transfer circuit 4 and voltage absorptive unit 5.Each circuit difference
It connects between power supply VCC and ground GND.
VCC voltage detection circuit 1 is connected with power supply port and VCC detecting voltage transfer circuit 2, to detect power supply
The voltage of power port, and when the voltage of power supply port is more than setting ceiling voltage protection threshold value, by overvoltage signal
It is transmitted to VCC detecting voltage transfer circuit.
VCC detecting voltage transfer circuit 2 is connected with voltage absorptive unit 5, to the mistake for exporting VCC voltage detection circuit
Voltage signal amplifies processing, generates the driving voltage of voltage absorptive unit work.
ESD circuit for detecting 3 is connected with ESD detecting transfer circuit 4, to detect arteries and veins when supply port esd event occurs
Voltage is rushed, and the esd pulse voltage transmission of detecting to ESD is detected into transfer circuit, and prevents normal PWM switch control integrated
The non-ESD peak voltage that port generates when circuit chip works normally prevents voltage absorptive unit from malfunctioning.
ESD detecting transfer circuit 4 is connected with voltage absorptive unit 5, to the spike for exporting ESD voltage circuit for detecting 3
Pulse signal amplifies processing, generates the driving voltage that voltage absorptive unit 5 works.
Voltage absorptive unit 5 is connected with PWM switch control IC chip, to absorb the port power supply VCC
Overvoltage and esd discharge charge.Voltage absorptive unit 5 is the BJT pipe Q1 in NMOS tube N1 or Figure 11 in Figure 10.
As shown in Fig. 2, VCC voltage detection circuit 1 in the embodiment of the present invention include concatenated diode string (D1,
D2 ..., Dn) and resistance R1, the resistance R1 other end is grounded GND, and the diode D1 of head end meets power port VCC.
PMOS tube string that the concatenated grid leak that wherein, VCC voltage detection circuit 1 can also be as shown in figure 11 is shorted (MP1,
MP1 ..., MPn) and resistance R1, the resistance R1 other end is grounded GND, and the source electrode for the PMOS tube MP1 that the grid leak of head end is shorted connects power supply
Port VCC.Or the cascaded structure and resistance R1 for the PMOS tube combination being shorted for diode and grid leak, cascaded structure and R1 also structure
At cascaded structure, the resistance R1 other end is grounded GND, and the source electrode for the PMOS tube MP1 that the diode D1 or grid leak of head end are shorted connects electricity
Source port VCC.VCC detecting voltage voltage threshold draws signal end realization by adjusting VCC voltage detection circuit, draws signal end
For the tie point of PMOS tube string and resistance R1 that diode string or grid leak are shorted, or the connection between diode in diode string
Point, or the tie point between the PMOS tube of grid leak short circuit in the PMOS tube string of grid leak short circuit, or be that diode and grid leak are shorted
The tie point of PMOS tube, or be resistance R1 centre tap.
VCC detecting voltage transfer circuit 2 includes first order common source amplifying circuit 21 and second level common source amplifying circuit 22.
First order common source amplifying circuit 21 includes resistance R2 and NMOS tube N2, and resistance R2 is connected with power port VCC, resistance
The other end of R2 and NMOS tube N2 drain electrode are connected, the output end of NMOS tube N2 grid and VCC voltage detection circuit (diode Dn and
R3 tie point) it is connected, NMOS tube N2 source electrode ground connection；
Second level common source amplifying circuit 22 includes resistance R3 and PMOS tube P2, the source electrode and power port VCC of PMOS tube P2
It is connected, the grid of PMOS tube P2 is connected with the drain electrode of NMOS tube N2 pipe, and the source electrode of PMOS tube P2 and the one end resistance R3 and voltage absorb
Unit input terminal (grid of NMOS tube N1) is connected, and the resistance R3 other end is grounded GND.
ESD circuit for detecting 3 includes RC delay circuit 31 and spike interferes false triggering circuit 32, and RC delay circuit 31 includes electricity
Hinder R4) and capacitor C1, it includes resistance Rz and diode DZ1 that spike, which interferes false triggering circuit, the one end resistance R4 and power supply side
Mouth VCC is connected, and the other end is connected with the one end diode DZ1 and ESD detecting transfer circuit input terminal (grid of PMOS tube P1), and two
The pole pipe DZ1 other end is connected with the one end capacitor C1, and the capacitor C1 other end is connected with ground GND, and resistance Rz is connected in parallel on diode DZ1 two
End.
Wherein, DZ1 can be changed to the PMOS tube DP1 that grid leak is shorted in Figure 11.
It includes common-source amplifier that ESD, which detects transfer circuit 4, and common-source amplifier includes resistance R3 and PMOS tube P1, PMOS tube
The source electrode of P1 is connected with power port VCC, PMOS tube P1 grid and 3 output end of ESD circuit for detecting (resistance R4 and diode DZ2
Tie point) it is connected, PMOS tube P1 drain electrode and the one end resistance R3 and voltage absorptive unit 5 input terminal (grid of NMOS tube N1) phase
Even, resistance R3 other end ground connection.
As shown in Fig. 2, work when, when VCC port voltage due to supply voltage spike burr impact or ESD impact, cause
VCC voltage is more than that threshold value, series diode breakdown, the first order and the overturning of second level common-source amplifier are opened in protection, drives high pressure
Absorber power device N1 is opened, and the voltage that opposite end is made a slip of the tongue high carries out absorbing clamp.When ESD sharp pulse is applied to the port VCC, R4, DZ1
(with RZ resistor coupled in parallel), C1 series arm will pass through alternating current.The sharp pulse rate of rise is bigger, passes through the alternating current of the branch
It flows also bigger.When spike slope is sufficiently large, then flowing through the electric current on resistance R4 is connected P1 and raises resistance R4 current potential, makes N1 function
The conducting of rate pipe, absorbs the peak voltage energy on VCC.DZ1 in R4, DZ1 (with RZ resistor coupled in parallel), C1 series arm is acted on
The peak voltage triggering threshold of branch conducting has raised a DZ breakdown reverse voltage, usually 5.8V.It prevents from having served as by a small margin
Peak voltage be applied to the port VCC P1 caused to be opened by false triggering.
Difference of the Figure 10 with respect to Fig. 9 is: the ESD of Fig. 9 only completes ESD protection by a RC circuit triggering, initially
To the grid potential of N1 power tube pull-up ability do not have Figure 10 after the triggering of RC circuit using first stage amplifier to N1 power tube
Grid potential pull-up ability it is strong.
Figure 11 is of the invention a kind of voltage clamping and esd protection circuit schematic diagram.
Figure 11 is another voltage clamping and esd protection circuit schematic diagram of the invention, former in structure as Figure 10
The power tube N1 that the DZ1 diode come in Figure 10 has changed into the metal-oxide-semiconductor DP1, Figure 10 of grid leak short circuit has changed triode Q1 into, former
It manages identical.
The embodiment provides a kind of voltage clamping and esd protection circuit, a power tube has been shared to absorb
Excessive charge in excessively high voltage and esd event, it is ensured that internal pwm control circuit is not damaged.And diode is added
With the concatenated structure of capacitor, it on the one hand can guarantee that esd event triggers RC circuit and open protective effect, and chip can be prevented
The peak voltage being superimposed in normal working voltage causes false triggering to clamp circuit.
Of the invention a kind of voltage clamping and esd protection circuit, voltage absorbs after VCC voltage is more than detecting threshold voltage
Unit, which is opened, absorbs VCC too high voltages.When the end VCC is when esd event generates, voltage absorbs single after ESD circuit for detecting works
Member opens the esd discharge charge for absorbing the end VCC, absorbs excessively high voltage and ESD by having shared a voltage absorptive unit
Excessive charge in event, it is ensured that internal pwm control circuit is not damaged, saves chip area.And ESD circuit for detecting can
Protective effect is opened to guarantee that esd event triggers RC circuit, and the spike being superimposed in chip normal working voltage can be prevented
Voltage causes false triggering to clamp circuit.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (10)
1. a kind of voltage clamping and esd protection circuit, which is characterized in that passed including VCC voltage detection circuit, VCC detecting voltage
Pass circuit, ESD circuit for detecting, ESD detecting transfer circuit and voltage absorptive unit；
The VCC voltage detection circuit is connected with power supply port and the VCC detecting voltage transfer circuit, supplies for detecting
The voltage of electric power port, and when the voltage of power supply port is more than setting ceiling voltage protection threshold value, overvoltage is believed
Number it is transmitted to VCC detecting voltage transfer circuit；
The VCC detecting voltage transfer circuit is connected with the voltage absorptive unit, to export VCC voltage detection circuit
Overvoltage signal amplifies processing, generates the driving voltage of voltage absorptive unit work；
The ESD circuit for detecting is connected with ESD detecting transfer circuit, to detect pulse when supply port esd event occurs
Voltage, and the esd pulse voltage transmission of detecting to ESD is detected into transfer circuit, and prevent the integrated electricity of normal PWM switch control
The non-ESD peak voltage that port generates when road chip works normally prevents voltage absorptive unit from malfunctioning；
The ESD detecting transfer circuit is connected with the voltage absorptive unit, to the spike for exporting ESD voltage circuit for detecting
Pulse signal amplifies processing, generates the driving voltage of voltage absorptive unit work；
The voltage absorptive unit is connected with PWM switch control IC chip, to absorb the mistake of the port power supply VCC
Voltage and esd discharge charge.
2. a kind of voltage clamping according to claim 1 and esd protection circuit, which is characterized in that the VCC detecting voltage
Circuit includes concatenated diode string (D1, D2 ..., Dn) and resistance (R1), and resistance (R1) other end is grounded (GND), head end
Diode (D1) meets power port (VCC).
3. a kind of voltage clamping according to claim 1 and esd protection circuit, which is characterized in that the VCC detecting voltage
Circuit includes that the PMOS tube string (MP1, MP1 ..., MPn) that concatenated grid leak is shorted and resistance (R1), resistance (R1) other end are grounded
(GND), the source electrode for the PMOS tube (MP1) that the grid leak of head end is shorted meets power port (VCC).
4. a kind of voltage clamping according to claim 1 and esd protection circuit, which is characterized in that the VCC detecting voltage
Circuit includes the cascaded structure and resistance (R1) combined by the PMOS tube that diode and grid leak are shorted, cascaded structure and resistance (R1)
Also cascaded structure is constituted, resistance (R1) other end is grounded (GND), the PMOS tube that the diode (D1) or grid leak of head end are shorted
(MP1) source electrode meets power port (VCC).
5. a kind of voltage clamping and esd protection circuit according to claim 2 to 4, which is characterized in that the VCC voltage
Detect voltage threshold and draw signal end by adjusting VCC voltage detection circuit and realize, the extractions signal end for diode string or
The tie point of PMOS tube string and resistance (R1) that grid leak is shorted, or the tie point between diode in diode string, or be grid leak
Tie point between the PMOS tube that grid leak is shorted in the PMOS tube string of short circuit, or the connection of the PMOS tube for diode and grid leak short circuit
Point, or be resistance (R1) centre tap.
6. a kind of voltage clamping according to claim 1 and esd protection circuit, which is characterized in that the VCC detecting voltage
Transfer circuit includes first order common source amplifying circuit and second level common source amplifying circuit,
The first order common source amplifying circuit includes resistance (R2) and NMOS tube (N2), the resistance (R2) and power port
(VCC) it is connected, the other end of resistance (R2) is connected with NMOS tube (N2) drain electrode, NMOS tube (N2) grid and VCC detecting voltage electricity
The output end on road is connected, NMOS tube (N2) source electrode ground connection；
The second level common source amplifying circuit includes resistance (R3) and PMOS tube (P2), the source electrode and power port of PMOS tube (P2)
(VCC) it is connected, the grid of PMOS tube (P2) is connected with the drain electrode of NMOS tube (N2) pipe, the drain electrode of PMOS tube (P2) and resistance (R3) one
End is connected with voltage absorptive unit input terminal, and resistance (R3) other end is grounded (GND).
7. a kind of voltage clamping according to claim 1 and esd protection circuit, which is characterized in that the ESD circuit for detecting
False triggering circuit is interfered including RC delay circuit and spike, and the RC delay circuit includes resistance (R4) and capacitor (C1), described
Spike interference false triggering circuit includes resistance (Rz) and diode (DZ1), described resistance one end (R4) and power supply power supply port
(VCC) it is connected, the other end is connected with diode one end (DZ1) and ESD detecting transfer circuit input terminal, the diode DZ1 other end
It is connected with the one end capacitor (C1), the capacitor C1 other end is connected with ground (GND), and the resistance (Rz) is connected in parallel on the diode
(DZ1) both ends.
8. a kind of voltage clamping according to claim 1 and esd protection circuit, which is characterized in that the ESD circuit for detecting
False triggering circuit is interfered including RC delay circuit and spike, and the RC delay circuit includes resistance (R4) and capacitor (C1), described
Spike interference false triggering circuit includes that resistance (Rz) and grid leak are shorted PMOS tube (DP1), and described resistance one end (R4) and power supply supply
Electric port (VCC) is connected, and the other end is connected with grid leak short circuit PMOS tube (DP1) source level and ESD detecting transfer circuit input terminal phase
Even, grid leak is shorted PMOS tube (DP1) drain electrode and is connected with the one end capacitor (C1), and capacitor (C1) other end is grounded (GND), the resistance
(Rz) it is connected in parallel on grid leak and is shorted PMOS tube (DP1) source electrode and drain electrode both ends.
9. a kind of voltage clamping according to claim 1 and esd protection circuit, which is characterized in that the ESD detecting transmitting
Circuit includes common-source amplifier, and the common-source amplifier includes resistance (R3) and PMOS tube (P1), the source of the PMOS tube (P1)
Pole is connected with power port (VCC), and PMOS tube (P1) grid is connected with the ESD circuit for detecting output end, the PMOS
Pipe (P1) drain electrode is connected with resistance one end (R3) and voltage absorptive unit input terminal, resistance (R3) other end ground connection.
10. a kind of voltage clamping according to claim 1 and esd protection circuit, which is characterized in that the voltage absorbs single
Member is NMOS tube (N1) or BJT manages (Q1).
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| US11837866B1 (en) * | 2022-06-30 | 2023-12-05 | Halo Microelectronics International | ESD protection apparatus and control method |
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| CN112054815A (en) * | 2020-05-07 | 2020-12-08 | 珠海市杰理科技股份有限公司 | Wireless device, transceiving radio frequency circuit thereof and ESD protection circuit thereof |
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| CN112769113A (en) * | 2020-12-22 | 2021-05-07 | 深圳市创芯微微电子有限公司 | Battery protection chip and protection circuit thereof |
| US11837866B1 (en) * | 2022-06-30 | 2023-12-05 | Halo Microelectronics International | ESD protection apparatus and control method |
| CN116087734A (en) * | 2023-02-01 | 2023-05-09 | 南京航空航天大学 | High-precision junction temperature prediction circuit applied to GaN HEMT and working method thereof |
| CN116087734B (en) * | 2023-02-01 | 2024-03-29 | 南京航空航天大学 | High-precision junction temperature prediction circuit applied to GaN HEMT and working method thereof |
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