JP2010182805A - Static electricity protection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a static electricity protection circuit having a higher discharge performance and which can automatically stop a latch-up operation at a proper timing. <P>SOLUTION: A static electricity protection circuit used for a semiconductor apparatus has: a first terminal; a second terminal to which a lower voltage compared with that applied to the first terminal is applied; a main discharging path connected between the first and second terminals and which has an SCR (a silicon controlled rectifier); a delay means that applies a voltage to a third terminal after a voltage equal to or higher than a reference voltage is applied to the first terminal; and a sub discharging path connected between the first and second terminals and which can be conductive when a voltage equal to or higher than a threshold voltage is applied to the third terminal. The sub discharging path can be conductive to stop latch-up of the SCR provided in the main discharging path. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electrostatic protection circuit for protecting a semiconductor device such as an IC from a high voltage caused by ESD (Electrostatic Discharge) or the like.

  Conventionally, an electrostatic protection circuit or an element (also referred to as an ESD protection circuit or an element) for protecting a semiconductor device such as an IC from a high voltage due to ESD or the like has been used. ESD is also expressed as a surge voltage or the like. These protection circuits or elements are connected to an input terminal of an IC or the like, and a high voltage such as ESD higher than a voltage signal normally supplied by the IC or a voltage signal recognized as a normal signal is applied to the input terminal. When this is done, the semiconductor device such as an IC is protected by discharging it to the ground terminal or the like.

  As an IV characteristic necessary for such a protection circuit or protection element, there is a window characteristic as shown in FIG. That is, since it is necessary to perform a protection operation (snapback operation) before reaching the withstand voltage of the IC or the like, the trigger voltage (Vt1) at which the protection operation is started must be lower than the breakdown voltage of the IC or the like.

  On the other hand, the hold voltage which is the lowest voltage after the start of the protection operation (Vh) must be higher than the operation voltage of the IC or the like. Otherwise, the voltage (or voltage signal) to be supplied to the IC or the like is absorbed.

  In such a protection circuit or protection element, an SCR (Silicon Controlled Rectifier) or the like is used as a conductive state when a high voltage is applied to the input terminal.

  When using the SCR, once the protection operation, that is, the latch-up operation is started, the latch-up operation continues until the voltage applied to the SCR falls below the hold voltage. It is necessary to make the hold voltage higher than that. In particular, when connected to a power supply terminal for supplying power to an IC or the like (protection for power supply), if the hold voltage is lowered, the protection circuit or the protection element may be destroyed without stopping the latch-up operation.

  In order to increase the hold voltage when the SCR is used for a protection circuit or a protection element, it is necessary to connect a diode in series or increase a resistance component. An invention about an electrostatic breakdown protection circuit having such a structure is disclosed (for example, see Patent Document 1).

JP 2005-101386 A

  However, in the structure such as the electrostatic breakdown protection circuit described in Patent Document 1, the hold voltage can be increased, but the discharge performance of the SCR deteriorates.

  That is, when the hold voltage is increased, the discharge performance of the SCR is degraded, and when the hold voltage is decreased, the latch-up operation may not be stopped. FIG. 6 is a diagram showing how such inconvenience occurs. Therefore, when the SCR is used for a protection circuit or a protection element, the hold voltage and the discharge performance are in a trade-off relationship, and it is desirable to make the hold voltage as low as possible within a range in which the latch-up operation is stopped.

  The present invention has been made to solve such problems, and it is a main object of the present invention to provide an electrostatic protection circuit having higher discharge performance and capable of automatically stopping the latch-up operation at an appropriate timing. And

In order to achieve the above object, one embodiment of the present invention provides:
An electrostatic protection circuit used in a semiconductor device,
A first terminal;
A second terminal to which a low voltage is applied compared to the first terminal;
A main discharge path connected between the first terminal and the second terminal and having an SCR (Silicon Controlled Rectifier);
Delay means for applying a voltage to the third terminal after a voltage equal to or higher than a reference voltage is applied to the first terminal;
A sub-discharge path that is connected between the first terminal and the second terminal and becomes conductive when a voltage equal to or higher than a threshold is applied to the third terminal;
The sub-discharge path is made conductive, thereby stopping SCR latch-up of the main discharge path,
It is an electrostatic protection circuit.

  According to this embodiment of the present invention, it is possible to provide an electrostatic protection circuit that has higher discharge performance and can automatically stop the latch-up operation at an appropriate timing.

In one embodiment of the present invention,
The sub-discharge path may be a path connected between a fourth terminal connected to a base of an NPN transistor in the SCR included in the main discharge path and the second terminal.

  In this case, the same element can be used as the transistor in the sub-discharge path and the NPN transistor in the SCR included in the main discharge path, so that a protection circuit or a protection element can be designed at low cost.

  According to the present invention, it is possible to provide an electrostatic protection circuit that has higher discharge performance and can automatically stop the latch-up operation at an appropriate timing.

It is a figure which shows a mode that an electrostatic protection circuit is connected to a power supply terminal and a signal terminal for protection of an internal circuit. It is a circuit structural example of the electrostatic protection circuit 1 which concerns on 1st Example of this invention. The electrostatic protection circuit 1 is an example applied to a device having a plurality of anode terminals. It is a circuit structural example of the electrostatic protection circuit 2 which concerns on 2nd Example of this invention. It is a figure which shows the window characteristic which is IV characteristic required in a protection circuit or a protection element. It is a figure which shows inconveniences, such as the discharge performance of SCR falling when a hold voltage is made high.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings.

<Premise>
FIG. 1 is a diagram illustrating a state in which an electrostatic protection circuit is connected to a power supply terminal and a signal terminal for protecting an internal circuit. In an internal circuit configured as a semiconductor device, an instantaneous high voltage is applied from the connection terminal (power supply terminal or signal terminal) to the outside due to the charge accumulated in the internal parasitic capacitance, or conversely due to external noise or switching. An instantaneous high voltage may be applied. If such a situation occurs, the semiconductor device, which is an internal circuit, may be deteriorated or destroyed, so that it does not normally operate between the power supply terminal and the ground terminal or between the signal terminal and the ground terminal for the purpose of protecting the internal circuit. An electrostatic protection circuit that discharges to the ground terminal only when a high voltage is applied is installed.

<First embodiment>
The electrostatic protection circuit 1 according to the first embodiment of the present invention will be described below. FIG. 2 is a circuit configuration example of the electrostatic protection circuit 1 according to the first embodiment of the present invention. The electrostatic protection circuit 1 is connected to an anode terminal 70, which is an input terminal (power supply terminal or signal terminal) of an internal circuit (protected circuit) 100, to a ground terminal directly or via a reference potential, and has a lower voltage than the anode terminal. Is a circuit for protecting the internal circuit 100, being connected between the cathode terminal 80 to which is applied.

  The electrostatic protection circuit 1 includes an SCR 10, a delay circuit 20, and a sub-transistor 30 as main components.

  The SCR 10 is connected between the anode terminal 70 and the cathode terminal 80 to form a main discharge path. The SCR 10 includes a PNP transistor 11, an NPN transistor 12, and resistors 13 and 14. The sum of the resistance value of the resistor 13 and the ON resistance of the NPN transistor 12 is set sufficiently lower than the internal resistance of the internal circuit 100.

  The emitter of the PNP transistor 11 is connected to the anode terminal 70. The base of the PNP transistor 11 is connected to the anode terminal 70 via the resistor 13. The collector of the PNP transistor 11 is connected to a terminal 15 connected to the base of the NPN transistor 12.

  The collector of the NPN transistor 12 is connected to a terminal 16 to which the base of the PNP transistor 11 is connected. The base of the NPN transistor 12 is connected to the terminal 15 as described above, and the terminal 15 is connected to the cathode terminal 80 via the resistor 14. The emitter of the NPN transistor 12 is connected to the cathode terminal 80.

  With this configuration, when a large voltage due to ESD or the like (a voltage equal to or higher than the trigger voltage (Vt1) at which the latch-up operation is started) is applied to the anode terminal 70, the resistor 13 and the NPN transistor 12 are caused by the avalanche breakdown of the NPN transistor 12. The current begins to flow from the anode terminal 70 to the cathode terminal 80 via Before and after this, the base voltage of the PNP transistor 11 rises and the PNP transistor 11 is turned on, the base voltage of the NPN transistor 12 is raised, and the SCR 10 starts a latch-up operation.

  When the latch-up operation is started, a large amount of current flows through the discharge path via the resistor 13 and the NPN transistor 12, which has a resistance value lower than that of the internal resistance of the internal circuit 100. Therefore, the internal circuit 100 can be protected from destruction due to a high voltage. In the present embodiment, since the SCR 10 is directly connected to the anode terminal 70, the latch-up operation can be started quickly.

  Note that when a voltage normally supplied by the internal circuit 100 (for example, 12V) or a voltage signal that is normally recognized is applied between the anode terminal 70 and the cathode terminal 80, the latch-up operation is not started (supply voltage or Voltage signal <trigger voltage (Vt1)). Also, the delay circuit 20 does not start operation.

  The delay circuit 20 includes a voltage clamp circuit 22 and a CR timer 24.

  The voltage clamp circuit 22 has, for example, a structure in which constant voltage diodes (zener diodes) are connected in series. When a voltage higher than the reference voltage is applied to the anode terminal 70, the voltage clamp circuit 22 is fixed according to the standard of the constant voltage diode. A voltage is supplied to the CR timer 24 with a voltage drop. Here, the reference voltage may be approximately the same as or different from the trigger voltage (Vt1).

  The CR timer 24 has a resistor 25 and a capacitor 26. The resistor 25 is connected to the anode side of the voltage clamp circuit 22. The capacitor 26 is connected between the resistor 25 and the cathode terminal 80. A terminal 27 that exists between the resistor 25 and the capacitor 26 is connected to the base of the sub-transistor 30.

  With this configuration, the delay circuit 20 applies a voltage to the terminal 27 after a voltage equal to or higher than the reference voltage is applied to the anode terminal 70. The voltage Vout applied to the terminal 27 is expressed by the following equation (1). In the equation, Vin is a voltage supplied from the voltage clamp circuit 22, R is the resistance value of the resistor 25, and C is the capacitance of the capacitor 26.

  Vout = {1-e ^ (− t / RC)} · Vin (1)

  The sub-transistor 30 is an NPN transistor, for example. The base of the subtransistor 30 is connected to the terminal 27 as described above. The collector of the sub-transistor 30 is connected to the terminal 15 connected to the base of the NPN transistor 12. The emitter of the subtransistor 30 is connected to the cathode terminal 80.

  The sub-transistor 30 makes the collector and the emitter conductive when the voltage Vout applied to the terminal 27 becomes equal to or higher than the threshold value. When the collector and emitter of the subtransistor 30 are brought into conduction, most of the current that has flowed to the base of the NPN transistor 12 flows to the subtransistor 30. As a result, the discharge path based on the thyristor structure in which the latch-up operation has been performed is replaced with the discharge path including the PNP transistor 11 and the sub-transistor 30, and the latch-up operation is automatically stopped at an appropriate timing. As a result, the hold voltage does not need to be increased so much that the discharge performance can be improved as compared with the case where the hold voltage is increased by connecting diodes in series or increasing the resistance component.

  According to the electrostatic protection circuit 1 of the present embodiment described above, it has a higher discharge performance than that in which a diode is connected in series or a resistance component is increased to increase the hold voltage, and The latch-up operation can be automatically stopped at an appropriate timing.

  FIG. 3 shows an example in which the electrostatic protection circuit 1 is applied to a device having a plurality of anode terminals. In this case, the electrostatic protection circuit 1 may be provided for each anode terminal, but the CR timer 24 and the sub-transistor 30 can be shared. FIG. 2 shows a circuit configuration example when the CR timer 24 and the sub-transistor 30 are shared. Thus, by sharing a part of the configuration, the entire circuit can be reduced in size.

<Second embodiment>
Hereinafter, the electrostatic protection circuit 2 according to the second embodiment of the present invention will be described. FIG. 4 is a circuit configuration example of the electrostatic protection circuit 2 according to the second embodiment of the present invention. The electrostatic protection circuit 2 is connected to an anode terminal 70, which is an input terminal (power supply terminal or signal terminal) of the internal circuit (protected circuit) 100, directly or via a reference potential, and has a lower voltage than the anode terminal. Is a circuit for protecting the internal circuit 100, being connected between the cathode terminal 80 to which is applied.

  The electrostatic protection circuit 2 includes an SCR 10, a delay circuit 20, and a sub-transistor 30 as main components.

  Since the SCR 10 and the delay circuit 20 have the same configuration and function as those of the first embodiment, description thereof is omitted.

  The sub-transistor 30 is an NPN transistor, for example. The base of the subtransistor 30 is connected to the terminal 27 as described above. The collector of the sub-transistor 30 is connected to the anode terminal 70. The emitter of the subtransistor 30 is connected to the cathode terminal 80.

  The sub-transistor 30 makes the collector and the emitter conductive when the voltage Vout applied to the terminal 27 becomes equal to or higher than the threshold value. When the collector and emitter of the sub-transistor 30 become conductive, the anode terminal 70 discharges to the cathode terminal 80 via the sub-transistor 30. As a result, the voltage at the anode terminal 70 quickly decreases, and the latch-up operation is automatically stopped at an appropriate timing. As a result, the hold voltage does not need to be increased so much that the discharge performance can be improved as compared with the case where the hold voltage is increased by connecting diodes in series or increasing the resistance component.

  According to the electrostatic protection circuit 2 of the present embodiment described above, it has a higher discharge performance than that in which a diode is connected in series or a resistance component is increased to increase the hold voltage, and The latch-up operation can be automatically stopped at an appropriate timing.

  In the electrostatic protection circuit 2, the avalanche breakdown voltage of the subtransistor 30 needs to be higher than the avalanche breakdown voltage of the NPN transistor 12. Otherwise, the sub-transistor 30 is turned on before the latch-up operation of the SCR 10 is started. Therefore, the same transistor cannot be used as the sub-transistor 30 and the NPN transistor 12. In this respect, the first embodiment has an advantage that the circuit can be designed at a lower cost.

  The best mode for carrying out the present invention has been described above with reference to the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention. And substitutions can be added.

  For example, the configuration of the delay circuit 20 is not limited to that of the embodiment, and may be configured using, for example, an LC circuit.

  The present invention can be used in the automobile manufacturing industry, the automobile parts manufacturing industry, and the like.

1, 2 Static electricity protection circuit 10 SCR
DESCRIPTION OF SYMBOLS 11 PNP transistor 12 NPN transistor 13, 14, 25 Resistance 15, 16, 27 Terminal 20 Delay circuit 22 Voltage clamp circuit 24 CR timer 26 Capacitor 30 Subtransistor 70 Anode terminal 80 Cathode terminal 100 Internal circuit

Claims (2)

An electrostatic protection circuit used in a semiconductor device,
A first terminal;
A second terminal to which a low voltage is applied compared to the first terminal;
A main discharge path connected between the first terminal and the second terminal and having an SCR (Silicon Controlled Rectifier);
Delay means for applying a voltage to the third terminal after a voltage equal to or higher than a reference voltage is applied to the first terminal;
A sub-discharge path that is connected between the first terminal and the second terminal and becomes conductive when a voltage equal to or higher than a threshold is applied to the third terminal;
The sub-discharge path is made conductive, thereby stopping SCR latch-up of the main discharge path,
ESD protection circuit. The sub-discharge path is a path connected between a fourth terminal connected to a base of an NPN transistor in the SCR included in the main discharge path and the second terminal.
The electrostatic protection circuit according to claim 1.