CN101562334B - Power supply control circuit for electro-static discharge (ESD) protection - Google Patents
Power supply control circuit for electro-static discharge (ESD) protection Download PDFInfo
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- CN101562334B CN101562334B CN2008100936228A CN200810093622A CN101562334B CN 101562334 B CN101562334 B CN 101562334B CN 2008100936228 A CN2008100936228 A CN 2008100936228A CN 200810093622 A CN200810093622 A CN 200810093622A CN 101562334 B CN101562334 B CN 101562334B
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- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000001681 protective effect Effects 0.000 claims description 26
- 238000012360 testing method Methods 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000001514 detection method Methods 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 14
- 230000000694 effects Effects 0.000 description 7
- 230000003068 static effect Effects 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 5
- 206010003497 Asphyxia Diseases 0.000 description 4
- 230000036632 reaction speed Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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Abstract
The invention relates to a power supply control circuit for electro-static discharge (ESD) protection, which functions as a part of an integrated circuit provided with a high-voltage power line and a low-voltage power line and comprises an ESD instantaneous detection circuit and a main circuit; the ESD instantaneous detection circuit is electrically connected between the high-voltage power line and the low-voltage power line; the main circuit is driven by the ESD instantaneous detection circuit and is also electrically connected between the high-voltage power line and the low-voltage power line; and the main circuit comprises a transistor and a field oxide device, wherein the substrate of the field oxide device is connected with the substrate of the transistor. The power supply control circuit for ESD protection can extremely rapidly control the power supply and can bear extremely high ESD current so as to achieve the purpose of ESD protection.
Description
Technical field
The invention relates to a kind of power supply clamped circuit of Electrostatic Discharge protection, particularly about a kind of power supply clamped circuit that is applied in the electrostatic discharge protective in the integrated circuit (IC).
Background technology
ESD protection circuit (electrostatic discharge protection circuit) is applied between the input and output of CMOS integrated circuit; Utilize a P type diode to be connected to high-voltage power-line; Utilize a N type diode to be connected to the low-tension supply line again, cooperate the low-tension supply line to carry out power supply strangulation (power damping).It requires to can stand bigger static discharge current, and reaction wants fast.
See also Fig. 1, it is a kind of circuit diagram of existing ESD protection circuit.In Fig. 1, ESD protection circuit 1 is to be made up of instantaneous testing circuit 10 of ESD and a nmos pass transistor Mnl parallelly connected with it.Wherein the instantaneous testing circuit 10 of ESD is to be made up of resistance R, capacitor C and inverter; In the circuit of reality with CMOS processing procedure made; Capacitor C is to be made up of 101 of NMOS elements, and inverter then is to be made up of a PMOS transistor Mp and a nmos pass transistor Mn, and is as shown in Figure 1.
In ESD protection circuit 1; Because the grid of nmos pass transistor Mnl is connected in the output of inverter; The input of inverter then is connected in the node between resistance R and the capacitor C; Therefore the gate coupled effect (gate couple effect) that it caused just can utilize the reaction speed that is exceedingly fast to carry out the power supply strangulation, to reach the purpose of electrostatic discharge protective.
Yet; The shortcoming of existing ESD protection circuit as shown in Figure 1 is; Because nmos pass transistor has significantly rapid collapse (snapback) phenomenon of returning, therefore driven nmos pass transistor Mn1 collapses (breakdown) easily and burns, and this makes that the width (width) of nmos pass transistor must be big in the extreme in design; Just enough disperse static discharge current and can not make it to burn, but the uneven problem of conducting (turn on) takes place in excessive MOS transistor area easily.
See also Fig. 2, it is a United States Patent (USP) the 5th, 744, the circuit diagram of the ESD protection circuit that is proposed for No. 842.Fig. 2 and Fig. 1 different be in; ESD protection circuit 2 is to trigger field oxide device (substrate trigger field-oxide device) STFOD by instantaneous testing circuit 20 of identical ESD and a substrate parallelly connected with it to constitute, and is as shown in Figure 2.
In this ESD protection circuit 2, because use is that substrate triggers field oxide device STFOD, though have the advantage that can stand big static discharge current, shortcoming is that reaction speed is slower.
Duty is event, and the applicant tests and research through concentrated in view of the disappearance that is produced in the prior art, and a spirit of working with perseverance, and visualizes the present invention's " power supply clamped circuit of electrostatic discharge protective " eventually, below is brief description of the present invention.
Summary of the invention
Therefore; Be necessary to conceive a kind of power supply clamped circuit that is applied in the electrostatic discharge protective in the integrated circuit; Not only can carry out the power supply strangulation at a terrific speed; Also can stand great static discharge current, improve the shortcoming of aforementioned two kinds of prior aries simultaneously, reach the purpose of electrostatic discharge protective.
According to above-mentioned conception; The present invention proposes a kind of power supply clamped circuit of electrostatic discharge protective; It forms the part of an integrated circuit; This integrated circuit has a high-voltage power-line and a low-tension supply line, and the power supply clamped circuit of this electrostatic discharge protective comprises: the instantaneous testing circuit of an ESD is electrically connected between this high-voltage power-line and this low-tension supply line; And a main circuit, drive and be electrically connected between this high-voltage power-line and this low-tension supply line by the instantaneous testing circuit of this ESD.This main circuit comprises: a first transistor, have a grid, a drain electrode, one source pole and a substrate, and this grid is electrically connected at the instantaneous testing circuit of this ESD, and this drain electrode and this source electrode are electrically connected between this high-voltage power-line and this low-tension supply line; And a field oxide device, having three ends and a substrate, this three end is electrically connected between this high-voltage power-line and this low-tension supply line, and this substrate of this field oxide device is electrically connected at this substrate of this first transistor.
The present invention is by attached drawings and detailed description, so that more deep understanding:
Description of drawings
Fig. 1: a kind of circuit diagram of existing ESD protection circuit.
Fig. 2: United States Patent (USP) the 5th, 744, the circuit diagram of the ESD protection circuit that is proposed for No. 842.
Fig. 3: the circuit diagram of first preferred embodiment of the power supply clamped circuit of electrostatic discharge protective proposed by the invention.
Fig. 4: the circuit diagram of second preferred embodiment of the power supply clamped circuit of electrostatic discharge protective proposed by the invention.
Fig. 5: the circuit diagram of the 3rd preferred embodiment of the power supply clamped circuit of electrostatic discharge protective proposed by the invention.
Fig. 6: the circuit diagram of the 4th preferred embodiment of the power supply clamped circuit of electrostatic discharge protective proposed by the invention.
Fig. 7: the circuit diagram of the 5th preferred embodiment of the power supply clamped circuit of electrostatic discharge protective proposed by the invention.
Embodiment
See also Fig. 3, it is the circuit diagram of first preferred embodiment of the power supply clamped circuit of electrostatic discharge protective proposed by the invention.The power supply clamped circuit 3 of the electrostatic discharge protective of Fig. 3 has comprised instantaneous testing circuit 30 of ESD and the main circuit that is made up of element 31 and 32.Instantaneous testing circuit 30 of ESD and main circuit all are electrically connected between the high-voltage power-line VDD low-tension supply line VSS.
In the embodiments of figure 3; The instantaneous testing circuit 30 of ESD has comprised capacitor C that is one another in series and the resistance R that is connected between high-voltage power-line VDD and the low-tension supply line VSS; And element 31 is nmos pass transistors, and element 32 is a field oxide device (field-oxide device).
As shown in Figure 3; The main invention spirit of the present invention is; Let the substrate of nmos pass transistor 31 and the substrate that the field oxide device is violated be electrically connected to each other; Thus, just can utilize the gate coupled effect of nmos pass transistor 31 to drive earlier nmos pass transistor 31 earlier, (trigger) the field oxide device 32 that utilizes the substrate of nmos pass transistor 31 to trigger again.
Owing to the reaction speed of the gate coupled effect driving N MOS transistor 31 that utilizes nmos pass transistor 31 is very fast, utilize the substrate triggering field oxide device criminal of nmos pass transistor 31 then can make it stand bigger electrostatic defending electric current; Therefore, ESD protection circuit 3 proposed by the invention can have the advantage of aforementioned two kinds of prior aries simultaneously.
In the embodiments of figure 3, be to be used as the field oxide device with a nmos pass transistor to violate, and under same invention spirit, also can utilize a silicon control rectification body (SCR) to be used as field oxide device 32, as shown in Figure 4.
See also Fig. 4, it is the circuit diagram of second preferred embodiment of the power supply clamped circuit of electrostatic discharge protective proposed by the invention.In Fig. 4, the element of the instantaneous testing circuit 40 of ESD is all identical with Fig. 3 with configuration mode, and the configuration mode of nmos pass transistor 41 is also identical with nmos pass transistor 31, but field oxide device 32 is implemented with silicon control rectification body (SCR) 42; But immovablely be; This moment, the substrate of nmos pass transistor 41 was still the P type substrate that is electrically connected at silicon control rectification body (SCR) 42; Can flow to the P type substrate place of silicon control rectification body (SCR) 42 with the static discharge current of the nmos pass transistor 41 of guaranteeing to flow through, reach the purpose that the aforementioned substrate that utilizes nmos pass transistor 41 triggers field oxide device 42 whereby.
Except the instantaneous testing circuit of ESD of aforementioned resistance one electric capacity (RC) formula, also can adopt the mode of aforementioned second kind of resistance that prior art is carried one electric capacity one inverter to dispose the instantaneous testing circuit of ESD.See also Fig. 5, it is the circuit diagram of the 3rd preferred embodiment of the power supply clamped circuit of electrostatic discharge protective proposed by the invention.Fig. 5 is in the element and the configuration mode of the instantaneous testing circuit 50 of ESD with the different of Fig. 3; That is; Except the series sequence of resistance R and capacitor C is put upside down; Also the grid at nmos pass transistor 51 has electrically connected an inverter, and the configuration mode of this inverter is identical with aforementioned prior art, is to use a PMOS transistor Mp of mutual series connection and a nmos pass transistor Mn to constitute.Certainly, circuit start and the first two embodiment among Fig. 5 are roughly the same, and the effect that can reach is also similar, so locate no longer to give unnecessary details.
See also Fig. 6, it is the circuit diagram of the 4th preferred embodiment of the power supply clamped circuit of the electrostatic discharge protective that this case proposed.Fig. 6 and Fig. 5 different be in, a field nmos pass transistor 32 that constitutes field oxide device 52 is replaced with silicon control rectification body 62, remaining circuit start is then roughly the same with previous embodiment, the effect that can reach is also similar.
See also Fig. 7, it is the circuit diagram of the 5th preferred embodiment of the power supply clamped circuit of the electrostatic discharge protective that this case proposed.Fig. 7 is in the electric connection mode of nmos pass transistor 71 with a nmos pass transistor 72 with the different of Fig. 3; That is the substrate of a nmos pass transistor 72 is electrically connected at the source electrode and the low-tension supply line VSS of nmos pass transistor 71 simultaneously, and the grid of a nmos pass transistor 72 then changes into and is electrically connected at low-tension supply line VSS.Utilize this different connected mode, also can reach the gate coupled effect of utilizing nmos pass transistor 71 earlier and drive nmos pass transistor 71 earlier, utilize nmos pass transistor 71 to trigger the purpose of field oxide device 72 again.
In sum; The power supply clamped circuit of electrostatic discharge protective proposed by the invention is with being arranged on the nmos pass transistor next door by the field nmos pass transistor that nmos pass transistor triggered in the conventional art; Let the substrate of the two electrically connect mutually to share P type substrate; Make static discharge current can flow through the in regular turn substrate of nmos pass transistor and the substrate of nmos pass transistor; So just can make the power supply clamped circuit of this electrostatic discharge protective when carrying out the power supply strangulation at a terrific speed, can also stand great static discharge current, reach the purpose of electrostatic discharge protective.
Claims (4)
1. the power supply clamped circuit of Electrostatic Discharge protection, it forms the part of an integrated circuit, and this integrated circuit has a high-voltage power-line and a low-tension supply line, and the power supply clamped circuit of this electrostatic discharge protective comprises:
The instantaneous testing circuit of one ESD is electrically connected between this high-voltage power-line and this low-tension supply line;
And
One main circuit drives and is electrically connected between this high-voltage power-line and this low-tension supply line by the instantaneous testing circuit of this ESD, comprising:
One the first transistor has a grid, a drain electrode, one source pole and a substrate, and this grid is electrically connected at the instantaneous testing circuit of this ESD, and this drain electrode and this source electrode are electrically connected between this high-voltage power-line and this low-tension supply line; And
One field oxide device has three ends and a substrate, and this three end is electrically connected between this high-voltage power-line and this low-tension supply line, and this substrate of this field oxide device is electrically connected at this substrate of this first transistor;
The instantaneous testing circuit of this ESD comprises:
One resistance has one first end and one second end, and this of this resistance first end is electrically connected at this high-voltage power-line;
One electric capacity has one first end and one second end, and this of this electric capacity first end is electrically connected at this second end of this resistance, and this of this electric capacity second end is electrically connected at this low-tension supply line;
One PMOS transistor; Have one source pole, a grid and a drain electrode; Transistorized this source electrode of this PMOS is electrically connected at this high-voltage power-line; Transistorized this grid of this PMOS is electrically connected at this second end of this resistance and this first end of this electric capacity, and transistorized this drain electrode of this PMOS is electrically connected at this grid of this first transistor; And
One nmos pass transistor; Have a drain electrode, a grid and one source pole; This drain electrode of this nmos pass transistor is electrically connected at transistorized this drain electrode of this PMOS; This grid of this nmos pass transistor is electrically connected at this second end of this resistance and this first end of this electric capacity, and this source electrode of this nmos pass transistor is electrically connected at this low-tension supply line.
2. the power supply clamped circuit of electrostatic discharge protective as claimed in claim 1, wherein this first transistor is a nmos pass transistor.
3. the power supply clamped circuit of electrostatic discharge protective as claimed in claim 1, wherein this field oxide device is a nmos pass transistor.
4. the power supply clamped circuit of electrostatic discharge protective as claimed in claim 1, wherein this field oxide device is a silicon control rectification body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100936228A CN101562334B (en) | 2008-04-17 | 2008-04-17 | Power supply control circuit for electro-static discharge (ESD) protection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100936228A CN101562334B (en) | 2008-04-17 | 2008-04-17 | Power supply control circuit for electro-static discharge (ESD) protection |
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| Publication Number | Publication Date |
|---|---|
| CN101562334A CN101562334A (en) | 2009-10-21 |
| CN101562334B true CN101562334B (en) | 2012-05-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2008100936228A Expired - Fee Related CN101562334B (en) | 2008-04-17 | 2008-04-17 | Power supply control circuit for electro-static discharge (ESD) protection |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8773826B2 (en) * | 2012-08-29 | 2014-07-08 | Amazing Microelectronic Corp. | Power-rail electro-static discharge (ESD) clamp circuit |
| CN103117280A (en) * | 2013-02-25 | 2013-05-22 | 无锡凌湖科技有限公司 | Electro-static discharge (ESD) protection structure between voltage drain drain (VDD) and voltage source source (VSS) under submicron process |
| CN107123977B (en) | 2016-02-24 | 2019-04-19 | 比亚迪股份有限公司 | The driving circuit of transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744842A (en) * | 1996-08-15 | 1998-04-28 | Industrial Technology Research Institute | Area-efficient VDD-to-VSS ESD protection circuit |
| CN1234612A (en) * | 1998-05-01 | 1999-11-10 | 摩托罗拉公司 | Substrate-triggering type electrostatic discharge protective semiconductor and method thereof |
| CN1979842A (en) * | 2005-12-01 | 2007-06-13 | 上海华虹Nec电子有限公司 | Electrostatic discharging protection circuit triggered by lining-bottom |
| US7233475B1 (en) * | 2006-02-16 | 2007-06-19 | Novatek Microelectronics Corp. | Integrated circuit with an electrostatic discharge protection circuit |
-
2008
- 2008-04-17 CN CN2008100936228A patent/CN101562334B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744842A (en) * | 1996-08-15 | 1998-04-28 | Industrial Technology Research Institute | Area-efficient VDD-to-VSS ESD protection circuit |
| CN1234612A (en) * | 1998-05-01 | 1999-11-10 | 摩托罗拉公司 | Substrate-triggering type electrostatic discharge protective semiconductor and method thereof |
| CN1979842A (en) * | 2005-12-01 | 2007-06-13 | 上海华虹Nec电子有限公司 | Electrostatic discharging protection circuit triggered by lining-bottom |
| US7233475B1 (en) * | 2006-02-16 | 2007-06-19 | Novatek Microelectronics Corp. | Integrated circuit with an electrostatic discharge protection circuit |
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| CN101562334A (en) | 2009-10-21 |
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