CN103117280A - Electro-static discharge (ESD) protection structure between voltage drain drain (VDD) and voltage source source (VSS) under submicron process - Google Patents
Electro-static discharge (ESD) protection structure between voltage drain drain (VDD) and voltage source source (VSS) under submicron process Download PDFInfo
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- CN103117280A CN103117280A CN201310059137XA CN201310059137A CN103117280A CN 103117280 A CN103117280 A CN 103117280A CN 201310059137X A CN201310059137X A CN 201310059137XA CN 201310059137 A CN201310059137 A CN 201310059137A CN 103117280 A CN103117280 A CN 103117280A
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Abstract
The invention discloses an electro-static discharge (ESD) protection structure between voltage drain drain (VDD) and voltage source source (VSS) under a submicron process. The ESD protection structure comprises a resistance-capacitance (RC) detection circuit and an N type STFOD device, wherein the RC detection circuit is formed by a resistor, a capacitor and an inverter composed of a p-channel metal oxide semiconductor (PMOS) and an n-channel metal oxide semiconductor (NMOS). An output end of the inverter of the RC detection circuit is connected to a back gate substrate of the N type STFOD device. Not only is the RC coupling characteristic of gate-couple metal oxide semiconductor (GCMOS) combined, but also the characteristic of parasitic NPN bypass ESD discharge current of a grounded-gate metal oxide semiconductor (GGMOS) is utilized. A function of protecting integrated circuit (IC) internal circuits is achieved, only extremely small layout area is occupied simultaneously, and accordingly cost of IC products is reduced.
Description
Technical field
The invention belongs to integrated circuit ESD guard technology, particularly a kind of being applicable under the sub-micron processing procedure, have high ESD strangulation ability and save the VDD of layout area and the ESD protection circuit between VSS.
Background technology
ESD(Electro-Static discharge, static discharges) be formed since mid-term in 20th century with the generation of research static and the science of decay, static discharge model, static discharge effect and galvanomagnetic effect.Be accompanied by the development of integrated circuit, integrated circuit ESD guard technology has obtained increasing attention.
In manufacturing process in early days, resistance, diode, NPN triode, thin grid oxygen transistor etc. can be used for realizing the protection of ESD.GGMOS(Gate-Gnd MOS) etc. GCMOS(Gate-Couple MOS since entering 21 century), technology becomes the major technique of integrated circuit ESD protection.For the manufacturing process more than 0.5um, it is feasible using the ESD guard technologies such as GCMOS, GGMOS.But for the manufacturing process of development, above-mentioned ESD safeguard structure just becomes unrealistic when it develops into the sub-micron processing procedure.Because for GCMOS and GGMOS, often can not use the layout spacing of minimum for these devices of reason of self-shield, to promote it to the ability to bear of ESD.Circuit under the sub-micron processing procedure, the layout area of these ESD structures will be very large like this, and this has increased the cost of IC product to a great extent.
The NMOS component size of ESD voltage is too large in view of being used under the sub-micron processing procedure between strangulation VDD and VSS power line, make this safeguard structure become unrealistic to the sub-micron processing procedure, a kind of ESD safeguard structure that takies very little layout area just becomes a kind of exigence.
Summary of the invention
The invention provides the ESD safeguard structure between VDD and VSS under a kind of sub-micron processing procedure; ESD between effective VDD and VSS strangulation can be provided; reach the function of protection IC internal circuit, this ESD structure only takies very little layout area simultaneously, saves the cost of IC product.
Technical scheme of the present invention is as follows:
ESD safeguard structure under a kind of sub-micron processing procedure between VDD and VSS comprises by resistance, electric capacity and the RC circuit for detecting that the inverter that is comprised of PMOS and NMOS consists of, and a N-type STFOD device; At the bottom of the inverter output of described RC circuit for detecting is connected to the back of the body grid base of described N-type STFOD device by a P+ diffusion region.
Its further technical scheme is: the grid of described N-type STFOD device is positioned on the thick oxide layer of place.
Its further technical scheme is: the grid of described N-type STFOD device is connected to VSS.
Its further technical scheme is: have the P+ diffusion region ring that is connected to VSS outside the source N+ diffusion region of described N-type STFOD device.
Its further technical scheme is: the below, source N+ diffusion region of described N-type STFOD device has the N well construction.
Its further technical scheme is: described N-type STFOD device is annular closing structure.
Useful technique effect of the present invention is:
The present invention adopts the RC circuit for detecting to add that the STFOD(matrix triggers N-type thick oxide layer device) element is as esd protection structure.This composite construction not only combines the RC coupling characteristics of GCMOS, and has utilized the characteristic of the parasitic NPN bypass esd discharge electric current of GGMOS.Reached the function of protection IC internal circuit, only taken very little layout area simultaneously, thereby saved the cost of IC product.
The advantage that the present invention adds provides in embodiment description partly below, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Fig. 1 is circuit theory diagrams of the present invention.
One of Fig. 2 is the structural representation of the STFOD device in the present invention.
Fig. 3 is the structural representation of the STFOD device in the present invention, two.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further.
The structure explanation
As shown in Figure 1, the present invention adds that by resistance R and capacitor C an inverter that is comprised of PMOS and NMOS has consisted of circuit for detecting of the present invention.The present invention utilizes a N-type STFOD device to come bypass esd discharge electric current.Therefore the present invention is that the RC circuit for detecting is in conjunction with the composite construction of a N-type STFOD device.
STFOD device in the present invention is designed to utilize parasitic BJT to come bypass esd discharge electric current, in order better to realize the characteristic of this BJT, requires the STFOD device to have shorter channel length.
For the ability of anti-ESD, because STFOD does not contain LDD(Lightly Doped Drain, lightly doped drain) structure, and trigger bypass ESD electric current by matrix.STFOD does not have weak Surface L DD structure like this, and the ESD electric current is by body portion but not concentrate on the device surface part.Therefore STFOD has better anti-ESD ability than GGMOS and the GCMOS of thin oxide layer.
Under general manufacturing process, generally in the 18V left and right, as shown in Figure 2, in the present invention, the grid of STFOD are connected on VSS the conducting voltage of STFOD, mainly for following some consideration.
First: if the grid of STFOD are linked on VDD, when ESD voltage appears on VDD, because the effect of resistance substrate below prime circuit for detecting and B point causes late effect, may cause parasitic NPN pipe to open the conducting that lags behind STFOD, because the grid of STFOD are directly connected to above VDD.The junction depth of these diffusions is superficial in the manufacturing process of sub-micron, and the layout area that the source leakage is adopted is smaller, these situations can make larger ESD electric current all concentrate in the very little scope in surface, thereby cause the perforation phenomenon that the silicon face local overheating causes and melt the silicon phenomenon.
Second: in order to realize better BJT characteristic, the STFOD device has shorter channel length, and namely the C zone in Fig. 2 is very little.If being connected to the concentration that can make how sub-hole, C region surface place on VDD, reduce the grid of STFOD.Because the drain terminal of STFOD is connected on VDD, form depletion region like this between drain terminal and substrate C zone.Hole concentration reduction due to the C zone, depletion region can seriously be charged into to the low side of concentration, the C zone is often very little under the submicrometer processing processing procedure, short circuit is leaked in the source that may cause due to the voltage fluctuation on VDD STFOD when circuit works of seriously charging into of depletion region, and namely VDD leaks electricity to VSS.
In sum, the grid with STFOD is connected on VSS and can addresses the above problem.
Operation principle
Below in conjunction with Fig. 1 and Fig. 2, operation principle of the present invention is described.
(1) there is ESD voltage to appear at the situation of VDD.
Before the ESD voltage-drop loading was to the VDD power line, the initial voltage of A point in Fig. 1 was 0 volt.When ESD voltage appeared on the VDD power line, related experiment showed that the rate of climb of ESD voltage is very fast, and the rise time is in the 10ns left and right.Within the so short time, on the upper vdd line that the current potential that A is ordered can't be followed due to the delayed action of resistance R and capacitor C, the rate of climb of ESD voltage, cause the current potential that A is ordered still to remain on 0 volt of starting voltage like this.And the low-voltage that A is ordered makes the current potential that B is ordered rise to high potential by means of the ESD voltage on vdd line through the effect of one-level inverter later (A point low-voltage is opened the PMOS pipe).
Because B point zone is the base of STFOD device parasitic NPN pipe, and the emitter region of this NPN pipe namely the source of STFOD be connected to VSS and get on.When B point current potential rises to high potential, NPN pipe for parasitism will form a forward bias between its base and emitter region, this NPN pipe will conducting when Vbe reaches 0.7 volt, thereby makes the ESD voltage on the vdd line that is connected to NPN pipe collector region be released.
Because this ESD electric current is that NPN pipe by STFOD device parasitism comes bypass, and it is not the surface that concentrates on device.So occupying the anti-ESD ability that can provide very high in very little layout area situation.Due to less layout area, can satisfy like this application requirements of high density, high integration under the submicrometer processing processing procedure simultaneously, greatly reduce the cost of product.
(2) VDD situation about normally powering on (occurring without ESD voltage).
The present invention is based on ESD voltage and appears at and design in situation on the VDD power line, and this esd protection structure should be idle in the situation that VDD normally powers on, otherwise will cause the short circuit electric leakage between VDD and VSS.
When circuit did not power on, the starting voltage that A is ordered was still 0 volt.When VDD began to power on, the power-on time of general VDD was in the 1ms left and right, and the rise time of ESD is in the 10ns left and right.In view of difference the present invention of this two rise time is arranged on the 0.1us left and right with the time constant RC of ESD circuit for detecting, just be easy to identify by such this circuit for detecting that arranges that the VDD power line normally powers on and the esd discharge both of these case.
Under the normal electrifying condition of VDD, the vdd voltage rise time is in the 1ms left and right.Because the time constant of RC circuit for detecting is arranged on the 0.1us left and right, so the current potential that A is ordered is almost along with supply voltage rises simultaneously.The inverter (A point high voltage is opened the NMOS pipe) that the potential rise that A is ordered acts on rear one-level makes the current potential that B is ordered be clamped at very low level, substantially near VSS voltage.The electronegative potential that B is ordered makes the parasitic NPN pipe BE knot can not positively biased, and NPN pipe that like this should parasitism is in the situation that VDD normally powers on is to keep the state of closing.
STFOD designs main points
In the present invention, the design of N-type STFOD device seems particularly important, because the ESD electric current comes bypass by this device.Describe below in conjunction with Fig. 3.
P+ diffusion region in Fig. 3 below the B point is connected to the output of the inverter of RC circuit for detecting, and what annular was surrounded the P+ diffusion region is N+ diffusion region (drain terminal of STFOD device), and this N+ diffusion region is connected on the VDD power line.What annular was surrounded the N+ diffusion region is another N+ diffusion region (source of STFOD device), and this N+ diffusion region is connected on the VSS ground wire.Outermost one deck P+ diffusion region ring is connected to VSS, and the base bias effect of parasitic NPN pipe is provided.
When the RC circuit for detecting detected ESD voltage, the potential rise that B is ordered flowed to substrate thereby cause the P+ diffusion region of electric current below the B point.Due to the effect of resistance substrate Rs in Fig. 3, form a forward bias between the base of parasitic NPN pipe and emitter region.
When the source of this STFOD device of design, designed a N well below the N+ diffusion region.Because the darker junction depth of N well has effectively stopped the electric current that the B point injects to substrate, thereby guide this current direction N well area.Namely parasitic NPN manages the base has electric current to inject the emitter region.
In sum, between the base of NPN pipe and emitter region, forward bias is arranged, and the base there is electric current to inject the emitter region, thereby makes this NPN pipe conducting.The ESD electric current that is connected to like this on the vdd line of collector region just can flow into VSS thus.
The layout design main points
Main points one: during design STFOD device, drain terminal is connected to the VDD power line.For the design of drain terminal, require the drain terminal contact hole enough large apart from the spacing d of grid, because when esd discharge, meeting is a large amount of electric current of abrupt release at grid with in the passage between leaking.That only has spacing d design rationally could satisfy this device and have anti-ESD ability preferably.
Main points two: the P+ diffusion region under the manufacturing process of sub-micron below the B point is large to the spacing d of the ratio drain terminal pitch-row grid that the spacing L of STFOD drain terminal N+ diffusion region will design.Preferably L is designed between 1.5 times to 2 times of d.
Main points three: the drain terminal of STFOD device and source perforate are many as much as possible, prevent that esd discharge from postponing and then initiation perforation phenomenon.
Main points four: the aluminum steel of the drain terminal connection VDD power line of STFOD device is enough wide, in order to bear larger ESD electric current.And aluminum steel bag hole is enough large.
Above-described is only the preferred embodiment of the present invention, the invention is not restricted to above embodiment.Be appreciated that other improvement and variation that those skilled in the art directly derive without departing from the basic idea of the present invention or associate, all should think be included in protection scope of the present invention within.
Claims (6)
1. the ESD safeguard structure between VDD and VSS under a sub-micron processing procedure, is characterized in that comprising by resistance, electric capacity and the RC circuit for detecting that the inverter that is comprised of PMOS and NMOS consists of, and a N-type STFOD device; At the bottom of the inverter output of described RC circuit for detecting is connected to the back of the body grid base of described N-type STFOD device by a P+ diffusion region.
2. the ESD safeguard structure between VDD and VSS under the sub-micron processing procedure according to claim 1, it is characterized in that: the grid of described N-type STFOD device is positioned on the thick oxide layer of place.
3. the ESD safeguard structure between VDD and VSS under the sub-micron processing procedure according to claim 1, it is characterized in that: the grid of described N-type STFOD device is connected to VSS.
4. the ESD safeguard structure between VDD and VSS under the sub-micron processing procedure according to claim 1 is characterized in that: have the P+ diffusion region ring that is connected to VSS outside the source N+ diffusion region of described N-type STFOD device.
5. the ESD safeguard structure between VDD and VSS under the sub-micron processing procedure according to claim 1, it is characterized in that: the below, source N+ diffusion region of described N-type STFOD device has the N well construction.
6. the ESD safeguard structure between VDD and VSS under the sub-micron processing procedure according to claim 1, it is characterized in that: described N-type STFOD device is annular closing structure.
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| CN201310059137XA CN103117280A (en) | 2013-02-25 | 2013-02-25 | Electro-static discharge (ESD) protection structure between voltage drain drain (VDD) and voltage source source (VSS) under submicron process |
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| CN201310059137XA CN103117280A (en) | 2013-02-25 | 2013-02-25 | Electro-static discharge (ESD) protection structure between voltage drain drain (VDD) and voltage source source (VSS) under submicron process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878416A (en) * | 2018-06-28 | 2018-11-23 | 武汉新芯集成电路制造有限公司 | ESD protection circuit |
| CN109814650A (en) * | 2019-01-23 | 2019-05-28 | 西安交通大学 | A kind of low pressure difference linear voltage regulator clamping transistor structure |
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| US5744842A (en) * | 1996-08-15 | 1998-04-28 | Industrial Technology Research Institute | Area-efficient VDD-to-VSS ESD protection circuit |
| CN1234612A (en) * | 1998-05-01 | 1999-11-10 | 摩托罗拉公司 | Substrate-triggering type electrostatic discharge protective semiconductor and method thereof |
| US20040218322A1 (en) * | 2003-05-02 | 2004-11-04 | Industrial Technology Research Institute | ESD protection circuits for mixed-voltage buffers |
| CN1979842A (en) * | 2005-12-01 | 2007-06-13 | 上海华虹Nec电子有限公司 | Electrostatic discharging protection circuit triggered by lining-bottom |
| CN101562334A (en) * | 2008-04-17 | 2009-10-21 | 盛群半导体股份有限公司 | Power supply control circuit for electro-static discharge (ESD) protection |
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2013
- 2013-02-25 CN CN201310059137XA patent/CN103117280A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744842A (en) * | 1996-08-15 | 1998-04-28 | Industrial Technology Research Institute | Area-efficient VDD-to-VSS ESD protection circuit |
| CN1234612A (en) * | 1998-05-01 | 1999-11-10 | 摩托罗拉公司 | Substrate-triggering type electrostatic discharge protective semiconductor and method thereof |
| US20040218322A1 (en) * | 2003-05-02 | 2004-11-04 | Industrial Technology Research Institute | ESD protection circuits for mixed-voltage buffers |
| CN1979842A (en) * | 2005-12-01 | 2007-06-13 | 上海华虹Nec电子有限公司 | Electrostatic discharging protection circuit triggered by lining-bottom |
| CN101562334A (en) * | 2008-04-17 | 2009-10-21 | 盛群半导体股份有限公司 | Power supply control circuit for electro-static discharge (ESD) protection |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878416A (en) * | 2018-06-28 | 2018-11-23 | 武汉新芯集成电路制造有限公司 | ESD protection circuit |
| CN109814650A (en) * | 2019-01-23 | 2019-05-28 | 西安交通大学 | A kind of low pressure difference linear voltage regulator clamping transistor structure |
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Application publication date: 20130522 |