CN114220811A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN114220811A
CN114220811A CN202110855772.3A CN202110855772A CN114220811A CN 114220811 A CN114220811 A CN 114220811A CN 202110855772 A CN202110855772 A CN 202110855772A CN 114220811 A CN114220811 A CN 114220811A
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layer
gate
breakdown
well
source
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CN202110855772.3A
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廖忠志
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明实施例提出一种半导体装置如金属氧化物半导体场效晶体管。半导体装置包括基板与井位于基板上，且井包括一第一导电型态的掺质。井包括抗击穿层于井的上侧部分，抗击穿层包括第一导电型态的掺质且还包括碳。金属氧化物半导体场效晶体管还包括源极结构与漏极结构以与抗击穿层相邻且为第二导电型态，且第二导电型态与第一导电型态相反。金属氧化物半导体场效晶体管还包括多个通道层于抗击穿层上，并连接源极结构至漏极结构，其中通道层彼此垂直堆叠。金属氧化物半导体场效晶体管包括栅极以包覆每一通道层(如全绕式栅极装置中的每一通道层)，其中栅极的第一部分位于通道层的最底层以及抗击穿层之间。

Description

半导体装置
技术领域
本发明实施例涉及半导体装置与其制作方法，尤其涉及全绕式栅极装置如垂直堆叠的全绕式栅极的水平纳米线或纳米片的金属氧化物半导体场效晶体管。
背景技术
电子产业已经历对更小且更快的电子装置的需求持续成长，且这些电子装置可同时支持大量的复杂功能。为了符合这些需求，集成电路产业中的持续趋势为制造低成本、高效能与低能耗的集成电路。达成这些目标的主要方法微减少集成电路尺寸(比如最小的集成电路结构尺寸)，以改善产能并降低相关成本。然而这些缩小尺寸的方法亦增加集成电路制造工艺的复杂度。因此集成电路的制造工艺与技术亦须类似发展，以实现集成电路装置与其效能的持续进展。
近来已导入多栅极装置已改善栅极控制。多栅极装置可增加栅极-通道耦合、降低关闭状态电流及/或减少短通道效应。多栅极装置之一为全绕式栅极装置，其可视作垂直堆叠的水平取向的多通道晶体管，比如纳米线晶体管与纳米片晶体管。全绕式栅极装置可大幅缩小集成电路的技术尺寸、维持栅极控制、并缓解短通道效应，且可无缝整合至公知的集成电路制造工艺。然而全绕式栅极装置亦面临挑战。挑战之一为如何控制栅极未完全围绕的半导体层(如最底部的纳米片或纳米线之下的半导体层)中的漏电流。综上所述，虽然现有的全绕式栅极装置与其制作方法通常符合其发展目的，但无法完全符所有方面的需求。
发明内容
本发明实施例的目的在于提出一种半导体装置，以解决上述至少一个问题。
在本发明一例中，关于半导体装置如金属氧化物半导体场效晶体管，其包括基板；第一井位于基板上，且第一井包括第一导电型态的掺质。第一井包括第一抗击穿层，位于第一井的上侧部分，且第一抗击穿层包括第一导电型态的掺质且还包括碳。半导体装置还包括源极结构与漏极结构，与第一抗击穿层相邻且为第二导电型态，且第二导电型态与第一导电型态相反。半导体装置还包括多个通道层，位于第一抗击穿层上并连接源极结构至漏极结构，其中通道层彼此垂直堆叠。半导体装置还包括栅极，包覆每一通道层(如全绕式栅极装置中的通道层)，其中栅极的第一部分位于通道层的最底层以及第一抗击穿层之间。
在另一例中，半导体装置包括基板；第一井，位于完全掺杂n型掺质与碳的基板上，且第一井包括第一抗击穿层于第一井的上侧部分；以及第二井，位于完全掺杂p型掺质与碳的基板上，且第二井包括第二抗击穿层于第二井的上侧部分。半导体装置还包括第一源极结构与第一漏极结构，位于第一抗击穿层上并包含p型掺质；以及第二源极结构与第二漏极结构，位于第二抗击穿层上并包含n型掺质。半导体装置包括第一组多通道层，悬空于第一抗击穿层上并连接第一源极结构至第一漏极结构，其中第一组多通道层彼此垂直堆叠；以及第二组多通道层，悬空于第二抗击穿层上并连接第二源极结构至第二漏极结构，其中第二组多通道层彼此垂直堆叠。半导体装置还包括高介电常数的介电层与金属栅极，包覆第一组多通道层与第二组多通道层的每一者的三侧。半导体装置包括多个内侧介电间隔物，位于高介电常数的介电层与金属栅极以及第一源极结构、第二源极结构、第一漏极结构与第二漏极结构之间；以及顶部介电层，位于高介电常数的介电层与金属栅极的侧壁之上以及第一组多通道层的最顶层与第二组多通道层的最顶层之上。
在另一例中，半导体装置包括基板；第一井，位于完全掺杂n型掺质的基板上，且第一井包括第一抗击穿层于掺杂碳的第一井的上侧部分，其中第一抗击穿层以外的第一井中实质上无碳；以及第二井，位于完全掺杂p型掺质的基板上，且第二井包括第二抗击穿层于掺杂碳的第二井的上侧部分，其中第二抗击穿层以外的第二井中实质上无碳。半导体装置还包括第一源极结构与第一漏极结构，位于第一抗击穿层上并包含p型掺质；以及第二源极结构与第二漏极结构，位于第二抗击穿层上并包含n型掺质。半导体装置包括第一组多通道层，悬空于第一抗击穿层上并连接第一源极结构至第一漏极结构，其中第一组多通道层彼此垂直堆叠；以及第二组多通道层，悬空于第二抗击穿层上并连接第二源极结构至第二漏极结构，其中第二组多通道层彼此垂直堆叠。半导体装置还包括高介电常数的介电层与金属栅极，包覆第一组多通道层与第二组多通道层的每一者的三侧。半导体装置亦包括多个内侧介电间隔物，位于高介电常数的介电层与金属栅极以及第一源极结构、第二源极结构、第一漏极结构与第二漏极结构之间；以及顶部介电层，位于高介电常数的介电层与金属栅极的侧壁之上以及第一组多通道层的最顶层与第二组多通道层的最顶层之上。
附图说明
图1为本发明一实施例中，全绕式栅极装置的布局俯视图。
图2A及图3A分别为本发明一些实施例中，图1中的全绕式栅极装置的部分沿着切线cut-1与切线cut-2的剖视图。
图2B及图3B分别为本发明一些其他实施例中，图1中的全绕式栅极装置的部分沿着切线cut-1与切线cut-2的剖视图。
图4为本发明一些实施例中，图1中的全绕式栅极装置的部分沿着切线cut-3的剖视图。
图5为本发明一些实施例中，制作全绕式栅极装置的方法的流程图。
图6A及图7A为本发明一些实施例中，图5的方法的中间步骤所形成的图1的全绕式栅极装置的部分剖视图。
图6B及图7B为本发明一些其他实施例中，图5的方法的中间步骤所形成的图1的全绕式栅极装置的部分剖视图。
附图标记如下：
cut-1,cut-2,cut-3:切线
C:碳
d1,d2,d3,d4,d5,d6:深度
Lg:栅极长度
S1,S2:空间
T1,T2:厚度
W1,W2:宽度
X:半导体材料
200:装置
202:基板
204,204N,204P:井
206,206N,206P:抗击穿层
210:半导体层
215:通道层
230:隔离结构
240:栅极堆叠
247,255:栅极间隔物
260,260N,260P:源极/漏极结构
261:硅化物结构
262:轻掺杂源极/漏极区
270:层间介电层
282:栅极介电层
284N,284P:功函数金属层
350:金属填充层
404:栅极末端介电结构
406:源极/漏极接点
408:栅极顶部介电层
410:栅极通孔
411N,411P:漏极通孔
412N,412P:源极通孔
416:硬掩模层
500:方法
502,504,506,508,510:步骤
具体实施方式
下述详细描述可搭配附图说明，以利理解本发明的各方面。值得注意的是，各种结构仅用于说明目的而未按比例绘制，如本业常态。实际上为了清楚说明，可任意增加或减少各种结构的尺寸。
下述内容提供的不同实施例或实例可实施本发明的不同结构。下述特定构件与排列的实施例是用以简化本发明内容而非局限本发明。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触的实施例，或两者之间隔有其他额外构件而非直接接触的实施例。此外，本发明的多个实例可重复采用相同标号以求简洁，但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外，空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。此外，当数值或数值范围的描述有“约”、“近似”或类似用语时，除非特别说明否则其包含所述数值的+/-10％。举例来说，用语“约5nm”包含的尺寸范围为4.5nm至5.5nm、4.0nm至5.0nm或类似范围。
本发明实施例关于半导体装置与其制作方法，还特别关于全绕式栅极装置如垂直堆叠的全绕式栅极的水平纳米线或纳米片的金属氧化物半导体场效晶体管，其具有极窄的圆形或片状通道主体。全绕式栅极装置因良好的栅极控制能力、较低的漏电流、尺寸缩小能力与鳍状场效晶体管装置的布局相容性而前景看好。然而全绕式栅极装置的多种方面仍须改善。举例来说，一些实施方式中最底部的通道层之下的半导体层位于源极与漏极之间。围绕最底部的通道层的栅极的部分亦位于此半导体层上，造成穿过此半导体层的导电通道，如平面晶体管。此平面的导电通道可能带来困难。举例来说，临界电压不匹配纳米线或纳米片的通道，而穿过半导体层的漏电流会造成一些应用的问题。举例来说，在待机模式(或非有源模式)的装置中，这些漏电流会直接造成额外能耗。本发明实施例的一般目的为提供抗击穿掺杂于此半导体层中(视作抗击穿层)，以减少漏电流。控制抗击穿层的掺杂浓度，使其高到足以抑制漏电流，并低到足以在抗击穿离子注入与后续的热工艺时最小化扩散至通道层中的掺质。在一些实施例中，对源极端、漏极端与井(p型井或n型井)施加适当的偏电压可结合抗击穿层，以减少漏电流。本发明一些实施例的结构与制作方法的细节将搭配附图说明如下，其显示全绕式栅极装置与其制造工艺。本技术领域中技术人员应理解采用本发明实施例作为基础，可设计或调整其他工艺与结构以执行相同目的及/或达到此次所述的实施例的相同优点。
图1、图2A、图2B、图3A、图3B及图4为本发明一些实施例中，全绕式栅极装置200的附图。图1为装置200在X-Y平面中的俯视图。图2A、图2B、图3A、图3B及图4分别为图1中的全绕式栅极装置的部分沿着切线cut-1、切线cut-2与切线cut-3的剖视图。
在一些实施例中，装置200可包含于微处理器、存储器及/或其他集成电路装置中。在一些实施例中，装置200为集成电路芯片、单芯片系统或其部分，其可包含多种无源与有源微电子装置如电阻、电容器、电感、二极管、p型场效晶体管、n型场效晶体管、鳍状场效晶体管、纳米片场效晶体管、纳米线场效晶体管、其他种类的多栅极场效晶体管、金属氧化物半导体场效晶体管、互补式金属氧化物半导体场效晶体管、互补式金属氧化物半导体晶体管、双极接面晶体管、横向扩散金属氧化物半导体晶体管、高电压晶体管、高频晶体管、存储器装置、其他合适构件或上述的组合。已简化图1至图4使附图清楚，以利理解本发明实施例的发明概念。可添加额外结构至装置200中，且装置200的其他实施例可置换、调整或省略一些下述结构。
如图1、图2A、图2B、图3A、图3B及图4所示，装置200包括基板202与多个井(如n型井204N与p型井204P)形成于基板202之中或之上。提供抗击穿层206N于n型井204N的顶部中，并提供抗击穿层206P于p型井204P的顶部中。通道层215的堆叠位于抗击穿层206N上，而通道层215的另一堆叠位于抗击穿层206P上。通道层215的长度方向沿着y方向，而宽度方向沿着x方向。装置200还包括栅极堆叠240(如高介电常数的介电层与金属栅极的堆叠)，其长度方向沿着x方向并接合通道层215以形成全绕式栅极晶体管。具体而言，每一栅极堆叠240包覆个别通道层215。装置200还包括栅极间隔物247位于栅极堆叠240的侧壁上，以及栅极末端介电结构404位于每一栅极堆叠240的两端。装置200还包括接点位于相邻的栅极间隔物247与多种通孔(如源极通孔412N及412P、漏极通孔411N及411P与栅极通孔410)之间的源极/漏极区上。接点与通孔可适当地耦接至多种电压或信号线。
在一实施例中，基板202包含硅如硅晶片。基板202可改为或额外包含另一半导体元素如锗、半导体化合物(如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟)、半导体合金(如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟及/或磷砷化镓铟)或上述的组合。基板202可改为绝缘层上半导体基板，比如绝缘层上硅基板、绝缘层上硅锗基板或绝缘层上锗基板。绝缘层上半导体基板的制作方法可采用分离注入氧、晶片接合及/或其他合适方法。
在此实施例中，p型井204P与n型井204N包括的半导体材料可与基板202相同。p型井204P可进一步掺杂p型掺质如硼、铟、其他p型掺质或上述的组合，以设置为用于n型全绕式栅极晶体管。n型井204N更掺杂n型掺质如磷、砷、其他n型掺质或上述的组合，以设置为用于p型全绕式栅极晶体管。在一些实施方式中，井204N由p型掺质与n型掺质的组合所形成，但净效应为n型掺杂。在一些实施方式中，井204P由p型掺质与n型掺质的组合所形成，但净效应为p型掺杂。多种掺杂区可直接形成于基板202之上及/或之中，且其形成方法可为离子注入工艺、扩散工艺及/或其他合适的掺杂工艺。
如图2A及图2B所示，装置200还包括n型掺杂的源极/漏极结构260N位于p型井204P上以形成n型金属氧化物半导体全绕式栅极晶体管。如图3A及图3B所示，p型掺杂的源极/漏极结构260P位于n型井204N以形成p型金属氧化物半导体全绕式栅极晶体管。源极/漏极结构260N与260P的形成方法可采用外延成长。举例来说，自基板202、井204(如井204N及204P)、抗击穿层206(如抗击穿层206N及206P)与半导体层210及通道层215的部分外延成长半导体材料(见图6A、图6B、图7A及图7B)，以形成外延的源极/漏极结构260N及260P。外延工艺可采用化学气相沉积技术(比如气相外延及/或超高真空化学气相沉积)、分子束外延、其他合适的外延成长工艺或上述的组合。外延工艺可采用气态及/或液态前驱物，其可与基板202、井204P及240N与通道层215的组成作用。在一些实施例中，外延源极/漏极结构260N可包含硅，且可掺杂碳、磷、砷、其他n型掺质或上述的组合(比如形成碳化硅的外延源极/漏极结构、磷化硅的外延源极/漏极结构或碳磷化硅的外延源极/漏极结构)。在一些实施例中，外延的源极/漏极结构260P可包含硅锗或锗，且可掺杂硼、其他p型掺质或上述的组合(比如形成硼化硅锗的外延源极/漏极结构)。在一些实施例中，外延的源极/漏极结构260N及/或260P包含超过一个外延半导体层，其中外延半导体层可包含相同或不同的材料及/或掺质浓度。在一些实施例中，外延的源极/漏极结构260N及/或260P包含的材料及/或掺质，可达全绕式栅极晶体管的个别通道层中的所需的拉伸应力及/或压缩应力。在一些实施例中，在沉积时添加杂质至外延工艺的源材料，以原位掺杂外延的源极/漏极结构260N及260P。在一些实施例中，可在沉积工艺之后以离子注入工艺掺杂外延的源极/漏极结构260N及260P。在一些实施例中，进行退火工艺(如快速热退火及/或激光退火)，以活化外延的源极/漏极结构260N及260P中的掺质。在一些实施例中，在分开的工艺顺序中形成外延的源极/漏极结构260N及260P，包括在形成外延的源极/漏极结构260N于n型金属氧化物半导体全绕式栅极晶体管区中时掩模p型金属氧化物半导体全绕式栅极晶体管区，并在形成外延的源极/漏极结构260P于p型金属氧化物半导体全绕式栅极晶体管区中时掩模n型金属氧化物半导体全绕式栅极晶体管区。
通道层215的第一堆叠悬空于每一对源极/漏极结构260N之间，而通道层215的另一堆叠悬空于每一对源极/漏极结构260P之间。通道层215的堆叠可作为个别全绕式栅极装置所用的晶体管通道。综上所述，通道层215亦可视作半导体层。通道层215可包含硅锗。在其他实施例中，通道层215可包含硅、锗、硅锗或另一合适的半导体材料。在此实施例中，通道层215未掺杂或实质上不含抗击穿层206N及206P中的掺质。在其他实施例中，通道层215可掺杂非常低浓度的掺质。举例来说，通道层215中的掺质浓度可低于约5E16原子/cm3。通道层215一开始可形成为含有通道层215与半导体层210的一部分，见图6A、图6B、图7A及图7B。在栅极置换工艺时，可选择性蚀刻半导体层堆叠以移除牺牲半导体层，并保留通道层215以悬空于基板202之上与个别源极/漏极结构260N及260P之间。
如图2A及图2B所示的多种实施例，n型的源极/漏极结构260N延伸低于抗击穿层206P的上表面(其亦为井204P的上表面)的距离为深度d1。在一些实施例中，深度d1为约5nm至约25nm。在这些实施例中，抗击穿层206P具有自抗击穿层206P的上表面(其与栅极介电层282交界)测量的深度d2。在一些实施例中，深度d2可高达40nm，比如约5nm至约50nm。在多种实施例中，深度d2小于深度d3。井204P具有自抗击穿层206P(其可视作井204P的部分)的上表面测量的深度d3。在一些实施例中，深度d3可高达300nm，比如约100nm至约400nm。在一些实施例中，井204P的掺质浓度可为约1E16原子/cm3至约1E19原子/cm3，端视井的电阻需求而定。
如图3A及图3B所示的多种实施例，p型源极/漏极结构260P延伸低于抗击穿层206N的上表面(其亦可为井204N的上表面)的距离为深度d4。在一些实施例中，深度d4可为约5nm至约25nm。在一些实施例中，深度d4大于图2A及图2B所示的n型源极/漏极结构的深度d1，比如大至少3nm且较佳在15nm以内。这是因为p型金属氧化物半导体场效晶体管通道迁移率与源极/漏极的外延尺寸相关。较深的源极/漏极可具有较大体积，因此可较强地改善p型金属氧化物半导体场效晶体管离子所用的应力。
抗击穿层206N可具有自抗击穿层206N的上表面(其与栅极介电层282交界)测量的深度d5。在一些实施例中，深度d5可高达40nm，比如约5nm至约50nm。在多种实施例中，深度d5小于深度d4。井204N具有自抗击穿层206N(其可视作井204N的部分)的上表面测量的深度d6。在一些实施例中，深度d6可高达300nm，比如约100nm至约400nm。在一些实施例中，井204N中的掺质浓度可为约1E16原子/cm3至约1E19原子/cm3，端视井的电阻需求而定。
在不同实施例中，掺杂井204P及204N与抗击穿层206P及206N的掺杂可能改变。此实施例之一如图2A及图3A所示。如图2A所示，抗击穿层206P与井204P包含相同的半导体材料(如图式中的半导体材料X)，且可视作p型井204P的部分。此外，抗击穿层206P掺杂碳(如图式中的碳C)。这可由不同方式达成。在一例中，可采用较低能量的注入工艺(比如约10keV至50keV)，以掺杂碳与p型掺质(如硼或铟)至抗击穿层206P。可采用一或多道较高能量的注入工艺(比如注入能量大于50keV的两道注入工艺)，以掺杂p型掺质(如硼、铟或氟化硼)至井204P的其余部分。
如图3A所示，抗击穿层206N包括的半导体材料与井204N相同(如图式中的半导体材料X)，且可视作n型井204N的部分。此外，抗击穿层206N掺杂碳(如图式中的碳C)，其可由多种方式达成如上述。在一例中，可采用较低能量的注入工艺(如约10keV至约50keV)，以掺杂碳与n型掺质(如磷或砷)至抗击穿层206N。可采用一或多道较高能量的注入工艺(比如注入能量大于约50keV的两道注入工艺)，以掺杂n型掺质(如磷或砷)至井204N的其余部分。
掺杂井204P及204N与抗击穿层206P及206N的另一实施例如图2B及图3B所示。如图2B所示，抗击穿层206P与井204P包括相同的半导体材料(如图式中的半导体材料X)，且抗击穿层206P可视作p型井204P的部分。在此实施例中，抗击穿层206P与井204P均掺杂碳(如图式中的碳C)，且可由不同方式达成。在一例中，可采用较低能量的注入工艺(比如约10keV至约50keV)，以掺杂碳与p型掺质(如硼或铟)至抗击穿层206P。可采用一或多道较高能量的注入工艺(如注入能量大于约50keV的两道注入工艺)，以掺杂碳与p型掺质至井204P的其余部分。
如图3B所示，抗击穿层206N包含的半导体材料(如图式中的半导体材料X)可与井204N相同，且可视作n型井204N的部分。在此实施例中，抗击穿层206N与井204N均掺杂碳(如图式中的碳C)，且可由不同方法达成如上述。在一例中，可采用较低能量的注入工艺(比如约10keV至约50keV)，以掺杂碳与n型掺质(如磷或砷)至抗击穿层206N。可采用一或多道较高能量的注入工艺(如注入能量大于约50keV的两道注入工艺)，以掺杂碳与n型掺质至井204N的其余部分。
如图4所示，装置200还包含隔离结构230位于基板202上以与含抗击穿层206N及206P的井204N及204P的上侧部分相邻。隔离结构230可包含氧化硅、氮化硅、氮氧化硅、其他合适的隔离材料(比如含硅、氧、氮、碳或其他合适的隔离组成)或上述的组合。隔离结构230可包含不同结构，比如浅沟槽隔离结构、深沟槽隔离结构及/或局部氧化硅结构。举例来说，隔离结构230可包含浅沟槽隔离结构，以定义并电性隔离掺杂区。在一些实施例中，浅沟槽隔离结构包括多层结构以填入沟槽，比如含氮化硅的层状物位于含热氧化物的衬垫层上。在另一例中，浅沟槽隔离结构包括介电层位于掺杂的衬垫层(如硼硅酸盐玻璃或磷硅酸盐玻璃)上。在又一例中，浅沟槽隔离结构包括基体介电层位于衬垫介电层上，其中基体介电层与衬垫介电层包括的材料取决于设计需求。
如图4所示，n型金属氧化物半导体全绕式栅极装置所用的通道层215彼此沿着z方向隔有空间S1，而p型金属氧化物半导体全绕式栅极装置所用的通道层215彼此沿着z方向隔有空间S2。在所述实施例中，空间S1大致等于空间S2(比如空间S1及S2彼此之间的差异在5％以内)，但本发明实施例所实施的空间S1可与空间S2不同。此外，n型金属氧化物半导体全绕式栅极装置所用的通道层215具有沿着x方向的宽度W1以及沿着z方向的厚度T1，而p型金属氧化物半导体全绕式栅极装置所用的通道层215具有沿着x方向的宽度W2以及沿着z方向的厚度T2。在所述实施例中，厚度T1大致等于厚度T2(比如厚度T1及T2彼此之间的差异在5％以内)，但本发明实施例所实施的厚度T1可与厚度T2不同。在一些实施例中，每一厚度T1及T2可为约4nm至约8nm，且每一空间S1及S2可为约6nm至约15nm。此外，一些实施例中的厚度T1与空间S1的总和(以及厚度T2与空间S2的总和)可为约10nm至约23nm。在一实施例中，宽度W2大致等于宽度W1。在另一实施例中，宽度W2与宽度W1不同，端视设计目的而定。举例来说，宽度W2设计为大于宽度W1，以促进p型金属氧化物半导体场效晶体管的全绕式栅极装置效能。本发明实施例的宽度W1与宽度W2可具有任何设置，比如宽度W1大于、小于或等于宽度W2。在多种实施例中，每一宽度W1及W2可各自为约4nm至约70nm。在一些实施例中，通道层215为圆柱形(如纳米线)、矩形(如纳米棒)、片状(如纳米片)或其他合适形状。在多种实施例中，栅极堆叠240包含栅极介电层282、功函数金属层(如p型金属氧化物半导体全绕式栅极装置所用的功函数金属层284P与n型金属氧化物半导体全绕式栅极装置所用的功函数层284N)、以及低电阻的金属填充层350。如图4所示，一些实施例中的栅极堆叠240可省略低电阻的金属填充层350。p型金属氧化物半导体全绕式栅极装置所用的栅极堆叠240位于一对p型的源极/漏极结构260P之间，而n型金属氧化物半导体全绕式栅极装置所用的栅极堆叠240位于一对n型的源极/漏极结构260N之间。如图1所示，一些栅极堆叠240跨过p型金属氧化物半导体全绕式栅极装置与n型金属氧化物半导体全绕式栅极装置，因此成为p型金属氧化物半导体全绕式栅极装置与n型金属氧化物半导体全绕式栅极装置所用的共同栅极。虽然图1未显示，栅极堆叠240可只接合p型金属氧化物半导体全绕式栅极装置或只接合n型金属氧化物半导体全绕式栅极装置。此外，多种实施例中的栅极堆叠240的宽度(亦可视作栅极长度Lg，其沿着图1中的y方向)可为4nm至30nm。
栅极介电层282包覆每一通道层215。栅极介电层282可包含高介电常数的介电材料如氧化铪、氧化铪硅、硅酸铪、氮氧化铪硅、氧化铪镧、氧化铪钽、氧化铪钛、氧化铪锆、氧化铪铝、氧化锆、二氧化锆、氧化锆硅、氧化铝、氧化铝硅、三氧化二铝、氧化钛、二氧化钛、氧化镧、氧化镧硅、三氧化二钽、五氧化二钽、氧化钇、钛酸锶、氧化钡锆、钛酸钡、钛酸钡锶、氮化硅、氧化铪-氧化铝合金、其他合适的高介电常数的介电材料或上述的组合。高介电常数的介电材料通常指的是介电常数大于氧化硅的介电常数(约3.9)的介电材料。栅极介电层282的形成方法可为化学氧化、热氧化、原子层沉积、化学气相沉积及/或其他合适方法，且其厚度可为约0.5nm至约3nm。在一些实施例中，栅极堆叠240还包括界面层于栅极介电层282与通道层215之间。界面层可包含氧化硅、氮氧化硅或其他合适材料。在一些实施例中，功函数金属层284N包括n型金属氧化物半导体场效晶体管的全绕式栅极装置所用的n型功函数层，且功函数金属层284P包括p型金属氧化物半导体场效晶体管的全绕式栅极装置所用的p型功函数层。举例来说，n型功函数层可包含足够低的有效功函数的金属，比如钛、铝、碳化钽、碳氮化钽、氮化钽硅或上述的组合。举例来说，p型功函数层可包含足够高的有效功函数的金属，比如氮化钛、氮化钽、钌、钼、钨、铂或上述的组合。低电阻的金属填充层350可包含钨、钌、铜及/或其他合适材料，且其形成方法可为化学气相沉积、物理气相沉积、电镀及/或其他合适工艺。由于栅极堆叠240包括高介电常数的介电层与金属层，其亦可视作高介电常数的介电层与金属栅极。低电阻的金属填充层350不形成于垂直地位于最底部的通道层215与抗击穿层206P及206N之间的区域中。
装置200包括栅极间隔物247于栅极堆叠240的侧壁之上与最顶部的通道层215之上，还包括栅极间隔物255于栅极堆叠240的侧壁之上与最顶部的通道层215之下。在本发明实施例中，栅极间隔物247可视作外侧间隔物或顶间隔物，而栅极间隔物255亦可视作内侧间隔物。内侧间隔物如栅极间隔物255横向地位于源极/漏极结构260N(或260P)与栅极堆叠240之间，并垂直地位于通道层215之间。在多种实施例中，顶间隔物如栅极间隔物247沿着y方向的宽度可为约3nm至约12nm，且内侧间隔物如栅极间隔物255沿着y方向的宽度可为约3nm至约12nm。
在此实施例中，装置200还包括轻掺杂源极/漏极区262于通道层215与源极/漏极结构260A及260B(或重掺杂源极/漏极)之间。内侧间隔物如栅极间隔物255可围绕通道层215与源极/漏极结构260N及260P之间的轻掺杂源极/漏极区262，且内侧间隔物255与顶间隔物如栅极间隔物247围绕最顶部的通道层215与源极/漏极结构260N及260P之间的轻掺杂源极/漏极区262。轻掺杂源极/漏极区262可使全绕式栅极装置200增进额外的装置效能(如短通道控制)。
装置200还包含栅极末端介电结构404，其位于栅极堆叠240与顶间隔物如栅极间隔物247的末端。顶间隔物如栅极间隔物247、内侧间隔物如栅极间隔物255与栅极末端介电结构404可提供隔离功能，比如使栅极堆叠240彼此隔离并隔离栅极堆叠240与相邻的导体(包含源极/漏极结构260N及260P与源极/漏极接点406，见图1)。在一实施例中，顶间隔物如栅极间隔物247、内侧间隔物如栅极间隔物255与栅极末端介电结构404的材料彼此不同，且栅极末端介电结构404具有最高的介电常数。在一实施例中，栅极末端介电结构404包括高介电常数的材料，比如氮化硅、含氮的氧化物、含碳的氧化物、介电金属氧化物(如氧化铪、氧化铪硅、硅酸铪、氮氧化铪硅、氧化铪镧、氧化铪钽、氧化铪钛、氧化铪锆、氧化铪铝、氧化锆、二氧化锆、氧化锆硅、氧化铝、氧化铝硅、三氧化二铝、氧化钛、二氧化钛、氧化镧、氧化镧硅、三氧化二钽、五氧化二钽、氧化钇、钛酸锶、氧化钡锆、钛酸钡、钛酸钡锶)、氧化铪-氧化铝合金、其他合适的高介电常数的介电材料或上述的组合。在其他实施例中，内侧间隔物如栅极间隔物255比顶间隔物如栅极间隔物247具有更高的有效介电常数。举例来说，内侧间隔物如栅极间隔物255的材料可包含氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮氧化硅、氮化物为主的介电材料、气隙或上述的组合，而顶间隔物如栅极间隔物247的材料可包含氧化硅、氮化硅、掺杂碳的氧化物、掺杂氮的氧化物、多孔氧化物、气隙或上述的组合。
如图4所示，装置200还包含栅极顶部介电层408位于栅极堆叠240上。在一些实施例中，栅极顶部介电层408的厚度可为约2nm至约60nm。栅极顶部介电层408的材料可包含氧化硅、碳氧化硅、氮氧化硅、碳氮氧化硅、氮化物为主的介电层、介电金属氧化物(如氧化铪、氧化钽、氧化钛、氧化锆、氧化铝或氧化钇)或上述的组合。栅极顶部介电层408的形成方法可为使栅极堆叠240与顶间隔物如栅极间隔物247凹陷以形成沟槽，将一或多种介电材料填入沟槽，并进行化学机械研磨工艺以移除多余的介电材料。
装置200还包括硅化物结构261位于源极/漏极结构260N及260P上，以及源极/漏极接点406位于硅化物结构261上。硅化物结构261的形成方法可为沉积一或多种金属于源极/漏极结构260(如源极/漏极结构260N及260P)上，对装置200进行退火工艺使一或多种金属与源极/漏极结构260之间产生反应以产生硅化物结构261，以及移除一或多种金属的未反应部分。硅化物结构261可包含钛硅化物、镍硅化物、钨硅化物、镍铂硅化物、镍铂锗硅化物、镍锗硅化物、镱硅化物、铂硅化物、铱硅化物、铒硅化物、钴硅化物或其他合适化合物。在一实施例中，源极/漏极接点406可包含导电阻挡层，以及金属填充层位于导电阻挡层上。导电阻挡层可避免金属填充层的金属材料扩散至与源极/漏极接点406相邻的介电层中。导电阻挡层可包含钛、钽、钨、钴、钌或导电氮化物(如氮化钛、氮化钛铝、氮化钨、氮化钽或上述的组合)，且其形成方法可为化学气相沉积、物理气相沉积、原子层沉积及/或其他合适工艺。金属填充层可包含钨、钴、钼、钌或其他金属，且其形成方法可为化学气相沉积、物理气相沉积、原子层沉积、电镀或其他合适工艺。在一些实施例中，源极/漏极接点406中可省略导电阻挡层。
在一些实施例中，硅化物结构261与源极/漏极接点406的形成方法为采用自对准的蚀刻工艺蚀刻源极/漏极接点孔，接着进行上述沉积、退火与其他工艺于接点孔中，以形成硅化物结构261与源极/漏极接点406。自对准的蚀刻工艺采用栅极顶部介电层408、顶间隔物如栅极间隔物247及/或栅极末端介电结构404作为蚀刻掩模。
装置200还包含层间介电层270。层间介电层270位于隔离结构230、源极/漏极接点406与栅极顶部介电层408上。多种结构如源极/漏极结构260、硅化物结构261、源极/漏极接点406、栅极堆叠240、顶间隔物如栅极间隔物247、内侧间隔物如栅极间隔物255、栅极末端介电结构404与栅极顶部介电层408可埋置于层间介电层270中。在一些实施例中，装置200还包括接点蚀刻停止层于层间介电层270与源极/漏极结构260、栅极堆叠240及顶间隔物如栅极间隔物247之间。接点蚀刻停止层可包括氧化镧、氧化铝、碳氮氧化硅、碳氧化硅、碳氮化硅、氧化硅、碳化硅、氧化锌、氮化锆、氧化锆铝、氧化钛、氧化钽、氧化锆、氧化铪、氮化硅、氧化钇、钽氧化铝、碳氮化钽、锆硅化物或其他合适材料，且其形成方法可为化学气相沉积、物理气相沉积、原子层沉积或其他合适方法。层间介电层270可包含四乙氧基硅烷的氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(如硼磷硅酸盐玻璃、氟硅酸盐玻璃、磷硅酸盐玻璃或硼硅酸盐玻璃)、低介电常数的介电材料、其他合适的介电材料或上述的组合。层间介电层270的形成方法可为等离子体辅助化学气相沉积、可流动的化学气相沉积或其他合适方法。
装置200还包括栅极通孔410以电性连接至栅极堆叠240。装置200还包括漏极通孔411N及411P以分别电性连接至源极/漏极结构260N及260P的漏极上的源极/漏极接点406，以及源极通孔412N及412P以分别电性连接至源极/漏极结构260N及260P的源极上的源极/漏极接点406。栅极通孔410、漏极通孔411N及411P与源极通孔412N及412P的每一者可包含导电阻挡层，以及导电阻挡层上的金属填充层。导电阻挡层可避免金属填充层的金属材料扩散至与通孔相邻的介电层中。导电阻挡层可包含钛、钽、钨、钴、钌或导电氮化物(如氮化钛、氮化钛铝、氮化钨或氮化钽或上述的组合)，且其形成方法可为化学气相沉积、物理气相沉积、原子层沉积及/或其他合适工艺。金属填充层可包含钨、钴、钼、钌或其他金属，且其形成方法可为化学气相沉积、物理气相沉积、原子层沉积、电镀或其他合适工艺。在一些实施例中，通孔可省略导电阻挡层。
图5为本发明多种实施例中，制作多栅极装置如装置200的方法500的流程图。本发明实施例可实施额外工艺。可在方法500之前、之中与之后提供额外步骤，且方法500的额外实施例可调换、置换或省略一些所述步骤。
方法500的步骤502可形成井204N于基板202上，亦形成抗击穿层206N。图4所示的结构为一实施例。举例来说，步骤502可形成第一硬掩模以覆盖基板202的n型金属氧化物半导体区并露出基板202的p型金属氧化物半导体区，接着对基板202的p型金属氧化物半导体区进行一或多道离子注入工艺，以形成n型井204N。步骤502可额外掺杂碳至n型井204N的上侧部分，以形成抗击穿层206N，如图3A及图6A所示的下述内容。在其他实施例中，可注入碳于整个n型井204N与抗击穿层206N，如图3B及图6B所示。步骤502可控制前述的n型井204N与抗击穿层206N所用的掺杂深度与掺质浓度，步骤502之后可移除第一硬掩模。
方法的步骤504形成p型井204P于基板202上，且更形成抗击穿层206P。图4所示的结构唯一实施例。举例来说，步骤504可形成第二硬掩模以覆盖基板202的p型金属氧化物半导体区，并露出基板202的n型金属氧化物半导体区。接着步骤504可对基板202的n型金属氧化物半导体区进行一或多道离子注入工艺，以形成p型井204P。步骤504可重掺杂p型井204P的上侧部分，以形成抗击穿层206P。步骤504可额外掺杂碳至p型井204P的上侧部分，以形成抗击穿层206P，如图2A及图7A所示的下述内容。在其他实施例中，可注入碳于整个p型井204P与抗击穿层206P，如图2B及图7B所示的下述内容。步骤504可控制p型井204P与抗击穿层206P的掺杂深度与掺质浓度如前述。步骤504之后可移除第二硬掩模层。
方法500的步骤506形成半导体层堆叠，其具有半导体层210与通道层215自基板202的上表面以交错设置的方式垂直堆叠。图7A及图7B所示的结构依据下方井与抗击穿层的不同实施例。在这些实施例中，以交错的设置外延成长半导体层210与通道层215。举例来说，外延成长通道层215的第一者于基板上、晶成长半导体层210的第一者于通道层215的第一者上、外延成长通道层215的第二者于半导体层210的第一者上、以此类推，直到半导体层堆叠具有所需数目的半导体层210与通道层215。在此实施例中，通道层215为硅锗，而半导体层210为纯硅。其他实施例亦可具有不同设置。在一些实施例中，半导体层210与通道层215的外延成长方法可为分子束外延工艺、化学气相沉积工艺、有机金属化学气相沉积工艺、其他合适的外延成长工艺或上述的组合。
方法500的步骤508可图案化半导体层堆叠成鳍状物，亦可图案化井204的上侧部分成鳍状物。可采用任何合适方法图案化鳍状物。举例来说，可采用一或多道光刻工艺图案化鳍状物，包括双重图案化或多重图案化工艺。一般而言，双重图案化或多重图案化工艺结合光刻与自对准工艺，其产生的图案间距小于采用单一的直接光刻工艺所得的图案间距。举例来说，一实施例形成牺牲层于半导体层堆叠上，并采用光刻工艺图案化半导体层堆叠。采用自对准工艺以沿着图案化的牺牲层侧部形成间隔物。接着移除牺牲层，再采用保留的间隔物或芯作为掩模单元以图案化鳍状物。
步骤508更形成隔离结构230。隔离结构230的形成方法可为将绝缘材料填入鳍状物之间的沟槽，比如采用化学气相沉积工艺或旋转涂布玻璃工艺。可进行化学机械研磨工艺以移除多于的绝缘材料及/或平坦化隔离结构230的上表面。接着进行回蚀刻工艺使隔离结构230凹陷至所需厚度，比如围绕鳍状物的下侧部分但使鳍状物的上侧部分凸起高于隔离结构230。在一些实施例中，化学机械研磨工艺或回蚀刻工艺时可移除硬掩模层416。
方法500的步骤510对装置200进行后续制作工艺，以达图1所示的装置以及最终完成的集成电路。
本发明的一或多个实施例可提供许多优点至半导体装置与其形成方法，但不局限于此。举例来说，本发明实施例提供的结构(如抗击穿层)与方法(如栅极、源极、漏极与井的偏电压方案)可减少全绕式栅极装置中的漏电流。举例来说，结合此处所述的偏电压方案与掺杂碳的抗击穿层，可大幅减少待机模式中的全绕式栅极装置的源极端与漏极端之间的漏电流。公开的结构与方法可轻易整合至现有的半导体制造工艺。
在本发明一例中，关于半导体装置如金属氧化物半导体场效晶体管，其包括基板；第一井位于基板上，且第一井包括第一导电型态的掺质。第一井包括第一抗击穿层，位于第一井的上侧部分，且第一抗击穿层包括第一导电型态的掺质且还包括碳。半导体装置还包括源极结构与漏极结构，与第一抗击穿层相邻且为第二导电型态，且第二导电型态与第一导电型态相反。半导体装置还包括多个通道层，位于第一抗击穿层上并连接源极结构至漏极结构，其中通道层彼此垂直堆叠。半导体装置还包括栅极，包覆每一通道层(如全绕式栅极装置中的通道层)，其中栅极的第一部分位于通道层的最底层以及第一抗击穿层之间。
在一些实施例中，源极结构的下表面相对于基板，比栅极与第一抗击穿层之间的界面深约5nm至约25nm。
在一些实施例中，漏极结构的下表面相对于基板，比栅极与第一抗击穿层之间的界面深约5nm至约25nm。
在一些实施例中，第一抗击穿层比栅极与第一抗击穿层之间的界面低约5nm至约25nm。
在一些实施例中，半导体装置还包括隔离结构位于基板上，以与第一井的上侧部分相邻并与第一抗击穿层相邻。
在一些实施例中，半导体装置还包括：第二井，位于基板上，且第二井包括第二导电型态的掺质；以及第二抗击穿层，位于第二井的上侧部分，且第二抗击穿层包括第二导电型态的掺质且还包括碳。
在一些实施例中，半导体装置还包括：隔离结构，位于基板上以与第一井与第二井的上侧部分相邻，并与抗击穿层相邻。
在一些实施例中，多通道组件为外延成长的硅锗。
在一些实施例中，第一井完全掺杂碳。
在一些实施例中，第一井与第二井完全掺杂碳。
在一些实施例中，第一抗击穿层以外的第一井不完全掺杂碳。
在一些实施例中，第一抗击穿层与第二抗击穿层以外的第一井与第二井不完全掺杂碳。
在另一例中，半导体装置包括基板；第一井，位于完全掺杂n型掺质与碳的基板上，且第一井包括第一抗击穿层于第一井的上侧部分；以及第二井，位于完全掺杂p型掺质与碳的基板上，且第二井包括第二抗击穿层于第二井的上侧部分。半导体装置还包括第一源极结构与第一漏极结构，位于第一抗击穿层上并包含p型掺质；以及第二源极结构与第二漏极结构，位于第二抗击穿层上并包含n型掺质。半导体装置包括第一组多通道层，悬空于第一抗击穿层上并连接第一源极结构至第一漏极结构，其中第一组多通道层彼此垂直堆叠；以及第二组多通道层，悬空于第二抗击穿层上并连接第二源极结构至第二漏极结构，其中第二组多通道层彼此垂直堆叠。半导体装置还包括高介电常数的介电层与金属栅极，包覆第一组多通道层与第二组多通道层的每一者的三侧。半导体装置包括多个内侧介电间隔物，位于高介电常数的介电层与金属栅极以及第一源极结构、第二源极结构、第一漏极结构与第二漏极结构之间；以及顶部介电层，位于高介电常数的介电层与金属栅极的侧壁之上以及第一组多通道层的最顶层与第二组多通道层的最顶层之上。
在一些实施例中，半导体装置还包括：隔离结构，位于基板上以与第一井及第二井的上侧部分相邻并位于第一井及第二井的上侧部分之间，并与第一抗击穿层与第二抗击穿层相邻；其中第一井与第二井的部分位于隔离结构之下。
在一些实施例中，n型掺质为硼而p型掺质为磷。
在一些实施例中，第一井的硼与碳的掺质浓度为约1E16原子/cm3至1E19原子/cm3。
在一些实施例中，第一源极结构与第一漏极结构延伸至第一井中的量为第一量，第二源极结构与第二漏极结构延伸至第二井中的量为第二量，且第二量与第一量不同。
在另一例中，半导体装置包括基板；第一井，位于完全掺杂n型掺质的基板上，且第一井包括第一抗击穿层于掺杂碳的第一井的上侧部分，其中第一抗击穿层以外的第一井中实质上无碳；以及第二井，位于完全掺杂p型掺质的基板上，且第二井包括第二抗击穿层于掺杂碳的第二井的上侧部分，其中第二抗击穿层以外的第二井中实质上无碳。半导体装置还包括第一源极结构与第一漏极结构，位于第一抗击穿层上并包含p型掺质；以及第二源极结构与第二漏极结构，位于第二抗击穿层上并包含n型掺质。半导体装置包括第一组多通道层，悬空于第一抗击穿层上并连接第一源极结构至第一漏极结构，其中第一组多通道层彼此垂直堆叠；以及第二组多通道层，悬空于第二抗击穿层上并连接第二源极结构至第二漏极结构，其中第二组多通道层彼此垂直堆叠。半导体装置还包括高介电常数的介电层与金属栅极，包覆第一组多通道层与第二组多通道层的每一者的三侧。半导体装置亦包括多个内侧介电间隔物，位于高介电常数的介电层与金属栅极以及第一源极结构、第二源极结构、第一漏极结构与第二漏极结构之间；以及顶部介电层，位于高介电常数的介电层与金属栅极的侧壁之上以及第一组多通道层的最顶层与第二组多通道层的最顶层之上。
在一些实施例中，第一源极结构与第一漏极结构延伸至第一井的量为第一量；以及第二源极结构与第二漏极结构延伸至第二井的量为第二量，且第二量与第一量不同。
上述实施例的特征有利于本技术领域中技术人员理解本发明。本技术领域中技术人员应理解可采用本发明作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解，这些等效置换并未脱离本发明精神与范畴，并可在未脱离本发明的精神与范畴的前提下进行改变、替换或更动。

Claims (1)

1.一种半导体装置，包括：
一基板；
一第一井，位于该基板上，该第一井包括一第一导电型态的掺质；
一第一抗击穿层，位于该第一井的上侧部分，该第一抗击穿层包括该第一导电型态的掺质且还包括碳；
一源极结构与一漏极结构，与该第一抗击穿层相邻且为一第二导电型态，且该第二导电型态与该第一导电型态相反；
多个通道层，位于该第一抗击穿层上并连接该源极结构至该漏极结构，其中多个所述通道层彼此垂直堆叠；以及
一栅极，包覆每一所述通道层，其中该栅极的第一部分位于多个所述通道层的最底层以及该第一抗击穿层之间。
CN202110855772.3A 2020-11-13 2021-07-28 半导体装置 Pending CN114220811A (zh)

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