CN114184832B - Low-voltage detection circuit - Google Patents
Low-voltage detection circuit Download PDFInfo
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- CN114184832B CN114184832B CN202111480045.XA CN202111480045A CN114184832B CN 114184832 B CN114184832 B CN 114184832B CN 202111480045 A CN202111480045 A CN 202111480045A CN 114184832 B CN114184832 B CN 114184832B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The embodiment of the invention discloses a low-voltage detection circuit, which comprises a current source generating circuit, a reference voltage generating circuit and a comparator which are connected in sequence; the current source generating circuit is used for generating a reference current, the reference voltage generating circuit is used for generating a first comparison voltage VP and a second comparison voltage VN according to the reference current, and the comparator outputs a high-level signal when the first comparison voltage VP is greater than or equal to the second comparison voltage VN.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a low-voltage detection circuit.
Background
The low voltage detection circuit is mainly used for detecting the power supply voltage VDD, and when the detected power supply voltage VDD is lower than a threshold voltage (Vth) of a specific design, the low voltage detection circuit outputs a high level signal to reset or protect a subsequent system or device. Many application scenarios have high requirements on the threshold voltage (Vth) precision and power consumption of the circuit, and the existing low-voltage detection circuit generally generates a reference voltage from a band-gap reference source, and then compares the reference voltage with the resistor voltage division of the power supply voltage through a comparator, so as to detect the power supply voltage.
Disclosure of Invention
The embodiment of the invention provides a low-voltage detection circuit which is simple in structure and can realize low-power consumption detection.
In order to solve the above technical problems, in a first aspect, the present invention provides a low voltage detection circuit, which includes a current source generating circuit, a reference voltage generating circuit, and a comparator connected in sequence;
the current source generating circuit is used for generating reference current and comprises a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1, a second NMOS tube N2 and a first resistor R1; the grid electrode and the drain electrode of the first PMOS tube P1 are connected with the grid electrode of the second PMOS tube P2 and the drain electrode of the first NMOS tube N1, the source electrode of the first PMOS tube P1 and the source electrode of the second PMOS tube P2 are connected with a power supply voltage VDD, the drain electrode of the second PMOS tube P2 is connected with the grid electrode of the first NMOS tube N1 and the grid electrode and the drain electrode of the second NMOS tube N2, the source electrode of the first NMOS tube N1 is grounded through the first resistor R1, and the source electrode of the second NMOS tube N1 is grounded, wherein the number ratio of the first NMOS tube N1 to the second NMOS tube N2 is N, and N is an integer greater than or equal to 2;
the reference voltage generating circuit comprises a first branch and a second branch, wherein the first branch is connected with the grid electrode of the first PMOS tube P1 and the grid electrode of the second PMOS tube P2 and is used for generating a first comparison voltage VP, and the second branch is connected with the grid electrode of the first NMOS tube N1 and the grid electrode of the second NMOS tube N2 and is used for generating a second comparison voltage VN; the non-inverting input end of the comparator inputs the first comparison voltage VP, the inverting input end of the comparator inputs the second comparison voltage VN, and the output end of the comparator outputs a high-level signal when the first comparison voltage VP is greater than or equal to the second comparison voltage VN.
Further, the first branch circuit includes a third PMOS transistor P3 and a conducting element;
the grid electrode of the third PMOS tube P3 is connected with the grid electrode of the first PMOS tube P1 and the grid electrode of the second PMOS tube P2, the source electrode of the third PMOS tube P3 is connected with the power supply voltage VDD, the drain electrode of the third PMOS tube P3 is grounded through the conducting element, and the drain electrode of the third PMOS tube P3 is also connected with the non-inverting input end of the comparator.
Further, the conducting element is a diode, the anode of the diode is connected with the drain electrode of the third PMOS transistor P3, and the cathode of the diode is grounded.
Furthermore, the conducting element is a PNP bipolar transistor Q1, the base of the PNP bipolar transistor Q1 is grounded, the emitter is connected to the drain of the third PMOS transistor P3, and the collector is grounded.
Further, the second branch circuit comprises a second resistor R2 and a third NMOS tube N3;
one end of the second resistor R2 is connected with the power supply voltage VDD, the other end of the second resistor R2 is connected with the drain electrode of the third NMOS transistor N3 and the inverting input end of the comparator, the gate electrode of the third NMOS transistor N3 is connected with the gate electrode of the first NMOS transistor N1 and the gate electrode of the second NMOS transistor N2, and the source electrode of the third NMOS transistor N3 is grounded.
Further, the comparator includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7;
the source of the fourth PMOS transistor P4, the source of the fifth PMOS transistor P5, and the source of the sixth PMOS transistor P6 are all connected to the power supply voltage VDD, the gate and the drain of the fourth PMOS transistor P4 are connected to the gate of the fifth PMOS transistor P5 and the drain of the fourth NMOS transistor N4, the drain of the fifth PMOS transistor P5 is connected to the gate of the sixth PMOS transistor P6 and the drain of the fifth NMOS transistor N5, the drain of the sixth PMOS transistor P6 is the output terminal of the comparator and is connected to the drain of the seventh NMOS transistor N7, the gate of the fourth NMOS transistor N4 is the inverting input terminal of the comparator, the gate of the fifth NMOS transistor N5 is the non-inverting input terminal of the comparator, the source of the fourth NMOS transistor N4 is connected to the drain of the sixth NMOS transistor N6, the gate of the sixth NMOS transistor N6 and the gate of the seventh NMOS transistor N7 are both biased by the source of the seventh NMOS transistor N7 and the source of the seventh NMOS transistor N7.
Still further, a bias circuit for providing a first bias voltage NBIAS is included;
the bias circuit comprises a capacitor Cs, a seventh PMOS tube P7, an eighth NMOS tube N8 and a ninth NMOS tube N9;
one end of the capacitor Cs is connected to the power supply voltage VDD, the other end of the capacitor Cs is connected to the source of the seventh PMOS transistor P7, the gate of the seventh PMOS transistor P7 is input with an enable signal ENB, the drain of the seventh PMOS transistor P7 is connected to the drain of the eighth NMOS transistor N8 and the gate of the ninth NMOS transistor N9, the source of the eighth NMOS transistor N8 is grounded, the gate of the eighth NMOS transistor N8 is connected to the gate of the first NMOS transistor N1, the gate of the second NMOS transistor N2, the gate of the sixth NMOS transistor N6, and the gate of the seventh NMOS transistor N7, the drain of the ninth NMOS transistor N9 is connected to the gate of the first PMOS transistor P1 and the gate of the second PMOS transistor P2, and the source of the ninth NMOS transistor N9 is grounded.
In a second aspect, the present invention further provides an integrated circuit chip, including a low voltage detection circuit as described in any one of the above.
In a third aspect, the present invention further provides an electronic device, including the above-mentioned integrated circuit chip.
The beneficial effects are that: the low-voltage detection circuit comprises a current source generation circuit, a reference voltage generation circuit and a comparator which are connected in sequence; the current source generating circuit is used for generating reference current and comprises a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1, a second NMOS tube N2 and a first resistor R1; the grid electrode and the drain electrode of the first PMOS tube P1 are connected with the grid electrode of the second PMOS tube P2 and the drain electrode of the first NMOS tube N1, the source electrode of the first PMOS tube P1 and the source electrode of the second PMOS tube P2 are connected with a power supply voltage VDD, the drain electrode of the second PMOS tube P2 is connected with the grid electrode of the first NMOS tube N1 and the grid electrode and the drain electrode of the second NMOS tube N2, the source electrode of the first NMOS tube N1 is grounded through the first resistor R1, and the source electrode of the second NMOS tube N1 is grounded, wherein the number ratio of the first NMOS tube N1 to the second NMOS tube N2 is N, and N is an integer greater than or equal to 2; the reference voltage generating circuit is used for generating a first comparison voltage VP and a second comparison voltage VN according to the reference current, and the comparator outputs a high-level signal when the first comparison voltage VP is greater than or equal to the second comparison voltage VN.
Drawings
The technical solution of the present invention and its advantageous effects will be made apparent by the following detailed description of the specific embodiments of the present invention with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a low voltage detection circuit according to an embodiment of the present invention;
fig. 2 is another schematic diagram of a low voltage detection circuit according to an embodiment of the present invention.
Detailed Description
Referring to the drawings, wherein like reference numbers refer to like elements throughout, the principles of the present invention are illustrated in an appropriate computing environment. The following description is based on illustrative embodiments of the invention and should not be taken as limiting other embodiments of the invention not described in detail herein.
Referring to fig. 1, a low voltage detection circuit 100 according to an embodiment of the present invention includes a current source generating circuit 11, a reference voltage generating circuit 12, and a comparator 13 connected in sequence.
The current source generating circuit 11 is used for generating a reference current I PTAT The transistor comprises a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1, a second NMOS tube N2 and a first resistor R1. The grid electrode and the drain electrode of the first PMOS tube P1 are connected with the grid electrode of the second PMOS tube P2 and the drain electrode of the first NMOS tube N1, the source electrode of the first PMOS tube P1 and the source electrode of the second PMOS tube P2 are connected with the power supply voltage VDD, the drain electrode of the second PMOS tube P2 is connected with the grid electrode of the first NMOS tube N1 and the grid electrode and the drain electrode of the second NMOS tube N2, the source electrode of the first NMOS tube N1 is grounded through the first resistor R1, and the source electrode of the second NMOS tube N1 is grounded.
The number ratio of the first NMOS tubes N1 to the second NMOS tubes N2 is N, where N is an integer greater than or equal to 2, that is, the ratio of the number of the first NMOS tubes N1 to the number of the second NMOS tubes N2 is N, so in the embodiment of the present invention, there are a plurality of first NMOS tubes N1 and at least 1 second NMOS tube N2. The plurality of first NMOS transistors N1 are in a parallel relationship, that is, the drains of the plurality of first NMOS transistors N1 are connected in parallel, the gates of the plurality of first NMOS transistors N1 are connected in parallel, and the sources of the plurality of first NMOS transistors N1 are connected in parallel. When there are a plurality of second NMOS transistors N2, the plurality of second NMOS transistors N2 are also connected in parallel.
The reference voltage generating circuit 12 includes a first branch 121 and a second branch 122, where the first branch 121 is connected to the gate of the first PMOS transistor P1 and the gate of the second PMOS transistor P2, and is used to generate a first comparison voltage VP, and the second branch 122 is connected to the gate of the first NMOS transistor N1 and the gate of the second NMOS transistor N2, and is used to generate a second comparison voltage VN. The non-inverting input end of the comparator inputs the first comparison voltage VP, the inverting input end of the comparator inputs the second comparison voltage VN, and the output end of the comparator outputs a high-level signal when the first comparison voltage VP is greater than or equal to the second comparison voltage VN.
In the embodiment of the present invention, the reference current I is known from the circuit structure of the current source generating circuit 11 shown in FIG. 1 PTAT The calculation formula of (2) is as follows:
where n is a weak inversion factor, and n may take a value of 1.5.V (V) T Is a thermal voltage, and
wherein at a temperature of 300K, V T Approximately 26mV, wherein N is the ratio of the number of the first NMOS tube N1 to the number of the second NMOS tube N2, and R1 is the resistance value of the first resistor R1. Therefore, in the embodiment of the invention, by setting proper values of N and R1, a smaller reference current I can be obtained PTAT For example, the reference current I can be made PTAT The value of 10nA is that the current source generating circuit consumes smaller current by adjusting the values of N and R1, so as to realize the design requirement of ultra-low power consumption, and compared with the band gap reference source with complex structure, the current source generating circuit 11 of the embodiment of the invention has simple structure, and is beneficial to reducing the chip area.
Further, the first branch 121 includes a third PMOS transistor P3 and a conducting element.
The gate of the third PMOS transistor P3 is connected to the gate of the first PMOS transistor P1 and the gate of the second PMOS transistor P2, the source of the third PMOS transistor P3 is connected to the power voltage VDD, the drain of the third PMOS transistor P3 is grounded through the conductive element, and the drain of the third PMOS transistor P3 is further connected to the non-inverting input terminal of the comparator 13, so that the first comparison voltage VP is output from the drain of the third PMOS transistor P3 to the non-inverting input terminal of the comparator 13.
In some embodiments, the conducting element is a PNP bipolar transistor Q1, a base of the PNP bipolar transistor Q1 is grounded, an emitter of the PNP bipolar transistor Q1 is connected to a drain of the third PMOS transistor P3, and a collector of the PNP bipolar transistor Q is grounded.
In other embodiments, the conducting element may also be a diode, where an anode of the diode is connected to the drain of the third PMOS transistor P3, and a cathode of the diode is grounded.
With continued reference to fig. 1, the second branch 122 includes a second resistor R2 and a third NMOS transistor N3.
One end of the second resistor R2 is connected to the power supply voltage VDD, the other end of the second resistor R2 is connected to the drain of the third NMOS transistor N3 and the inverting input end of the comparator 13, the gate of the third NMOS transistor N3 is connected to the gate of the first NMOS transistor N1 and the gate of the second NMOS transistor N2, and the source of the third NMOS transistor N3 is grounded.
The low voltage detection circuit 100 according to the embodiment of the present invention can obtain the high-precision threshold voltage Vth that does not change with temperature, that is, the threshold voltage Vth of the low voltage detection circuit 100 can be made to not change with temperature by the current source generating circuit 11 and the reference voltage generating circuit 12 and the comparator 13 according to the present invention, so that the precision of the threshold voltage of the low voltage detection circuit 100 can be improved. The process of calculating the threshold voltage Vth of the low voltage detection circuit 100 is as follows:
as can be seen from the circuit shown in fig. 1, vp=v BE ；
VN＝VDD-I PTAT ·R2；
When VP is greater than or equal to VN, the comparator 13 outputs a high level signal, so that the power supply voltage VDD when vp=vn is the threshold voltage Vth of the low voltage detection circuit 100, i.e.
Wherein V is BE For conducting elements such as transistor Q1 or diode, the negative temperature coefficient is typically-2.0 to-2.2 mV/DEG C, R2 is the resistance of the second resistor R2Values. And thermal voltage V T Has a positive temperature coefficient: +0.087mV/. Degree.C, therefore, the temperature coefficient of the threshold voltage Vth can be zero by reasonably designing the sizes of the first resistor R1 and the second resistor R2, namely:
thus, a high-accuracy threshold voltage Vth that does not vary with temperature can be obtained. Wherein, the liquid crystal display device comprises a liquid crystal display device,
the result of deriving the threshold voltage Vth is the temperature coefficient of the threshold voltage Vth, V BE The value of (C) is-2.0 mV/DEG C.
Further, referring to fig. 2, in the embodiment of the present invention, the comparator 13 includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7.
The source of the fourth PMOS transistor P4, the source of the fifth PMOS transistor P5, and the source of the sixth PMOS transistor P6 are all connected to the power supply voltage VDD, the gate and the drain of the fourth PMOS transistor P4 are connected to the gate of the fifth PMOS transistor P5 and the drain of the fourth NMOS transistor N4, the drain of the fifth PMOS transistor P5 is connected to the gate of the sixth PMOS transistor P6 and the drain of the fifth NMOS transistor N5, the drain of the sixth PMOS transistor P6 is the output terminal of the comparator 13 and is connected to the drain of the seventh NMOS transistor N7, the gate of the fourth NMOS transistor N4 is the inverting input terminal of the comparator 13, the gate of the fifth NMOS transistor N5 is the non-inverting input terminal of the comparator 13, the source of the fourth NMOS transistor N4 is connected to the drain of the sixth NMOS transistor N6, the gate of the sixth NMOS transistor N6 and the drain of the seventh NMOS transistor N7 are both connected to the drain of the bias voltage of the seventh NMOS transistor N7.
The low voltage detection circuit 100 further includes a bias circuit 14 for providing a first bias voltage NBIAS. The bias circuit 14 may perform a start-up function for starting the current source generating circuit 11 and the comparator 13.
Specifically, the bias circuit 14 includes a capacitor Cs, a seventh PMOS transistor P7, an eighth NMOS transistor N8, and a ninth NMOS transistor N9; one end of the capacitor Cs is connected to the power supply voltage VDD, the other end of the capacitor Cs is connected to the source of the seventh PMOS transistor P7, the gate of the seventh PMOS transistor P7 is input with an enable signal ENB, the drain of the seventh PMOS transistor P7 is connected to the drain of the eighth NMOS transistor N8 and the gate of the ninth NMOS transistor N9, the source of the eighth NMOS transistor N8 is grounded, the gate of the eighth NMOS transistor N8 is connected to the gate of the first NMOS transistor N1, the gate of the second NMOS transistor N2, the gate of the sixth NMOS transistor N6, and the gate of the seventh NMOS transistor N7, the drain of the ninth NMOS transistor N9 is connected to the gate of the first PMOS transistor P1 and the gate of the second PMOS transistor P2, and the source of the ninth NMOS transistor N9 is grounded.
The low voltage detection circuit 100 of the present invention can realize that the current source generating circuit 11 only needs about 20nA of power consumption current and the reference voltage generating circuit 12 only needs about 20nA of power consumption current and the power consumption current of the comparator 13 is about 20nA by reasonably setting the sizes of the first resistor R1 and the second resistor R2, so that the total power consumption current of the low voltage detection circuit 100 is about 60nA, and the requirement of low power consumption can be satisfied.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present invention, the present description should not be construed as limiting the present invention.
Claims (9)
1. The low-voltage detection circuit is characterized by comprising a current source generation circuit, a reference voltage generation circuit and a comparator which are connected in sequence;
the current source generating circuit is used for generating reference current and comprises a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1, a second NMOS tube N2 and a first resistor R1; the grid electrode and the drain electrode of the first PMOS tube P1 are connected with the grid electrode of the second PMOS tube P2 and the drain electrode of the first NMOS tube N1, the source electrode of the first PMOS tube P1 and the source electrode of the second PMOS tube P2 are connected with a power supply voltage VDD, the drain electrode of the second PMOS tube P2 is connected with the grid electrode of the first NMOS tube N1 and the grid electrode and the drain electrode of the second NMOS tube N2, the source electrode of the first NMOS tube N1 is grounded through the first resistor R1, and the source electrode of the second NMOS tube N1 is grounded, wherein the number ratio of the first NMOS tube N1 to the second NMOS tube N2 is N, and N is an integer greater than or equal to 2;
the reference voltage generating circuit comprises a first branch and a second branch, wherein the first branch is connected with the grid electrode of the first PMOS tube P1 and the grid electrode of the second PMOS tube P2 and is used for generating a first comparison voltage VP, and the second branch is connected with the grid electrode of the first NMOS tube N1 and the grid electrode of the second NMOS tube N2 and is used for generating a second comparison voltage VN; the non-inverting input end of the comparator inputs the first comparison voltage VP, the inverting input end of the comparator inputs the second comparison voltage VN, and the output end of the comparator outputs a high-level signal when the first comparison voltage VP is greater than or equal to the second comparison voltage VN.
2. The low voltage detection circuit according to claim 1, wherein the first branch circuit includes a third PMOS transistor P3 and a pass device;
the grid electrode of the third PMOS tube P3 is connected with the grid electrode of the first PMOS tube P1 and the grid electrode of the second PMOS tube P2, the source electrode of the third PMOS tube P3 is connected with the power supply voltage VDD, the drain electrode of the third PMOS tube P3 is grounded through the conducting element, and the drain electrode of the third PMOS tube P3 is also connected with the non-inverting input end of the comparator.
3. The low voltage detection circuit according to claim 2, wherein the conducting element is a diode, an anode of the diode is connected to a drain of the third PMOS transistor P3, and a cathode of the diode is grounded.
4. The low voltage detection circuit according to claim 2, wherein the conducting element is a PNP bipolar transistor Q1, a base of the PNP bipolar transistor Q1 is grounded, an emitter of the PNP bipolar transistor Q1 is connected to a drain of the third PMOS transistor P3, and a collector of the PNP bipolar transistor Q is grounded.
5. The low voltage detection circuit of claim 1, wherein the second branch comprises a second resistor R2 and a third NMOS transistor N3;
one end of the second resistor R2 is connected with the power supply voltage VDD, the other end of the second resistor R2 is connected with the drain electrode of the third NMOS transistor N3 and the inverting input end of the comparator, the gate electrode of the third NMOS transistor N3 is connected with the gate electrode of the first NMOS transistor N1 and the gate electrode of the second NMOS transistor N2, and the source electrode of the third NMOS transistor N3 is grounded.
6. The low voltage detection circuit according to claim 1, wherein the comparator comprises a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7;
the source of the fourth PMOS transistor P4, the source of the fifth PMOS transistor P5, and the source of the sixth PMOS transistor P6 are all connected to the power supply voltage VDD, the gate and the drain of the fourth PMOS transistor P4 are connected to the gate of the fifth PMOS transistor P5 and the drain of the fourth NMOS transistor N4, the drain of the fifth PMOS transistor P5 is connected to the gate of the sixth PMOS transistor P6 and the drain of the fifth NMOS transistor N5, the drain of the sixth PMOS transistor P6 is the output terminal of the comparator and is connected to the drain of the seventh NMOS transistor N7, the gate of the fourth NMOS transistor N4 is the inverting input terminal of the comparator, the gate of the fifth NMOS transistor N5 is the non-inverting input terminal of the comparator, the source of the fourth NMOS transistor N4 is connected to the drain of the sixth NMOS transistor N6, the gate of the sixth NMOS transistor N6 and the gate of the seventh NMOS transistor N7 are both biased by the source of the seventh NMOS transistor N7 and the source of the seventh NMOS transistor N7.
7. The low voltage detection circuit of claim 6, further comprising a bias circuit for providing a first bias voltage NBIAS;
the bias circuit comprises a capacitor Cs, a seventh PMOS tube P7, an eighth NMOS tube N8 and a ninth NMOS tube N9;
one end of the capacitor Cs is connected to the power supply voltage VDD, the other end of the capacitor Cs is connected to the source of the seventh PMOS transistor P7, the gate of the seventh PMOS transistor P7 is input with an enable signal ENB, the drain of the seventh PMOS transistor P7 is connected to the drain of the eighth NMOS transistor N8 and the gate of the ninth NMOS transistor N9, the source of the eighth NMOS transistor N8 is grounded, the gate of the eighth NMOS transistor N8 is connected to the gate of the first NMOS transistor N1, the gate of the second NMOS transistor N2, the gate of the sixth NMOS transistor N6, and the gate of the seventh NMOS transistor N7, the drain of the ninth NMOS transistor N9 is connected to the gate of the first PMOS transistor P1 and the gate of the second PMOS transistor P2, and the source of the ninth NMOS transistor N9 is grounded.
8. An integrated circuit chip comprising the low voltage detection circuit of any one of claims 1-7.
9. An electronic device comprising the integrated circuit chip of claim 8.
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| CN202111480045.XA CN114184832B (en) | 2021-12-06 | 2021-12-06 | Low-voltage detection circuit |
| PCT/CN2022/132872 WO2023103748A1 (en) | 2021-12-06 | 2022-11-18 | Low-voltage detection circuit |
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| CN202111480045.XA CN114184832B (en) | 2021-12-06 | 2021-12-06 | Low-voltage detection circuit |
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| CN114184832B true CN114184832B (en) | 2023-05-23 |
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| CN117471152B (en) * | 2023-12-27 | 2024-03-08 | 苏州贝克微电子股份有限公司 | Low-power-consumption voltage detection circuit |
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| CN111158422A (en) * | 2020-01-15 | 2020-05-15 | 西安电子科技大学 | Reference voltage source with zero temperature coefficient bias point |
| CN114184832B (en) * | 2021-12-06 | 2023-05-23 | 深圳飞骧科技股份有限公司 | Low-voltage detection circuit |
-
2021
- 2021-12-06 CN CN202111480045.XA patent/CN114184832B/en active Active
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2022
- 2022-11-18 WO PCT/CN2022/132872 patent/WO2023103748A1/en unknown
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101196540A (en) * | 2006-12-07 | 2008-06-11 | 三洋电机株式会社 | Voltage detecting circuit |
| CN206223841U (en) * | 2016-08-16 | 2017-06-06 | 大唐恩智浦半导体有限公司 | A kind of low-voltage testing circuit and half-bridge driven chip |
| CN110806777A (en) * | 2019-12-02 | 2020-02-18 | 湖南品腾电子科技有限公司 | Low-power consumption small-area temperature compensation low-voltage detection circuit |
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| WO2023103748A1 (en) | 2023-06-15 |
| CN114184832A (en) | 2022-03-15 |
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