CN114156379B - Manufacturing method of light-emitting chip - Google Patents
Manufacturing method of light-emitting chip Download PDFInfo
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- CN114156379B CN114156379B CN202111469259.7A CN202111469259A CN114156379B CN 114156379 B CN114156379 B CN 114156379B CN 202111469259 A CN202111469259 A CN 202111469259A CN 114156379 B CN114156379 B CN 114156379B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 67
- 239000002184 metal Substances 0.000 claims abstract description 67
- 238000000034 method Methods 0.000 claims abstract description 63
- 238000012546 transfer Methods 0.000 claims abstract description 54
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 230000008569 process Effects 0.000 claims abstract description 29
- 239000010410 layer Substances 0.000 claims description 433
- 239000000758 substrate Substances 0.000 claims description 83
- 239000002346 layers by function Substances 0.000 claims description 39
- 230000007480 spreading Effects 0.000 claims description 27
- 238000003892 spreading Methods 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 16
- 230000007704 transition Effects 0.000 claims description 10
- 230000007797 corrosion Effects 0.000 claims description 8
- 238000005260 corrosion Methods 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 2
- 238000000605 extraction Methods 0.000 abstract description 11
- 238000005516 engineering process Methods 0.000 abstract description 7
- 238000002310 reflectometry Methods 0.000 abstract description 6
- 238000001259 photo etching Methods 0.000 abstract description 4
- 238000007788 roughening Methods 0.000 description 17
- 239000000243 solution Substances 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 7
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 230000002441 reversible effect Effects 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052594 sapphire Inorganic materials 0.000 description 5
- 239000010980 sapphire Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 235000011114 ammonium hydroxide Nutrition 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 230000031700 light absorption Effects 0.000 description 4
- 239000011259 mixed solution Substances 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000005286 illumination Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- JGJLWPGRMCADHB-UHFFFAOYSA-N hypobromite Inorganic materials Br[O-] JGJLWPGRMCADHB-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000000750 progressive effect Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000007771 core particle Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000005431 greenhouse gas Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 229910002059 quaternary alloy Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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Abstract
The application discloses a manufacturing method of a light-emitting chip, which adopts a secondary transfer technology, can realize light emission of a P surface and improves the extraction efficiency of light; meanwhile, a dielectric layer is added between the first ohmic contact layer and the metal mirror layer, and dielectric holes with specific sizes and quantity are manufactured on the dielectric layer by using a photoetching process, so that the first ohmic contact layer and the metal mirror layer in the dielectric holes form ohmic contact, voltage stability can be ensured, a chip process window is increased, and the semiconductor, the dielectric layer and the metal mirror layer form an omnibearing reflecting mirror structure, so that reflectivity can be greatly improved.
Description
Technical Field
The present invention relates to the field of semiconductor chip technology, and in particular, to a method for manufacturing a light emitting chip.
Background
The LED is used as a new illumination light source in the 21 st century, the power consumption of the semiconductor lamp is only 1/10 of that of a common incandescent lamp under the same brightness, and the service life of the semiconductor lamp can be prolonged by 100 times. The LED device is a cold light source, has high light efficiency, low working voltage, small power consumption and small volume, can be packaged in a plane, is easy to develop a light and thin product, has firm structure and long service life, does not contain harmful substances such as mercury, lead and the like, does not pollute infrared and ultraviolet, and can not pollute the outside in production and use. Therefore, the semiconductor lamp has the characteristics of energy saving, environmental protection, long service life and the like, and is a trend to replace the traditional incandescent lamp and fluorescent lamp like a transistor replaces an electron tube. LEDs have great potential as new illumination sources to replace conventional illumination sources, both from the point of view of saving electrical energy, reducing greenhouse gas emissions, and from the point of view of reducing environmental pollution.
With the rapid development of AlGaInP (AlGaInP) quaternary materials, the AlGaInP quaternary materials can be used for manufacturing high-power high-brightness red light and yellow light LEDs. Although red LEDs manufactured from AlGaInP-based materials have been commercially produced, LEDs using quaternary alloy materials as the multi-quantum well active region have extremely high internal quantum efficiency. However, the external quantum efficiency of the conventional AlGaInP-LED is extremely low due to limitations of the material itself and the substrate. The AlGaInP material system has large refractive index, so that the light-emitting angle is small, and most of light is totally reflected; and the GaAs substrate is a light absorption material, so that the light quantity of the active layer radiated towards the substrate is absorbed by the GaAs substrate in a large quantity, and the light emitting efficiency is poor.
Disclosure of Invention
In view of this, the present application provides a method for manufacturing a light emitting chip, which adopts a secondary transfer technology, and can realize light extraction from the P-surface and improve the light extraction efficiency.
In order to achieve the above object, the present invention provides the following technical solutions:
a method of fabricating a light emitting chip, the method comprising the steps of:
s1, providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface which are opposite;
s2, arranging a first functional layer on the first surface, wherein the first functional layer is respectively a buffer layer, a corrosion cut-off layer, a first ohmic contact layer, a first current expansion layer and a first limiting layer from bottom to top;
s3, an active layer is arranged on the surface, deviating from the first current expansion layer, of the first limiting layer;
s4, a second functional layer is arranged on the surface, deviating from the first limiting layer, of the active layer, wherein the second functional layer is a second limiting layer, a transition layer, a window layer, a second current expansion layer, a coarsening layer and a second ohmic contact layer respectively from bottom to top;
s5, a primary transfer structure is arranged on the surface, away from the roughened layer, of the second ohmic contact layer, wherein the primary transfer structure comprises a primary transfer substrate and a consumption layer, and the consumption layer is positioned between the primary transfer substrate and the second ohmic contact layer;
s6, dissolving the semiconductor substrate, the buffer layer and the corrosion-stopping layer by using a solution;
s7, arranging an omnibearing reflecting mirror structure on the surface of one side, away from the first current expansion layer, of the first ohmic contact layer, wherein the reflecting mirror structure comprises a semiconductor, a dielectric layer and a metal mirror layer, and the dielectric layer is positioned between the metal mirror layer and the first ohmic contact layer; the dielectric layer is provided with dielectric holes with preset quantity and size, and the metal mirror layer fills the dielectric holes, so that the first ohmic contact layer and the metal mirror layer in the dielectric holes form ohmic contact;
s8, providing a secondary transfer substrate, wherein the secondary transfer substrate is provided with a third surface and a fourth surface which are opposite;
s9, arranging a bonding metal layer on the third surface;
s10, bonding the bonding metal layer with the metal mirror layer on the surface of one side, facing away from the secondary transfer substrate;
s11, removing the primary transfer substrate and the consumption layer by using a solution dissolving or exposing method;
s12, coarsening the coarsening layer by utilizing coarsening liquid or a dry etching process;
s13, setting a third current expansion layer on the roughened surface of the roughened layer;
s14, a first electrode layer is arranged on the surface of one side, away from the roughened layer, of the second ohmic contact layer;
and S15, grinding and thinning the fourth surface, and forming a second electrode layer on the thinned fourth surface.
Preferably, in the above manufacturing method, the first functional layer is an N-type functional layer, and the second functional layer is a P-type functional layer.
Preferably, in the above manufacturing method, the sacrificial layer is a colloid material or a photosensitive material.
Preferably, in the above manufacturing method, the dielectric layer is SiO 2 Layers or MgF 2 A layer; the thickness of the dielectric layer is
Preferably, in the above manufacturing method, the metal mirror layer is an Au layer or an Ag layer.
Preferably, in the above-mentioned production method, the bonding metal layer is an Au layer or an Ag layer or an In layer.
Preferably, in the above manufacturing method, the roughened layer is a GaP layer.
Preferably, in the above manufacturing method, in step S10, the bonding pressure at the time of bonding is 8000-15000Kg, and the bonding temperature is 250-400 ℃.
Preferably, in the above manufacturing method, in step S13, the third current spreading layer is an ITO layer, an IZO layer, an AZO layer, or an IGZO layer;
the thickness of the third current expansion layer is 0.1-0.5um.
Preferably, in the above manufacturing method, in step S15, the thickness of the polished and thinned secondary transfer substrate is 100-250um.
As can be seen from the above description, in the method for manufacturing a light emitting chip provided by the technical scheme of the present invention, the secondary transfer technology is adopted, so that the light emitting of the P-surface can be realized, and the extraction efficiency of the light can be improved; meanwhile, a dielectric layer is added between the first ohmic contact layer and the metal mirror layer, and dielectric holes with specific sizes and quantity are manufactured on the dielectric layer by using a photoetching process, so that the first ohmic contact layer and the metal mirror layer in the dielectric holes form ohmic contact, voltage stability is ensured, a chip process window is increased, and the semiconductor, the dielectric layer and the metal mirror layer form an omnibearing reflecting mirror structure (ODR), so that the reflectivity is greatly improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.
The structures, proportions, sizes, etc. shown in the drawings are shown only in connection with the present disclosure, and should not be construed as limiting the scope of the invention, since any modification, variation in proportions, or adjustment of the size, which would otherwise be used by those skilled in the art, would not have the essential significance of the present disclosure, would not affect the efficacy or otherwise be achieved, and would still fall within the scope of the present disclosure.
Fig. 1 is a schematic structural diagram of a conventional reverse polarity chip.
Fig. 2-20 are process flow diagrams of a manufacturing method of a light emitting chip according to an embodiment of the present invention;
fig. 21-33 are process flow diagrams of another method for manufacturing a light emitting chip according to an embodiment of the present invention.
Detailed Description
Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which it is shown, and in which it is evident that the embodiments described are exemplary only some, and not all embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The reverse polarity AlGaInP quaternary LED chip is widely applied to the field of high-power red LED display screens, the reverse polarity is that the substrate is replaced, the GaAs substrate with larger light absorption is replaced by a monocrystalline conductive silicon substrate or a sapphire substrate, and the like, so that the light efficiency can be improved by more than 20%, but the N pole (light emitting surface) of the chip finished by the process is arranged on the upper surface, the P electrode is arranged below, and the chip is quite different from the traditional red chip, and when the red chip and the blue-green chip are used together, the phenomenon of increased difficulty in circuit management can occur.
AlGaInP quaternary materials are used for growing high-brightness red-yellow LEDs, and the internal quantum efficiency is high, but two key problems exist to limit the light extraction efficiency: 1. the refractive index of the material system is large (> 3.2), so that the light-emitting angle is small, and most of light is totally reflected; 2. the GaAs substrate absorbs red Huang Boduan light. To solve these two problems, the conventional approach is to use a technique of top surface roughening and an omni-directional mirror instead of the GaAs substrate.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a conventional reverse polarity chip, in which the structure of the reverse polarity chip is as follows: a P electrode 9, a transfer substrate 1, a metal bonding layer 2, a metal mirror layer 3, a dielectric layer 4, a P-type layer 5, an active layer 6, an N-type layer 7 and an N electrode 8.
In the traditional reverse polarity chip structure, the N-face emits light, and the P-face reflecting mirror adopts a surface roughening and P-face omnibearing reflecting mirror mode. Because the N surface needs to be roughened or a current expansion layer, the thickness of the N layer is thick, the growth time is long, the probability of epitaxial defect caused by falling of top cover impurities at the stage is increased, the number of failed core particles is increased by growing an active 6 layer and a P-type layer 5 on the basis, and the chip failure phenomenon caused by the problem is more remarkable along with the reduction of the chip size; meanwhile, the N-type layer 7 is doped with Si, the forbidden bandwidth of Si is only 1.12eV, the light absorption is easy, and the degree of Si light absorption is increased due to the thicker N layer.
In view of this, the invention provides a method for manufacturing a light emitting chip, which adopts a secondary transfer technology, can realize light emitting of the P surface and improves the extraction efficiency of light; meanwhile, a dielectric layer is added between the first ohmic contact layer and the metal mirror layer, and dielectric holes with specific sizes and quantity are manufactured on the dielectric by using a photoetching process, so that the first ohmic contact layer and the metal mirror layer in the dielectric holes form ohmic contact, voltage stability is ensured, a chip process window is increased, and the semiconductor, the dielectric layer and the metal mirror layer form an omnibearing reflecting mirror structure, so that the reflectivity is greatly improved.
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.
Referring to fig. 2 to 20, fig. 2 to 20 are process flow diagrams of a manufacturing method of a light emitting chip according to an embodiment of the present invention, where the manufacturing method includes:
step S1: as shown in fig. 2, a semiconductor substrate 11 is provided, the semiconductor substrate 11 having opposite first and second surfaces;
the semiconductor substrate 11 may be an N-type GaAs substrate having a <100> orientation biased toward <111> a by 2 degrees to 15 degrees.
Step S2: as shown in fig. 3, a first functional layer 12 is disposed on the first surface, where the first functional layer 12 may be an N-type functional layer, and the first functional layer 12 includes, from bottom to top, a buffer layer 121, a corrosion-stopping layer 122, a first ohmic contact layer 123, a first current expansion layer 124, and a first limiting layer 125, respectively;
the method for forming the first functional layer 12 includes: growing a buffer layer 121 on a first surface of the semiconductor substrate 11; growing a corrosion cut-off layer 122 on a surface of the buffer layer 121 on a side facing away from the semiconductor substrate 11; growing a first ohmic contact layer 123 on a surface of the corrosion cut-off layer 122 on a side facing away from the buffer layer 121; growing a first current spreading layer 124 on a surface of the first ohmic contact layer 123 facing away from the corrosion cut-off layer 122; a first confinement layer 125 is grown on a surface of the first current spreading layer 124 facing away from the first ohmic contact layer 123.
Step S3: as shown in fig. 4, an active layer 13 is disposed on a surface of the first confinement layer 125 facing away from the first current spreading layer 124; the active layer 13 may be a superlattice active layer, which may be grown using a low-temperature MQW process;
step S4: as shown in fig. 5, a second functional layer 14 is disposed on a surface of the active layer 13 facing away from the first limiting layer 125, where the second functional layer 14 may be a P-type functional layer, and the second functional layer 14 includes, from bottom to top, a second limiting layer 141, a transition layer 142, a window layer 143, a second current spreading layer 144, a roughening layer 145, and a second ohmic contact layer 146;
the method for forming the second functional layer 14 includes: growing a second confinement layer 141 on a surface of the active layer 13 facing away from the first confinement layer 125; growing a transition layer 142 on a surface of a side of the second confinement layer 141 facing away from the active layer 13; growing a window layer 143 on a surface of the transition layer 142 facing away from the second confinement layer 141; growing a second current spreading layer 144 on a surface of the window layer 143, which is away from the transition layer 142; a roughened layer 145 is grown on the surface of one side of the second current expansion layer 144 facing away from the window layer 143; and a second ohmic contact layer 146 is grown on the surface of the roughened layer 145 on the side facing away from the second current spreading layer 144.
The second current spreading layer 144 and the roughened layer 145 may be Mg-doped GaP layers, and the second ohmic contact layer 146 may be Mg-or C-doped GaP layers grown at low temperature.
Step S5: as shown in fig. 6, a primary transfer structure 15 is disposed on a surface of the second ohmic contact layer 146 facing away from the roughened layer 145, where the primary transfer structure 15 includes a primary transfer substrate 152 and a sacrificial layer 151, and the sacrificial layer 151 is located between the primary transfer substrate 152 and the second ohmic contact layer 146;
wherein, the primary transfer substrate 152 may be a metal substrate, or a sapphire substrate, or a quartz substrate, or a silicon substrate; the sacrificial layer 151 may be a colloidal material or a photosensitive material that is easily dissolved in a specific solution or denatured upon exposure to light.
Step S6: as shown in fig. 7, the semiconductor substrate 11, the buffer layer 121, and the corrosion-cut layer 122 are dissolved with a solution;
wherein, the solution can be a mixed solution of ammonia water, hydrogen peroxide and water, and the ammonia water: hydrogen peroxide: the volume ratio of water may be 1:2:6.
Step S7: as shown in fig. 8, an omnidirectional reflector structure 16 is disposed on a surface of the first ohmic contact layer 123 facing away from the first current spreading layer 124, the reflector structure 16 includes a semiconductor and dielectric layer 162 and a metal mirror layer 161, and the dielectric layer 162 is located between the metal mirror layer 161 and the first ohmic contact layer 123; the dielectric layer 162 has a preset number and size of dielectric holes 163 therein, and the metal mirror layer 161 fills the dielectric holes 163, so that the first ohmic contact layer 123 forms ohmic contact with the metal mirror layer 161 in the dielectric holes 163;
wherein the dielectric layer 162 may be SiO 2 Layers or MgF 2 Transparent film with low refractive index such as layerThe method comprises the steps of carrying out a first treatment on the surface of the The dielectric layer 162 may have a thickness of
For example, it can be +.>
The metal mirror layer 161 may be an Au layer or an Ag layer.
In the embodiment of the present invention, the dielectric layer 162 with a specific thickness may be first evaporated, then the dielectric holes 163 with a specific number and size may be fabricated on the dielectric layer 162 by using a photolithography burying process, and then the metal mirror layer 161 may be evaporated. And ensures that the thickness of the metal mirror layer 161 is greater than the thickness of the dielectric layer 162 and fills the dielectric hole 163. The number and size of the dielectric holes 163 may be set based on the requirement.
Step S8: as shown in fig. 9, a secondary transfer substrate 21 is provided, the secondary transfer substrate 21 having opposite third and fourth surfaces;
the secondary transfer substrate 21 may be a silicon substrate or a sapphire substrate, and the thickness of the secondary transfer substrate 21 may be 150-350um, for example, 280um.
Step S9: as shown in fig. 10, a bonding metal layer 22 is provided on the third surface; the bonding metal layer may be an Au layer or an Ag layer or an In layer.
Step S10: as shown in fig. 11, a side surface of the bonding metal layer 22 facing away from the secondary transfer substrate 21 is bonded to the metal mirror layer 161;
specifically, the bonding metal layer 22 may be bonded to the metal mirror layer 161 using a bonding machine, and the bonding pressure may be 8000-15000Kg and the bonding temperature may be 250-400 ℃.
Step S11: as shown in fig. 12, the primary transfer substrate 152 and the sacrificial layer 151 are removed using a solution dissolving or exposing method;
specifically, the primary transfer substrate 152 may be dissolved by using a mixed solution of ammonia, hydrogen peroxide and water to remove the primary transfer substrate 152, and then the sacrificial layer 151 is denatured by an exposure method to be separated from GaP.
Step S12: as shown in fig. 13-16, roughening the roughened layer 145 by using a roughening solution or a dry etching process;
in the embodiment of the present invention, the method for roughening the roughened layer 145 includes:
first, as shown in fig. 13, a photoresist layer 17 is grown on the surface of the second ohmic contact layer 146 facing away from the roughened layer 145;
then, as shown in fig. 14, the photoresist layer 17 is subjected to photolithography development to form a patterned photoresist layer 17, and a portion of the second ohmic contact layer 146 is exposed;
then, as shown in fig. 15, based on the patterned photoresist layer 17, etching the second ohmic contact layer 146 to expose a portion of the surface of the roughened layer 145, i.e., a roughened region;
then, as shown in fig. 16, the roughened region is roughened with a roughening liquid;
finally, as shown in fig. 17, the remaining photoresist layer 17 is removed.
In order to obtain the roughened morphology with optimal light extraction efficiency, a roughening solution with specific components is selected, and the roughening time and temperature are controlled to obtain the optimal roughened morphology. The roughening liquid can be mixed liquid of phosphoric acid, acetic acid and bromine water.
Step S13: as shown in fig. 18, a third current spreading layer 18 is provided on the roughened surface of the roughened layer 145;
wherein, the third current spreading layer 18 may be an ITO layer or an IZO layer or an AZO layer or an IGZO layer; the thickness of the third current spreading layer 18 may be 0.1-0.5um, such as 0.3um.
Step S14: as shown in fig. 19, a first electrode layer 19 is disposed on a surface of the second ohmic contact layer 146 facing away from the roughened layer 145;
the first electrode layer 19 may be a P-surface electrode, and the electrode material may be Au, pt, zn, or Ti.
Step S15: as shown in fig. 20, the fourth surface of the secondary transfer substrate 21 is polished and thinned, and a second electrode layer 23 is formed on the thinned fourth surface. The second electrode layer 23 may be an N-sided electrode, the electrode material may be Au, pt or AuGe, and the thickness may be 2-6um.
Specifically, the fourth surface may be ground and thinned by using a grinder, and the thickness of the thinned secondary transfer substrate 21 may be 100-250um, for example, 200um.
Based on the above embodiments, the present invention further provides another method for manufacturing a light emitting chip, as shown in fig. 2 to 7, fig. 9 to 10, and fig. 21 to 33 are process flow diagrams of another method for manufacturing a light emitting chip according to the embodiment of the present invention, where the manufacturing method includes:
step S21: as shown in fig. 2, a semiconductor substrate 11 is provided, the semiconductor substrate 11 having opposite first and second surfaces;
the semiconductor substrate 11 may be an N-type GaAs substrate having a <100> orientation biased toward <111> a by 2 degrees to 15 degrees.
Step S22: as shown in fig. 3, a first functional layer 12 is disposed on the first surface, where the first functional layer 12 may be an N-type functional layer, and the first functional layer 12 includes, from bottom to top, a buffer layer 121, a corrosion-stopping layer 122, a first ohmic contact layer 123, a first current expansion layer 124, and a first limiting layer 125, respectively;
the method for forming the first functional layer 12 includes: growing a buffer layer 121 on a first surface of the semiconductor substrate 11; growing a corrosion cut-off layer 122 on a surface of the buffer layer 121 on a side facing away from the semiconductor substrate 11; growing a first ohmic contact layer 123 on a surface of the corrosion cut-off layer 122 on a side facing away from the buffer layer 121; growing a first current spreading layer 124 on a surface of the first ohmic contact layer 123 facing away from the corrosion cut-off layer 122; a first confinement layer 125 is grown on a surface of the first current spreading layer 124 facing away from the first ohmic contact layer 123.
Step S23: as shown in fig. 4, an active layer 13 is disposed on a surface of the first confinement layer 125 facing away from the first current spreading layer 124; the active layer 13 may be a superlattice active layer, which may be grown using a low-temperature MQW process;
step S24: as shown in fig. 5, a second functional layer 14 is disposed on a surface of the active layer 13 facing away from the first limiting layer 125, where the second functional layer 14 may be a P-type functional layer, and the second functional layer 14 includes, from bottom to top, a second limiting layer 141, a transition layer 142, a window layer 143, a second current spreading layer 144, a roughening layer 145, and a second ohmic contact layer 146;
the method for forming the second functional layer 14 includes: growing a second confinement layer 141 on a surface of the active layer 13 facing away from the first confinement layer 125; growing a transition layer 142 on a surface of a side of the second confinement layer 141 facing away from the active layer 13; growing a window layer 143 on a surface of the transition layer 142 facing away from the second confinement layer 141; growing a second current spreading layer 144 on a surface of the window layer 143, which is away from the transition layer 142; a roughened layer 145 is grown on the surface of one side of the second current expansion layer 144 facing away from the window layer 143; and a second ohmic contact layer 146 is grown on the surface of the roughened layer 145 on the side facing away from the second current spreading layer 144.
The second current spreading layer 144 and the roughened layer 145 may be Mg-doped GaP layers, and the second ohmic contact layer 146 may be Mg-or C-doped GaP layers grown at low temperature.
Step S25: as shown in fig. 6, a primary transfer structure 15 is disposed on a surface of the second ohmic contact layer 146 facing away from the roughened layer 145, where the primary transfer structure 15 includes a primary transfer substrate 152 and a sacrificial layer 151, and the sacrificial layer 151 is located between the primary transfer substrate 152 and the second ohmic contact layer 146;
wherein, the primary transfer substrate 152 may be a metal substrate, or a sapphire substrate, or a quartz substrate, or a silicon substrate; the sacrificial layer 151 may be a colloidal material or a photosensitive material that is easily dissolved in a specific solution or denatured upon exposure to light.
Step S26: as shown in fig. 7, the semiconductor substrate 11, the buffer layer 121, and the corrosion-cut layer 122 are dissolved with a solution;
wherein, the solution can be a mixed solution of ammonia water, hydrogen peroxide and water, and the ammonia water: hydrogen peroxide: the volume ratio of water may be 1:2:6.
Step S27: as shown in fig. 21, the first ohmic contact layer 123 is etched by using a photolithography process, so that a portion of the surface of the first current spreading layer 124 is exposed, and the first ohmic contact layer 123 at the position of the post-pre-made dielectric hole 163 is maintained;
the purpose is that: the first ohmic contact layer 123 is used for forming ohmic contact with the metal mirror layer 161 later, for the ODR reflectivity, as the doping concentration of the ohmic contact layer is high, part of doping elements can diffuse into the dielectric layer 162 in the alloying process, so that the smoothness of the metal mirror layer 161 is reduced, the light-emitting efficiency is affected, so that the first ohmic contact layer 123 at the position of the dielectric hole 163 is reserved, the first ohmic contact layers 123 at other positions are removed, the ohmic contact between the subsequent metal mirror layer 161 and the first ohmic contact layer 123 is not affected, and the reflection efficiency of the ODR can be improved.
In this embodiment of the present invention, a photoresist layer may be formed on a surface of the first ohmic contact layer 123 opposite to the first current spreading layer 124, then the photoresist layer is etched by using a photolithography process to form a patterned photoresist layer, and then the first ohmic contact layer 123 is etched based on the patterned photoresist layer, so as to preserve the first ohmic contact layer 123 at the position of the later pre-made dielectric hole 163.
Step S28: as shown in fig. 22, a dielectric layer 162 is formed on the exposed surface of the first current spreading layer 124 and the surface of the first ohmic contact layer 123, the dielectric layer 162 has a preset number and size of dielectric holes 163, and the positions of the dielectric holes 163 are opposite to the positions where the first ohmic contact layer 123 is reserved in step S27; wherein, the thickness of the dielectric layer 162 is greater than the thickness of the first ohmic contact layer 123;
step S29: as shown in fig. 23, a metal mirror layer 161 is formed on a surface of the dielectric layer 162 on a side facing away from the first current spreading layer 124; wherein, the thickness of the metal mirror layer 161 is greater than the thickness of the dielectric layer 162, and the dielectric hole 163 is filled up, so that the first ohmic contact layer 123 forms ohmic contact with the metal mirror layer 161 in the dielectric hole 163;
the semiconductor and dielectric layer 162 and the metal mirror layer 161 form the omnidirectional reflector structure 16, so that the reflection efficiency of the ODR can be improved.
In the embodiment of the present invention, the dielectric layer 162 with a specific thickness may be first evaporated, then the dielectric layer 162 is further processed with a photolithography burying process to form the dielectric holes 163 with a specific number and size, the positions of the dielectric holes 163 are opposite to the positions of the first ohmic contact layer 123 reserved in step S27, and then the metal mirror layer 161 is evaporated. And the thickness of the metal mirror layer 161 is ensured to be greater than that of the dielectric layer 162, and the dielectric hole 163 is filled so that the metal mirror layer 161 and the first ohmic contact layer 123 form ohmic contact through annealing later.
Step S30: as shown in fig. 9, a secondary transfer substrate 21 is provided, the secondary transfer substrate 21 having opposite third and fourth surfaces;
the secondary transfer substrate 21 may be a silicon substrate or a sapphire substrate, and the thickness of the secondary transfer substrate 21 may be 150-350um, for example, 280um.
Step S31: as shown in fig. 10, a bonding metal layer 22 is provided on the third surface; the bonding metal layer may be an Au layer or an Ag layer or an In layer.
Step S32: as shown in fig. 24, a side surface of the bonding metal layer 22 facing away from the secondary transfer substrate 21 is bonded to the metal mirror layer 161;
specifically, the bonding metal layer 22 may be bonded to the metal mirror layer 161 using a bonding machine, and the bonding pressure may be 8000-15000Kg and the bonding temperature may be 250-400 ℃.
Step S33: as shown in fig. 25, the primary transfer substrate 152 and the sacrificial layer 151 are removed using a solution dissolving or exposing method;
specifically, the primary transfer substrate 152 may be dissolved by using a mixed solution of ammonia, hydrogen peroxide and water to remove the primary transfer substrate 152, and then the sacrificial layer 151 is denatured by an exposure method to be separated from GaP.
Step S34: as shown in fig. 26-30, the roughened layer 145 is roughened by using a roughening solution or a dry etching process;
in the embodiment of the present invention, the method for roughening the roughened layer 145 includes: first, as shown in fig. 26, a photoresist layer 17 is grown on the surface of the second ohmic contact layer 146 facing away from the roughened layer 145; then, as shown in fig. 27, the photoresist layer 17 is subjected to photolithography development to form a patterned photoresist layer 17, and a portion of the second ohmic contact layer 146 is exposed; then, as shown in fig. 28, based on the patterned photoresist layer 17, the second ohmic contact layer 146 is etched to expose a portion of the surface of the roughened layer 145, i.e., a roughened region; then, as shown in fig. 29, the roughened region is roughened with a roughening liquid; finally, as shown in fig. 30, the remaining photoresist layer 17 is removed.
In order to obtain the roughened morphology with optimal light extraction efficiency, a roughening solution with specific components is selected, and the roughening time and temperature are controlled to obtain the optimal roughened morphology. The roughening liquid can be mixed liquid of phosphoric acid, acetic acid and bromine water.
Step S35: as shown in fig. 31, a third current spreading layer 18 is provided on the roughened surface of the roughened layer 145;
wherein, the third current spreading layer 18 may be an ITO layer or an IZO layer or an AZO layer or an IGZO layer; the thickness of the third current spreading layer 18 may be 0.1-0.5um, such as 0.3um.
Step S36: as shown in fig. 32, a first electrode layer 19 is disposed on a surface of the second ohmic contact layer 146 facing away from the roughened layer 145;
the first electrode layer 19 may be a P-surface electrode, and the electrode material may be Au, pt, zn, or Ti.
Step S37: as shown in fig. 33, the fourth surface of the secondary transfer substrate 21 is polished and thinned, and a second electrode layer 23 is formed on the thinned fourth surface. The second electrode layer 23 may be an N-sided electrode, the electrode material may be Au, pt or AuGe, and the thickness may be 2-6um.
Specifically, the fourth surface may be ground and thinned by using a grinder, and the thickness of the thinned secondary transfer substrate 21 may be 100-250um, for example, 200um.
As can be seen from the above description, in the method for manufacturing a light emitting chip provided by the technical scheme of the present invention, the secondary transfer technology is adopted, so that the light emitting of the P-surface can be realized, and the light extraction efficiency is improved; meanwhile, a dielectric layer is added between the first ohmic contact layer and the metal mirror surface layer, and dielectric holes with specific sizes and quantity are manufactured on the dielectric layer by using a photoetching process, so that the first ohmic contact layer and the metal mirror surface layer in the dielectric holes form ohmic contact, voltage stability is ensured, a chip process window is increased, and the semiconductor, the dielectric layer and the metal mirror surface layer form an omnibearing reflecting mirror structure, so that the reflectivity is greatly improved.
The scheme also has the following advantages:
1. the P surface emits light, and the coarsening process and the current expansion layer are performed on the P surface, so that the thickness of the N-type functional layer can be reduced to about 30% of the previous thickness, the growth time is greatly shortened, and the probability of particle defects in the growth process of the N-type functional layer is reduced.
2. The dielectric layer and the metal mirror surface layer form an omnibearing reflecting mirror structure, the reflectivity is greatly improved, meanwhile, the key metal layer in the dielectric hole is contacted with the first ohmic contact layer, the voltage stability can be ensured, and the chip process window is increased.
3. Since particle defects appear on the surface P-type functional layer after epitaxial growth, the defects are usually falling onto the epitaxial layer from the top cover in the epitaxial growth or in the post-growth cooling stage, P-surface metal bonding is adopted in the conventional process, high temperature and high pressure are adopted in the bonding, and the epitaxial layer is broken by particles attached to the P-surface in the process, so that the local or large-area epitaxial layer falls off, and the yield loss is serious. The technology of transferring and adding N-face metal bonding by using the P-face nonmetal bonding mode replaces conventional P-face bonding, and damage to an epitaxial layer is avoided.
4. GaP refractive index of about 3.34, al for light in 620nm band x Ga 1-x InP (x is usually 0.2-0.4) with refractive index of about 3.4-3.5, and due to low GaP refractive index, the total reflection angle can be increased by adopting P surface light extraction, and the light extraction efficiency can be improved.
In the present specification, each embodiment is described in a progressive manner, or a parallel manner, or a combination of progressive and parallel manners, and each embodiment is mainly described as a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises such element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for manufacturing a light emitting chip, the method comprising the steps of:
s1, providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface which are opposite;
s2, arranging a first functional layer on the first surface, wherein the first functional layer is respectively a buffer layer, a corrosion cut-off layer, a first ohmic contact layer, a first current expansion layer and a first limiting layer from bottom to top;
s3, an active layer is arranged on the surface, deviating from the first current expansion layer, of the first limiting layer;
s4, a second functional layer is arranged on the surface, deviating from the first limiting layer, of the active layer, wherein the second functional layer is a second limiting layer, a transition layer, a window layer, a second current expansion layer, a coarsening layer and a second ohmic contact layer respectively from bottom to top;
s5, a primary transfer structure is arranged on the surface, away from the roughened layer, of the second ohmic contact layer, wherein the primary transfer structure comprises a primary transfer substrate and a consumption layer, and the consumption layer is positioned between the primary transfer substrate and the second ohmic contact layer;
s6, dissolving the semiconductor substrate, the buffer layer and the corrosion-stopping layer by using a solution;
s7, arranging an omnibearing reflecting mirror structure on the surface of one side, away from the first current expansion layer, of the first ohmic contact layer, wherein the reflecting mirror structure comprises a semiconductor, a dielectric layer and a metal mirror layer, and the dielectric layer is positioned between the metal mirror layer and the first ohmic contact layer; the dielectric layer is provided with dielectric holes with preset quantity and size, and the metal mirror layer fills the dielectric holes, so that the first ohmic contact layer and the metal mirror layer in the dielectric holes form ohmic contact;
s8, providing a secondary transfer substrate, wherein the secondary transfer substrate is provided with a third surface and a fourth surface which are opposite;
s9, arranging a bonding metal layer on the third surface;
s10, bonding the bonding metal layer with the metal mirror layer on the surface of one side, facing away from the secondary transfer substrate;
s11, removing the primary transfer substrate and the consumption layer by using a solution dissolving or exposing method;
s12, coarsening the coarsening layer by utilizing coarsening liquid or a dry etching process;
s13, setting a third current expansion layer on the roughened surface of the roughened layer;
s14, a first electrode layer is arranged on the surface of one side, away from the roughened layer, of the second ohmic contact layer;
and S15, grinding and thinning the fourth surface, and forming a second electrode layer on the thinned fourth surface.
2. The method of claim 1, wherein the first functional layer is an N-type functional layer and the second functional layer is a P-type functional layer.
3. The method of claim 1, wherein the sacrificial layer is a colloidal material or a photosensitive material.
4. The method of claim 1, wherein the dielectric layer is SiO 2 Layers or MgF 2 A layer; the thickness of the dielectric layer is
5. The method of claim 1, wherein the metal mirror layer is an Au layer or an Ag layer.
6. The method of claim 1, wherein the bonding metal layer is an Au layer or an Ag layer or an In layer.
7. The method of claim 1, wherein the roughened layer is a GaP layer.
8. The method according to claim 1, wherein in step S10, the bonding pressure is 8000-15000Kg and the bonding temperature is 250-400 ℃.
9. The method according to claim 1, wherein in step S13, the third current spreading layer is an ITO layer or an IZO layer or an AZO layer or an IGZO layer;
the thickness of the third current expansion layer is 0.1-0.5um.
10. The method according to claim 1, wherein in step S15, the thickness of the polished and thinned secondary transfer substrate is 100-250um.
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