CN114142846A

CN114142846A - Aging tracking circuit, electronic device and electronic equipment

Info

Publication number: CN114142846A
Application number: CN202111451676.9A
Authority: CN
Inventors: 钱雅倩; 黄瑞锋; 魏依苒
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-12-01
Filing date: 2021-12-01
Publication date: 2022-03-04

Abstract

The application provides an ageing tracking circuit, electron device and electronic equipment, the circuit includes: the size of a first PMOS transistor in the latch is consistent with that of a PMOS transistor to be tracked in an original circuit and is larger than that of a second PMOS transistor in the latch, and the driving capability of the aged first PMOS transistor is smaller than that of the second PMOS transistor; and the first end of the data pull-down module is connected with the two data storage points of the latch, the second end of the data pull-down module is grounded, the third end of the data pull-down module is used for accessing a control signal, when the original circuit is powered on, the first end is conducted with the second end so as to clear the data in the two data storage points, and after the data in the two data storage points are cleared, the first end is disconnected with the second end. The circuit can simulate the aging condition of the PMOS transistor to be tracked through the first PMOS transistor, and realizes the aging tracking of the PMOS transistor to be tracked.

Description

Aging tracking circuit, electronic device and electronic equipment

Technical Field

The present application relates to the field of circuit technologies, and in particular, to an aging tracking circuit, an electronic device, and an electronic apparatus.

Background

As integrated circuit process dimensions decrease, reliability issues are becoming increasingly more pronounced. Aging is one of the important indicators of device reliability, and describes that the reliability of a device is degraded more and more as the circuit is used for a longer time. The aging effect has an influence on the integrated circuit, which is mainly reflected in that as the service time of the circuit increases, performance degradation occurs on devices in the circuit, such as the threshold voltage of a transistor changes, the leakage current changes, the transconductance changes, and the like.

The most serious one affecting the aging reliability of an integrated circuit is the BTI (Bias Temperature Instability) effect, which is classified into PBTI (Positive Bias Temperature Instability) and NBTI (Negative Bias Temperature Instability) according to the sign of a stressed voltage. The BTI effect causes the transistor threshold voltage to increase and the on-state current to decrease. PBTI occurs in NMOS (N-type Metal-Oxide-Semiconductor) transistors, and the aging problem of NMOS transistors caused by PBTI is not much affected and can be generally ignored. On the contrary, NBTI occurs in a PMOS (P-type Metal Oxide Semiconductor) transistor, and the problem of PMOS transistor aging caused by NBTI is significant and is a main cause of device aging.

The failure mechanism of NBTI is: the PMOS transistor works under negative gate bias voltage (namely, the gate voltage is lower than the source voltage), the circuit works in a high electric field and high temperature condition, the saturated drain current and transconductance are continuously reduced along with the increase of working time, and the threshold voltage is continuously increased, so that the performance of the PMOS transistor is influenced.

The failure mechanism of NBTI is known: in a normally operating circuit, a normally-on PMOS transistor (gate-source voltage always in a negative bias state, i.e., gate voltage always lower than source voltage) is more affected by aging than a flipped PMOS transistor (gate-source voltage varies between positive and negative bias), because the NBTI effect has a partial recovery characteristic, when the gate-source voltage of the PMOS transistor after aging is in a positive bias state, the shifted threshold voltage can be repaired, the device characteristic is partially recovered, and this stage is called as an NBTI recovery stage. For the inverted PMOS transistor, namely the gate-source voltage of the PMOS transistor jumps from negative bias to positive bias, the PMOS transistor carries out NBTI recovery under the positive bias, and the NBTI effect is more and more obvious for the PMOS transistor which is always in a maintaining state, and finally the PMOS transistor can be caused to fail.

Since NBTI may cause the PMOS transistor to degrade in performance, the driving capability of the aged PMOS transistor may be degraded for the circuit, so that the internal delay of the circuit may be increased, and if the delay is too large, the timing problem of the circuit may be caused, thereby causing the whole circuit to fail to work normally.

Disclosure of Invention

An embodiment of the present invention provides an aging tracking circuit, an electronic device, and an electronic apparatus, so as to effectively track an aging condition of a circuit.

The embodiment of the application provides an aging tracking circuit, including:

the latch is composed of a first inverter and a second inverter which are coupled in a cross mode, wherein the first inverter is provided with a first PMOS transistor, and the second inverter is provided with a second PMOS transistor; the size of the first PMOS transistor is consistent with that of a PMOS transistor to be tracked in an original circuit and is larger than that of the second PMOS transistor, and the driving capability of the aged first PMOS transistor is smaller than that of the second PMOS transistor;

the first end of the data pull-down module is connected with the two data storage points of the latch, the second end of the data pull-down module is grounded, and the third end of the data pull-down module is used for accessing a control signal; the first end and the second end are switched on and off under the action of the control signal, wherein when the original circuit is powered on, the first end and the second end are switched on so as to clear data in the two data storage points, and the first end and the second end are switched off after the data in the two data storage points are cleared.

In the implementation circuit, the size of the first PMOS transistor is consistent with the size of the PMOS transistor to be tracked in the original circuit, and in the using process, the size of the first PMOS transistor is larger than the size of the second PMOS transistor, so that the first PMOS transistor is in a normally-on state (which is consistent with the using state of the PMOS transistor to be tracked) when the first PMOS transistor is not aged, and therefore the aging condition of the PMOS transistor to be tracked can be effectively simulated by the first PMOS transistor, and the aging condition of the first PMOS transistor can effectively represent the aging condition of the PMOS transistor to be tracked.

And when the first PMOS transistor is not aged, the first PMOS transistor is normally open, and the driving capability of the first PMOS transistor is greater than that of the second PMOS transistor, so that the data in the second storage data point at the grid electrode of the second PMOS transistor is 1, and the data in the first storage data point at the grid electrode of the first PMOS transistor is 0. When the first PMOS transistor is aged, since the driving capability of the first PMOS transistor is smaller than that of the second PMOS transistor, after the original circuit is powered up again and the data pull-down module clears the data in the latch, the second PMOS transistor in the latch is normally open, so that the data in the first storage data point is 1, and the data in the second storage data point is 0. Therefore, when the original circuit is powered on again every time, whether the PMOS transistor to be tracked in the original circuit is aged or not can be effectively determined based on the data value in any data storage point in the latch, and the aging tracking of the PMOS transistor to be tracked is realized.

The realization circuit is simple in realization structure, the PMOS transistor to be tracked is simulated through the PMOS transistor in the latch, and the realization circuit is applicable to various original circuits (such as memories, logic circuits, large-scale integrated circuits and the like) with the aging tracking requirement of the PMOS transistor, wide in application range and high in industrial application value.

Further, the data pull-down module comprises a first NMOS transistor and a second NMOS transistor; the two data storage points are a first data storage point and a second data storage point; the drains of the first NMOS transistor and the second NMOS transistor jointly form the first end; wherein the drain of the first NMOS transistor is connected to the first data storage point and the drain of the second NMOS transistor is connected to the second data storage point; the source electrodes of the first NMOS transistor and the second NMOS transistor are the second ends and are both grounded; the grid electrodes of the first NMOS transistor and the second NMOS transistor are the third ends and are both connected to the control signal; when the original circuit is powered on, the control signal is a high-level signal; and after the data in the two data storage points are cleared, the control signal is a low-level signal.

In the implementation circuit, the data pull-down module is formed by two NMOS transistors, and the sources of the two NMOS transistors are grounded, so that when a high-level control signal is input to the gate, the gate-source voltage is forward biased (i.e., the gate voltage is higher than the source voltage), and the source and the drain of the NMOS transistor are conducted, so that two data storage points in the latch are grounded, zero clearing of data in the latch is realized, and the latch can perform data latching again. The whole data pull-down module is simple in structure, cannot cause the aging tracking circuit to be complicated, and is convenient to arrange in various electronic elements with the aging tracking requirement of the PMOS transistor.

Further, the aging tracking circuit further includes: and the signal stabilizing module is connected with any one of the two data storage points and is used for outputting the data in the data storage points as a stable signal.

It will be appreciated that in actual practice, the data in the latch may not be a standard "0" signal or "1" signal, resulting in the output of the data being misidentified. Through the implementation structure, the data in the data storage point can be output in a stable signal, and the reliability of data reading and output is ensured.

Further, the signal stabilization module is an inverter and/or a buffer.

In the above implementation scheme, the data in the data storage point is processed by the inverter and/or the buffer and then output, and the processed data is stabilized to a standard "0" signal or "1" signal in the signal inverter or buffer, thereby ensuring the reliability of data reading and output.

Further, the aging tracking circuit further includes:

the circuit repairing module comprises a control end, a first input end, a first output end, a second input end and a second output end;

the first input end is used for accessing an input signal of the original circuit, and the first output end is used for accessing an input end of the original circuit; the second input end is used for being connected to the output end of the original circuit so as to receive the output signal of the original circuit;

the control end is connected with any one of the two data storage points;

the circuit repair module is used for connecting the data storage points according to the signals of the connected data storage points: performing an inverting operation on the input signal of the original circuit, outputting the inverted input signal to the original circuit through the first output end, performing an inverting operation on the output signal of the original circuit, and outputting the inverted output signal through the second output end; or, the input signal of the original circuit is output to the original circuit through the first output end, and the output signal of the original circuit is output through the second output end.

In the implementation circuit, the circuit repairing module performs an inverting or non-inverting operation on the input signal of the original circuit according to the signal of the data storage point of the latch. Therefore, after the first PMOS transistor is aged, the data in the data storage point can be overturned relative to the data before the first PMOS transistor is aged, so that the signals input into the original circuit through the circuit repairing module after the PMOS transistor to be tracked is aged are traced, and the signals input into the original circuit before the first PMOS transistor is aged can also be overturned relative to the signals input into the original circuit before the first PMOS transistor is aged, so that the PMOS transistor to be tracked in the original circuit can be subjected to NBTI recovery, and the effect of self-repairing of the PMOS transistor to be tracked is achieved.

In addition, after the first PMOS transistor is aged, the driving capacity of the first PMOS transistor is lower than that of the second PMOS transistor, so that the second PMOS transistor is normally opened in the latch, and the gate-source voltage of the first PMOS transistor keeps a forward bias state, so that the first PMOS transistor and the PMOS transistor to be traced carry out NBTI recovery together, and the first PMOS transistor can still have a good aging tracing effect in the self-repairing process of the PMOS transistor to be traced.

Further, the circuit repair module includes: an input inverter, an output inverter, a first multiplexer, and a second multiplexer; one end of the input reverser is the first input end, and the other end of the input reverser is connected to the first multiplexer; one input end of the first multiplexer is the first input end, and the other input end of the first multiplexer is connected with the input reverser; the output end of the first multiplexer is the first output end; one end of the output reverser is the second input end, and the other end of the output reverser is connected to the second multiplexer; one input end of the second multiplexer is the second input end, and the other input end of the second multiplexer is connected with the output inverter; the output end of the second multiplexer is the second output end; the control ends of the first multiplexer and the second multiplexer are connected with any one of the two data storage points; the first multiplexer and the second multiplexer are used for receiving the signals of the connected data storage points: gating the input inverter and the output inverter; or gating the input signal of the original circuit and the output signal of the original circuit.

In the implementation circuit, the circuit repair module is realized only by the two inverters and the two multiplexers, the circuit structure is very simple, the circuit repair module is favorable for being arranged in an electronic device without causing obvious change of the size of the electronic device, the influence on PPA (Performance, Power and Area) of the electronic device is small, and the circuit repair module has high practical application value.

Further, the first multiplexer and the second multiplexer are specifically configured to: gating the input inverter and the output inverter when the first PMOS transistor is not aging; gating an input signal of the original circuit and an output signal of the original circuit as the first PMOS transistor ages.

In the implementation scheme, when the first PMOS transistor is not aged, the input inverter and the output inverter are gated, and when the first PMOS transistor is aged, the input signal of the original circuit and the output signal of the original circuit are gated, so that when the first PMOS transistor is aged, the path taken by the input signal of the original circuit is reduced by two stages of inverters compared with the path taken before the aging, the delay of the whole circuit is reduced, and the timing problem caused by the circuit delay caused by the aging of the PMOS transistor to be tracked is repaired to a certain extent.

Further, the two data storage points are a first data storage point and a second data storage point; the first data storage point is a data storage point connected with the grid electrode of the first PMOS transistor; the second data storage point is a data storage point connected with the grid electrode of the second PMOS transistor; the control end is connected with a second data storage point in the latch through a third inverter; the first multiplexer is used for gating the input inverter when the control end inputs a low level and gating the input signal of the original circuit when the control end inputs a high level; and the second multiplexer is used for gating the output inverter when the control end inputs a low level and gating the output signal of the original circuit when the control end inputs a high level.

In the implementation process, the third inverter can ensure that the control signals output to the two multiplexers are stable, the input inverter and the output inverter are gated when the first PMOS transistor is not aged, and the input signal of the original circuit and the output signal of the original circuit are gated when the first PMOS transistor is aged, so that the delay of the whole circuit is reduced, and the time sequence problem caused by circuit delay due to aging of the PMOS transistor to be tracked is repaired to a certain extent.

An embodiment of the present application further provides an electronic device, including: a primitive circuit having a PMOS transistor to be tracked, and an aging tracking circuit of any of the above.

The embodiment of the application also provides electronic equipment comprising the electronic device.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic diagram illustrating a basic structure of an aging tracking circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of an aging tracking circuit with a detailed data pull-down module according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of an aging tracking circuit having a signal stabilizing module according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of an aging tracking circuit having a circuit repairing module according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of an aging tracking circuit with a detailed circuit repair module structure according to an embodiment of the present disclosure;

FIG. 6 is a more detailed schematic diagram of an aging tracking circuit according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of an exemplary aging tracking circuit according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a 6T SRAM Cell circuit according to an embodiment of the present disclosure;

fig. 9 is a timing diagram of a circuit when it is not aged according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

Example (b):

in order to realize effective tracking of the aging condition of the circuit, the embodiment of the application provides an aging tracking circuit. Referring to fig. 1, fig. 1 is a basic schematic diagram of an aging tracking circuit provided in an embodiment of the present application, including: latch 1 and data pull-down module 2.

Wherein the latch 1 is formed by a first inverter 11 and a second inverter 12 which are cross-coupled. The first inverter has a first PMOS transistor 111 therein and the second inverter has a second PMOS transistor 112 therein.

It should be understood that a latch is a memory cell circuit that temporarily stores a signal, and has two data storage points, which are located at the gate of the first PMOS transistor 111 and the gate of the second PMOS transistor 111, respectively. For convenience of description, in the embodiment of the present application, it is noted that the data storage point at the gate of the first PMOS transistor 111 is the first data storage point K1, and the data storage point at the gate of the second PMOS transistor 111 is the second data storage point K2.

In the embodiment of the present application, the size of the first PMOS transistor 111 should be consistent with the size of the PMOS transistor to be tracked in the original circuit, so as to ensure that the first PMOS transistor 111 can effectively simulate the PMOS transistor to be tracked.

It should be noted that, in the embodiment of the present application, the original circuit refers to a circuit having the aging tracking requirement of the PMOS transistor, which may be a Memory, a logic circuit, a large scale integrated circuit, and the like, and is not limited in the embodiment of the present application.

It should be further noted that, in the embodiment of the present application, in order to ensure that the first PMOS transistor 111 can effectively simulate a PMOS transistor to be tracked, the size of the first PMOS transistor 111 should be larger than that of the second PMOS transistor 121, and the driving capability of the first PMOS transistor 111 after aging should be smaller than that of the second PMOS transistor 121.

Thus, when the first PMOS transistor 111 is not aged, since the size of the first PMOS transistor 111 is larger than that of the second PMOS transistor 121, and the driving capability of the first PMOS transistor 111 is larger than that of the second PMOS transistor 121, the first PMOS transistor 111 is normally on, and is affected by NBTI effect together with the PMOS transistor to be tracked in the original circuit, and the second PMOS transistor 121 is turned off. At this time, the data in the first stored data point K1 is 0, and the data in the second stored data point K2 is 1.

When the first PMOS transistor 111 ages, the driving capability of the first PMOS transistor 111 degrades to a level less than the driving capability of the second PMOS transistor 121, at which time the first PMOS transistor 111 is turned off and the second PMOS transistor 121 is normally on. At this time, the data in the first stored data point K1 is 1, and the data in the second stored data point K2 is 0.

Therefore, based on the data in the first stored data point K1 or the data in the second stored data point K2, it can be determined effectively whether the first PMOS transistor 111 is aging.

Since the latch stores data each time it is held constant in the latch. Therefore, in the embodiment of the present application, the data pull-down module 2 is adopted to clear the data stored in the latch 1 after each time the original circuit is powered on, so as to ensure that the latch 1 can store the data again, and therefore, the latch 1 can update the data representing whether the first PMOS transistor 111 is aged or not and realize the aging tracking when each time the original circuit is powered on.

In order to enable the data pull-down module 2 to clear the data stored in the latch 1, in the embodiment of the present application, the first end of the data pull-down module 2 is connected to two data storage points K1 and K2 of the latch 1; the second terminal of the data pull-down module 2 is grounded, and the third terminal is used for accessing a control signal DCH. The first terminal and the second terminal are switched on and off under the action of the control signal DCH. When the original circuit is powered on, the first end and the second end are conducted, and at the moment, the data storage points K1 and K2 are directly grounded, so that the data in the two data storage points are cleared. After the data in the two data storage points K1 and K2 are cleared, the first terminal is disconnected from the second terminal, so that latch 1 can be operated normally again.

It should be understood that, in the embodiment of the present application, the data pull-down module 2 may be implemented by a device having a controlled switching function.

For example, as shown in fig. 2, the data pull-down module 2 may include a first NMOS transistor 21 and a second NMOS transistor 22. Wherein:

the drains of the first NMOS transistor 21 and the second NMOS transistor 22 together constitute a first terminal. The drain of the first NMOS transistor 21 is connected to the first data storage point K1, and the drain of the second NMOS transistor 22 is connected to the second data storage point K2.

And the sources of the first NMOS transistor 21 and the second NMOS transistor 22 constitute second terminals, both of which are grounded.

And the gates of the first NMOS transistor 21 and the second NMOS transistor 22 form a third terminal, and are both connected to the control signal DCH.

The control signal DCH is a high level signal output when the original circuit is powered on, and is a low level signal output after the data in the two data storage points K1 and K2 are cleared.

It should be understood that, in the embodiment of the present application, in addition to the structure shown in fig. 2, the data pull-down module 2 may also be implemented by other structures. For example, the NMOS transistor in the above example may be replaced with an NPN type transistor. In the embodiment of the present application, as long as a circuit structure for controllably connecting and disconnecting the data storage points K1 and K2 to and from the ground line can be implemented, the data pull-down module 2 in the embodiment of the present application can be adopted.

It will be appreciated that in actual practice, the data in the latch may not be a standard "0" signal or "1" signal, resulting in the output of the data being misidentified. For this reason, optionally, in the embodiment of the present application, referring to fig. 3, any one of the data storage points K1 and K2 may be connected to the signal stabilization module 3, so that the signal in the data storage point is output as a stabilized signal by the signal stabilization module 3, thereby ensuring the reliability of reading and outputting the signal.

In the embodiment of the present application, the signal stabilizing module 3 may be implemented by an inverter, a buffer, or the like, or a combination of devices having signal stabilizing capability, but is not limited thereto.

It should be noted that, in order to ensure the tracking effect, in the embodiment of the present application, the original circuit may be disposed in the electronic device, and the aging tracking circuit provided in the embodiment of the present application may be disposed together, so as to ensure that the first PMOS transistor 111 and the PMOS transistor to be tracked are in the same usage environment, and ensure the reliability of the aging tracking effect.

Optionally, in the embodiment of the present application, referring to fig. 4, the aging tracking circuit may further include a circuit repairing module 4. Wherein:

the circuit repair module 4 comprises a control terminal a1, a first input terminal a2, a first output terminal A3, a second input terminal a4 and a second output terminal a 5.

The first input terminal a2 is used for receiving the input signal DI of the original circuit 5, and the first output terminal A3 is used for receiving the input terminal of the original circuit 5; the second input terminal a4 is used for connecting to the output terminal of the original circuit to receive the output signal of the original circuit.

The control terminal a1 is connected to any one of two data storage points K1 and K2.

And the circuit repairing module 4 is used for executing one of the following two operations according to the difference of the signals of the connected data storage points:

operation one: the input signal DI of the original circuit 5 is inverted, the inverted input signal (denoted as DI') is output to the original circuit 5 through the first output terminal A3, the inverted output signal of the original circuit 5 is inverted, and the inverted output signal is output through the second output terminal a 5.

And operation II: the input signal DI of the original circuit 5 is directly output to the original circuit 5 through the first output terminal A3, and the output signal of the original circuit 5 is directly output through the second output terminal a 5.

It should be understood that assuming that circuit repair block 4 is not added, the input signal to original circuit 5 is DI and the output signal is DO.

After the circuit repairing module 4 is added, in the first operation, since the signal input to the original circuit 5 is DI ', the signal output from the original circuit 5 to the circuit repairing module 4 is the inverted signal DO ' of DO, so that after the DO ' is inverted by the circuit repairing module 4, the DO output by the circuit repairing module 4 can be ensured. In the second operation, the signal input to the original circuit 5 is DI, the signal output from the original circuit 5 to the circuit repairing module 4 is DO, and since the inversion operation is not performed in the second operation, the signal output from the circuit repairing module 4 is DO. Therefore, the addition of the circuit repairing module 4 does not cause the change of the signal DO output to other circuits, and the increase of the circuit repairing module 4 is ensured not to cause the disorder of the circuit signal logic.

And the circuit repairing module 4 is added, and the circuit repairing module 4 performs an inverting operation or non-inverting operation on the input signal of the original circuit according to the signal of the data storage point of the latch 1. Then, after the first PMOS transistor 111 is aged, the data in the data storage point will be inverted relative to the data before being aged, so that the signal input into the original circuit 5 through the circuit repairing module 4 after the PMOS transistor to be traced is aged is also inverted relative to the signal input into the original circuit 5 before being aged, so that the PMOS transistor to be traced in the original circuit can perform NBTI recovery, thereby achieving the effect of self-repairing the PMOS transistor to be traced.

For example, assuming that the circuit repairing module 4 performs operation one when the first PMOS transistor 111 is not aged, the data in the original circuit 5 is DI', and the PMOS transistor to be tracked keeps a normally-open working state. When the first PMOS transistor 111 ages, the data in the original circuit 5 is changed to DI, the data is inverted, the gate-source voltage of the PMOS transistor to be tracked is forward biased, and NBTI recovery is performed, so that the effect of self-repairing the PMOS transistor to be tracked can be achieved.

It should be understood that, in the embodiment of the present application, after the first PMOS transistor is aged, the driving capability of the first PMOS transistor is lower than that of the second PMOS transistor, which causes the latch to be normally open, and the gate-source voltage of the first PMOS transistor is kept in a forward bias state, so that the first PMOS transistor and the PMOS transistor to be tracked can also perform NBTI recovery, thereby further ensuring that the first PMOS transistor is also autonomously repaired in the autonomous repairing process of the PMOS transistor to be tracked, thereby ensuring that the aging condition of the first PMOS transistor can always effectively represent the aging condition of the PMOS transistor to be tracked, and thus having a good aging tracking effect all the time.

For example, referring to fig. 5, the circuit repair module 4 may include: an input inverter 41, an output inverter 42, a first multiplexer 43, and a second multiplexer 44. Wherein:

the input inverter 41 has a first input terminal a2 at one end and a first multiplexer 43 at the other end.

One input terminal of the first multiplexer 43 is also used as the first input terminal a2, and is directly connected to the input signal DI of the original circuit 5. The other input terminal is connected to the input inverter 41. While the output of the first multiplexer 43 is connected as a first output a3 to the original circuit 5.

One end of the output inverter 42 is connected to the input signal DI as a second input terminal a4, and the other end is connected to the second multiplexer 44.

One input end of the second multiplexer 44 is also used as a second input end a4, and is connected to the input signal DI. And the other input terminal is connected to the output inverter 42. The output of the second multiplexer 44 serves as a second output a5 for outputting the final output signal DO.

The control terminals a1 of the first and

second multiplexers

43 and 44 are each connected to any one of the two data storage points K1 and K2.

The first multiplexer 43 and the second multiplexer 44 are used for, based on the signals of the connected data storage points: a gated input inverter and output inverter 42; or, the input signal DI of the original circuit 5 and the output signal of the original circuit 5 are gated.

Therefore, the circuit repairing module 4 is realized only by the two inverters and the two multiplexers, the circuit structure is very simple, the circuit repairing module is favorable for being arranged in an electronic device without causing obvious change of the size of the electronic device, the influence on the PPA of the electronic device is small, and the practical application value is high.

Considering that the PMOS transistor aging will cause the internal delay of the circuit to become large, and even cause the timing problem of the circuit, thereby causing the whole circuit to work improperly. For this reason, in the embodiment of the present application, it is possible to gate the input inverter 41 and the output inverter 42 by setting the gate patterns of the two multiplexers such that the first PMOS transistor 111 is not aged; as the first PMOS transistor 111 ages, the input signal DI of the original circuit 5 and the output signal of the original circuit 5 are gated. Therefore, when the first PMOS transistor 111 tracks the aging of the PMOS transistor to be tracked, the path taken by the input signal DI of the original circuit is reduced by two stages of inverters (i.e. the input inverter 41 and the output inverter 42 are reduced) compared with the path before aging, so that the delay of the whole circuit is reduced, and the timing problem caused by the circuit delay due to the aging of the PMOS transistor to be tracked is repaired to a certain extent.

Illustratively, referring to FIG. 6, the control terminal is coupled to a second data storage point K2 in latch 1 through a third inverter M. The first multiplexer 43 is used to gate the input inverter 41 when the control terminal a1 inputs a low level and gate the input signal DI of the original circuit 5 when the control terminal a1 inputs a high level. The second multiplexer 44 is used to gate the output inverter 42 when the control terminal a1 inputs a low level and to gate the output signal of the original circuit 5 when the control terminal a1 inputs a high level.

Thus, when the first PMOS transistor 111 is not aged, the data K2 is 0, inverted by the third inverter M, and outputted to the first multiplexer 43 and the second multiplexer 44 as a high level signal. At this time, the input inverter 41 and the output inverter 42 are turned on, and the signal input to the original circuit 5 is DI'.

When the first PMOS transistor 111 ages and is powered up again, the data K2 is 1, and is inverted by the third inverter M and output to the first multiplexer 43 and the second multiplexer 44 as a low-level signal. At this time, the original circuit is directly conducted with DI, the signal input to the original circuit 5 is DI, and the output of the original circuit 5 is DO. When the first PMOS transistor 111 tracks the aging of the PMOS transistor to be tracked, the path taken by the input signal DI of the original circuit is reduced compared with the path taken before the aging, so that the effect of two-stage inverters is reduced, and the timing problem caused by circuit delay due to the aging of the PMOS transistor to be tracked is repaired to a certain extent.

In order to facilitate understanding of the solutions provided in the embodiments of the present application, a specific exemplary structure is taken as an example below to further illustrate the solutions of the present application.

Referring to fig. 7, the original circuit 5 is the 6T SRAM Cell (6T SRAM Cell) circuit shown in fig. 8.

For the 6T SRAM Cell circuit shown in fig. 8, assuming that point Q is 0 and QB is 1, the data read from the Cell is correct data 0 when no significant aging occurs. If Q and QB are maintained at 0 and 1 all the time, the PMOS transistor PUR is always in a negatively biased state and the aging problem becomes severe over time, resulting in the possibility that the Cell will read the opposite data.

With the aging tracking circuit shown in fig. 7 of the present application, before the 6T SRAM Cell circuit ages:

when the 6T SRAM Cell circuit starts to operate, the 6T SRAM Cell circuit is powered on, i.e., PowerOK ═ 1. After the PowerOK is stabilized, the DCH inputs a high signal to turn on the first NMOS transistor 21 and the second NMOS transistor 22 in fig. 7, and the points K1 and K2 are both pulled down to 0. Then DCH becomes a low level signal, and the first NMOS transistor 21 and the second NMOS transistor 22 are turned off.

For a normally operating circuit, i.e. a circuit without aging, since the driving capability of the first NMOS transistor 21 is stronger than that of the second NMOS transistor 22, K1 is pulled up to 1, and finally a stable control signal 0 is generated through the third inverter M. When the first multiplexer 43 receives the control signal 0, the input signal DI is selectively transmitted to the inside of the 6T SRAM Cell circuit through the input inverter 41. Similarly, the second multiplexer 44 also receives the control signal 0, and the finally read data DO is obtained through the output inverter 42. This approach ensures that the read Data (DO) and the written Data (DI) are identical, i.e., read and write are correct, but the data stored inside the 6T SRAM Cell is DI, which is the inverse of DI^’. If the circuit does not have aging problem, the circuit in fig. 7 is normally operated according to the above procedure at each power-onIn operation, the timing diagram of the circuit is shown in FIG. 9.

After the 6T SRAM Cell circuit ages: that is, when the circuit is operated for a long time and the transistors in the Keep initial state for a long time, the aging problem is serious, and the performance of the PMOS transistors inside the 6T SRAM Cell is degraded.

In the latch 1, after the 6T SRAM Cell circuit is powered on, the latch is also kept in a holding state, the first PMOS transistor 111 is in a negative bias state, and after long-term aging, the pull-up driving capability of the first PMOS transistor 111 is weaker than that of the second PMOS transistor 121. When the circuit is next powered up, the DCH generates a high signal to pull down the data at points K1 and K2 to 0 and then to a low state. At this time, the pull-up driving capability of the second PMOS transistor 121 is stronger than that of the first PMOS transistor 111, so that K1 is pulled up to 1, and K2 is maintained at 0. Finally K2 generates a stable control signal 1 through the third inverter M. When the first multiplexer 43 receives the control signal 1, the input terminal of the first multiplexer 43 selects one of the paths without the inverter, and directly inputs the DI into the 6T SRAM Cell circuit. Similarly, the second multiplexer 44 also receives the control signal 1, outputs a path without an inverter, and directly transmits the output signal of the 6T SRAM Cell circuit to the outside of the circuit to obtain DO, and the read data DO is also consistent with the input data DI, and the reading and writing are correct. The data stored in the 6T SRAM Cell circuit at this time is the same as the input signal DI.

The data stored in the 6T SRAM Cell circuit before aging is opposite to the data stored after aging, so that the 6T SRAM Cell circuit affected by aging can be recovered. In addition, the paths taken by the DI after the aging repair are reduced by two stages of inverters compared with the paths taken before the aging repair, so that the circuit delay caused by the aging is effectively compensated and repaired.

For latch 1, the values stored in k1 and k2 before and after aging repair are opposite, and in the process of repairing the original circuit 5, the first PMOS transistor 111 of the latch 1 can also be repaired, so that the whole circuit can be ensured to work normally all the time.

Also provided in embodiments of the present application is an electronic device that includes a primitive circuit having a PMOS transistor to be tracked, and an aging tracking circuit of any of the foregoing.

In the embodiment of the present application, the electronic device may have a circuit board in which the above-described original circuit and the burn-in trace circuit are uniformly disposed.

In the embodiment of the present application, the electronic device may be, but is not limited to, an electronic device having an aging tracking requirement of a PMOS transistor, such as a memory, a CPU, or the like.

The embodiment of the application also provides electronic equipment which comprises the electronic device. By way of example, the electronic device may be, but is not limited to, a server, a host, a computer, a mobile phone, etc. having an electronic device with PMOS transistor aging tracking requirements inside.

According to the aging tracking circuit, the electronic device and the electronic equipment, the size of the first PMOS transistor is consistent with that of the PMOS transistor to be tracked in the original circuit, and in the using process, the size of the first PMOS transistor is larger than that of the second PMOS transistor, so that the first PMOS transistor is in a normally-on state when not aged (the normally-on state is consistent with the using state of the PMOS transistor to be tracked), the aging condition of the PMOS transistor to be tracked can be effectively simulated by the first PMOS transistor, and the aging condition of the PMOS transistor to be tracked can be effectively represented.

In addition, according to the scheme provided by the embodiment of the application, the circuit implementation structure is simple, the PMOS transistor to be tracked is simulated through the PMOS transistor in the latch, the method and the device are applicable to various original circuits (such as memories, logic circuits, large-scale integrated circuits and the like) with the aging tracking requirements of the PMOS transistor, the application range is wide, and the industrial application value is high.

In addition, according to the scheme provided by the embodiment of the application, after the PMOS transistor to be tracked is aged, the signal input into the original circuit through the circuit repairing module is turned over relative to the signal input into the original circuit before aging through the circuit repairing module, so that the PMOS transistor to be tracked in the original circuit can be subjected to NBTI recovery, and the effect of autonomously repairing the PMOS transistor to be tracked is achieved.

In addition, according to the scheme provided by the embodiment of the application, the input inverter and the output inverter can be gated when the first PMOS transistor is not aged; as the first PMOS transistor ages, the input signal of the original circuit and the output signal of the original circuit are gated. In the aging process, compared with the path taken by the input signal of the original circuit before aging, two stages of inverters are reduced, so that the delay of the whole circuit is reduced, and the time sequence problem caused by the circuit delay caused by the aging of the PMOS transistor to be tracked is repaired to a certain extent.

In the embodiments provided in the present application, it should be understood that the disclosed circuit structure may be implemented in other manners. The embodiments described above are merely illustrative.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

In this context, a plurality means two or more.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An aging tracking circuit, comprising:

2. The aging tracking circuit of claim 1, wherein the data pull-down module comprises a first NMOS transistor and a second NMOS transistor; the two data storage points are a first data storage point and a second data storage point;

the drains of the first NMOS transistor and the second NMOS transistor jointly form the first end; wherein the drain of the first NMOS transistor is connected to the first data storage point and the drain of the second NMOS transistor is connected to the second data storage point;

the source electrodes of the first NMOS transistor and the second NMOS transistor are the second ends and are both grounded;

the grid electrodes of the first NMOS transistor and the second NMOS transistor are the third ends and are both connected to the control signal; when the original circuit is powered on, the control signal is a high-level signal; and after the data in the two data storage points are cleared, the control signal is a low-level signal.

3. The aging tracking circuit of claim 1, further comprising:

and the signal stabilizing module is connected with any one of the two data storage points and is used for outputting the data in the data storage points as a stable signal.

4. The aging tracking circuit of claim 3, wherein the signal stabilization module is an inverter and/or a buffer.

5. The aging tracking circuit of any of claims 1-4, further comprising:

the control end is connected with any one of the two data storage points;

6. The aging tracking circuit of claim 5, wherein the circuit repair module comprises: an input inverter, an output inverter, a first multiplexer, and a second multiplexer;

one end of the input reverser is the first input end, and the other end of the input reverser is connected to the first multiplexer;

one input end of the first multiplexer is the first input end, and the other input end of the first multiplexer is connected with the input reverser; the output end of the first multiplexer is the first output end;

one end of the output reverser is the second input end, and the other end of the output reverser is connected to the second multiplexer;

one input end of the second multiplexer is the second input end, and the other input end of the second multiplexer is connected with the output inverter; the output end of the second multiplexer is the second output end;

the control ends of the first multiplexer and the second multiplexer are connected with any one of the two data storage points;

the first multiplexer and the second multiplexer are used for receiving the signals of the connected data storage points: gating the input inverter and the output inverter; or gating the input signal of the original circuit and the output signal of the original circuit.

7. The aging tracking circuit of claim 6, wherein the first multiplexer and the second multiplexer are specifically to: gating the input inverter and the output inverter when the first PMOS transistor is not aging; gating an input signal of the original circuit and an output signal of the original circuit as the first PMOS transistor ages.

8. The aging tracking circuit of claim 6, wherein the two data storage points are a first data storage point and a second data storage point; the first data storage point is a data storage point connected with the grid electrode of the first PMOS transistor; the second data storage point is a data storage point connected with the grid electrode of the second PMOS transistor;

the control end is connected with a second data storage point in the latch through a third inverter;

the first multiplexer is used for gating the input inverter when the control end inputs a low level and gating the input signal of the original circuit when the control end inputs a high level;

and the second multiplexer is used for gating the output inverter when the control end inputs a low level and gating the output signal of the original circuit when the control end inputs a high level.

9. An electronic device, comprising: a raw circuit having PMOS transistors to be tracked, and an aging tracking circuit as claimed in any of claims 1 to 8.

10. An electronic device characterized by comprising the electronic device of claim 9.