JP6578413B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  In SRAM (Static Random Access Memory) which is one of semiconductor memory devices, various proposals have been made for reducing leakage current.

  For example, a technology has been proposed in which the leakage current is reduced by raising the source potential of the memory cell from the VSS level during the resume standby of the SRAM (Patent Document 1). In this technique, 0.4 V is applied to the source potential of the memory cell. On the other hand, 1.0 V is applied to the bit line as a power supply potential.

  In addition, in order to prevent an excessive leak current from flowing due to a hardware failure such as the internal node of the memory cell being fixed at the LOW level, a technique for bringing the bit line into a floating state during resume standby is shown ( Patent Document 2).

  In the resume standby mode of the resume standby circuit, channel leakage is reduced by floating the NMOS source potential of the memory cell from the VSS level, thereby reducing the leakage current of the entire module. At that time, a voltage that is VDD level or a voltage that falls from Vth of NMOS to Vth has been applied to the bit line. On the other hand, in the recent miniaturization process, leakage current from the bit line to the access transistor substrate is large due to GIDL (Gate Induced Drain Leakage), and the leakage current cannot be reduced so much in a normal resume standby circuit especially at room temperature. It was.

JP 2004-206745 A JP 2010-198729 A

  However, the inventor has found that the above-described technique has the following problems. In a recent miniaturization process, leakage current from the bit line to the access transistor substrate due to GIDL (Gate Induced Drain Leakage) cannot be ignored. In particular, the GIDL component is dominant over the channel leak component at room temperature. For this reason, the resume current circuit disclosed in Patent Document 1 in which the source potential of the memory cell is raised from the VSS level cannot effectively reduce the leakage current at room temperature. Further, as disclosed in Patent Document 2, if the bit line is made floating during the resume standby, not only a hardware failure but also leakage current from the bit line due to GIDL can be reduced. However, in Patent Document 2, the source potential of the memory cell is at the VSS level, and the leakage current cannot be effectively reduced at a high temperature. Further, as a problem of floating the bit line, there is an increase in peak current at the time of resume. When the bit line is floated, the bit line potential is lowered to the VSS level due to a leakage current or the like in some cases. When returning from the resume standby mode to the normal operation mode, the bit line is charged from the VSS level to the VDD level by the precharge transistor. In normal operation, the number of bit lines charged is one bit line pair for each MUX (Y address multiplexer) and True / Bar, so the number of bit lines charged at one time is Limited to the total number of bit lines / MUX / 2. On the other hand, when returning from the resume standby mode to the normal operation mode, all the bit lines may be charged simultaneously. The precharge transistor is designed with a sufficiently large size because it is necessary to charge the bit line to the VDD level in one cycle during normal operation. Therefore, if all the bit lines are charged simultaneously with the precharge transistor, a very large peak current flows, and there is a possibility that an instantaneous voltage drop may occur. FIG. 11 is a diagram schematically showing a voltage drop at the time of precharging the semiconductor memory device. When the voltage drops, for example, other analog circuits or logic circuits in the vicinity may malfunction. Moreover, there is a risk of causing a reliability failure such as electromigration.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor device according to an embodiment includes a power supply line, a plurality of word lines, a plurality of bit line pairs, a plurality of memory cells each connected to one word line and the plurality of pairs of bit lines. A plurality of input / output circuits connected to each of the plurality of bit line pairs, each including a first precharge circuit and a second precharge circuit, and a first control signal being input and a second control signal being output. A delay circuit, wherein the first precharge circuit has a source / drain path between the power supply line and one bit line of the bit line pair connected to the first precharge circuit. A first PMOS transistor having a gate electrode to which the first control signal is input, the power supply line, and the other bit line of the bit line pair connected to the first precharge circuit. Source / drain A second PMOS transistor having a path and a gate electrode to which the first control signal is input, wherein the second precharge circuit is connected to the power supply line and the second precharge circuit. A third PMOS transistor having a source / drain path between one of the paired bit lines and the second control signal being input to the gate electrode; the power supply line; A fourth PMOS transistor having a source / drain path between the other bit line of the pair of bit lines connected to the precharge circuit and the second control signal being input to the gate electrode; The first precharge circuit connects the power supply line and the bit line pair connected to the first precharge circuit in response to the first control signal, and the second precharge circuit The second Depending on the control signal, and the power line, and connects a bit line pair connected to said second precharge circuit.

  According to the embodiment, in the semiconductor memory device, it is possible to suppress the current of the bit line precharge when switching the operation mode while reducing the leakage current.

1 is a block diagram schematically showing a configuration of a semiconductor memory device according to a first embodiment; 1 is a circuit diagram showing in more detail the configuration of a semiconductor memory device according to a first embodiment; It is a figure which shows the structural example of a delay circuit. FIG. 3 is a timing diagram of signals in the semiconductor memory device according to the first embodiment; FIG. 3 is a circuit diagram schematically showing a configuration of a semiconductor memory device according to a second embodiment; FIG. 6 is a block diagram schematically showing a configuration of a semiconductor memory device according to a third embodiment. 4 is a circuit diagram showing a word line driver and memory cells according to a third embodiment; FIG. FIG. 6 is a signal timing diagram in the semiconductor memory device according to the third embodiment; FIG. 6 is a circuit diagram schematically showing a configuration of a semiconductor memory device according to a fourth embodiment; FIG. 9 is a signal timing diagram in the semiconductor memory device according to the fourth embodiment; It is a figure which shows typically the voltage drop at the time of the precharge of a semiconductor memory device.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted as necessary.

Embodiment 1
A semiconductor memory device 100 according to the first embodiment will be described. FIG. 1 is a block diagram schematically showing a configuration of the semiconductor memory device 100 according to the first embodiment. FIG. 2 is a circuit diagram showing in more detail the configuration of the semiconductor memory device 100 according to the first embodiment. As shown in FIGS. 1 and 2, the semiconductor memory device 100 is configured as an SRAM. The semiconductor memory device 100 includes a memory cell 1, an I / O circuit 2, and an operation mode control circuit 3.

  Hereinafter, the semiconductor memory device 100 has a plurality of memory cells, a plurality of word lines, and a plurality of bit line pairs. However, since the configuration of the memory cell, the word line, and the bit line pair is common, the following embodiments do not distinguish between the plurality of memory cells, the plurality of word lines, and the plurality of bit line pairs.

  The memory cell 1 includes NMOS transistors N1 to N4 and PMOS transistors P1 and P2. In the memory cell 1, the NMOS transistors N1 and N2 function as transfer transistors. The NMOS transistors N3 and N4 function as drive transistors. The PMOS transistors P1 and P2 function as a load.

  The drain of the NMOS transistor N1 is connected to the bit line BT. The drain of the NMOS transistor N2 is connected to the bit line BB. The gates of the NMOS transistors N1 and N2 are connected to the word line WL. A power supply potential VDD is applied to the sources of the PMOS transistors P1 and P2. The drain of the PMOS transistor P1 is connected to the source of the NMOS transistor N1, the drain of the NMOS transistor N3, the gates of the NMOS transistor N4 and the PMOS transistor P2. The drain of the PMOS transistor P2 is connected to the source of the NMOS transistor N2, the drain of the NMOS transistor N4, the gates of the NMOS transistor N3 and the PMOS transistor P1. The sources of the NMOS transistors N3 and N4 are grounded (ground potential VSS).

  The I / O circuit 2 includes a write driver 21, a sense amplifier 22, a normal operation precharge circuit 23, a resume standby return precharge circuit 24, a write column switch 25, a read column switch 26, and a column I / O control circuit 27. Have.

  The write driver 21 performs writing to the bit line BT and the bit line BB. The sense amplifier 22 reads the bit line BT and the bit line BB.

  The normal operation precharge circuit 23 includes PMOS transistors P31 to P33. One end of the PMOS transistor P31 is connected to the bit line BT, and the other end is connected to the bit line BB. The power supply potential VDD is applied to the sources of the PMOS transistors P32 and P33. The drain of the PMOS transistor P32 is connected to the bit line BT. The drain of the PMOS transistor P33 is connected to the bit line BB. A precharge control signal CPC is input from the column I / O control circuit 27 to the gates of the PMOS transistors P31 to P33.

  The resume standby recovery precharge circuit 24 includes PMOS transistors P41 and P42. The power supply potential VDD is applied to the sources of the PMOS transistors P41 and P42. The drain of the PMOS transistor P41 is connected to the bit line BT. The drain of the PMOS transistor P42 is connected to the bit line BB. The resume mode return precharge signal RSPC is input from the operation mode control circuit 3 to the gates of the PMOS transistors P41 and P42.

  The light column switch 25 includes NMOS transistors N51 and N52. One end of the NMOS transistor N51 is connected to the bit line BT, and the other end is connected to the write driver 21. One end of the NMOS transistor N52 is connected to the bit line BB, and the other end is connected to the write driver 21. The write switch control signal CWSE is input from the column I / O control circuit 27 to the gates of the NMOS transistors N51 and N52.

  The read column switch 26 includes PMOS transistors P61 and P62. One end of the PMOS transistor P61 is connected to the bit line BT, and the other end is connected to the sense amplifier 22. One end of the PMOS transistor P62 is connected to the bit line BB, and the other end is connected to the sense amplifier 22. The read switch control signal CRSE is input from the column I / O control circuit 27 to the gates of the PMOS transistors P61 and P62.

  The column I / O control circuit 27 includes a PMOS transistor P71, NAND circuits 271 and 272, and an inverter 273. The power supply potential VDD is applied to the source of the PMOS transistor P71. An inversion operation mode switching signal RSI is input to the gate of the PMOS transistor P71. A precharge signal PC is input to one input terminal of the NAND circuit 271, and an output terminal is connected to the gates of the PMOS transistors P31 to P33 of the normal operation precharge circuit 23 to output a precharge control signal CPC. The NAND circuit 272 receives the Y selection signal Y0 at one input terminal and the sense enable signal SE from the sense amplifier 22 at the other input terminal. The output terminal of the inverter 273 is connected to the gates of the NMOS transistors N51 and N52 of the light column switch 25, and outputs a light switch control signal CWSE. The drain of the PMOS transistor P71, the gates of the PMOS transistors P61 and P62 of the read column switch 26, the other input terminal of the NAND circuit 271, the output terminal of the NAND circuit 272, and the input terminal of the inverter 273 are connected to each other. .

  The operation mode control circuit 3 includes an inverter 31, a delay circuit 32, an AND circuit 33, an inverter 34 and a NAND circuit 35. An operation mode switching signal RS is input to the input terminal of the inverter 31, and an inverted operation mode switching signal RSI, which is an inverted signal of the operation mode switching signal RS, is output from the output terminal. The input terminal of the delay circuit 32 is connected to the output terminal of the inverter 31 and receives the inverting operation mode switching signal RSI. From the output terminal of the delay circuit 32, a delayed inversion operation mode switching signal RSI_D obtained by delaying the inversion operation mode switching signal RSI is output. One input terminal of the AND circuit 33 is connected to the output terminal of the inverter 31 and receives the inverted operation mode switching signal RSI. The other input terminal of the AND circuit 33 is connected to the output terminal of the delay circuit 32, and the delay inversion operation mode switching signal RSI_D is input thereto. A precharge signal PC is output from the output terminal of the AND circuit 33. The input terminal of the inverter 34 is connected to the output terminal of the delay circuit 32, the delayed inversion operation mode switching signal RSI_D is input, and the output terminal is connected to one input terminal of the NAND circuit 35. The other input terminal of the NAND circuit 35 is connected to the output terminal of the inverter 31 and receives the inverted operation mode switching signal RSI. The output terminal of the NAND circuit 35 is connected to the gates of the PMOS transistors P41 and P42 of the resume standby return precharge circuit 24, and outputs a resume mode return precharge signal RSPC. The inversion operation mode switching signal RSI is output to the gate of the PMOS transistor P71 of the column I / O control circuit 27.

  The delay circuit 32 can be configured as described below, for example. FIG. 3 is a diagram illustrating a configuration example of the delay circuit 32. The delay circuit 32 includes a buffer 321, an inverter 322, and an inverter 323.

  Inverter 322 is arranged at a position where it can be supplied with inverting operation mode switching signal RSI that has passed through a memory cell provided in semiconductor memory device 100. At this position, the inverting operation mode switching signal RSI is input to the input terminal of the inverter 322.

  The buffer 321 is arranged in the vicinity of each of the plurality of I / O circuits 2 corresponding to the plurality of memory cells 1 provided in the semiconductor memory device 100. The plurality of buffers 321 are cascade-connected. The input terminals of the plurality of buffers 321 connected in cascade are connected to the output terminal of the inverter 322. Output terminals of the plurality of subordinately connected buffers 321 are connected to an input terminal of the inverter 323. A delayed inversion operation mode switching signal RSI_D is output from the output terminal of the inverter 323.

  An operation of the semiconductor memory device 100 will be described. FIG. 4 is a timing diagram of signals in the semiconductor memory device 100 according to the first embodiment. Here, the operation in the NOP (non-operation) state in the normal operation mode will be described first. At this time, the word line WL is at the LOW level, the Y selection signals Y0 and Y1 are both at the LOW level, and the operation mode switching signal RS is at the LOW level.

  Since the Y selection signals Y0 and Y1 are both at the LOW level, the reed switch control signal CRSE is at the HIGH level. Therefore, the read column switch 26 is turned off, and the sense amplifier 22 is electrically disconnected from the bit line BT and the bit line BB.

  Since the read switch control signal CRSE is at a high level, the write switch control signal CWSE is at a LOW level. Accordingly, the write column switch 25 is turned off, and the write driver 21 is electrically disconnected from the bit line BT and the bit line BB.

  Since the operation mode switching signal RS is at the LOW level, the inversion operation mode switching signal RSI is at the HIGH level, and the delay inversion operation mode switching signal RSI_D is at the HIGH level. Therefore, the resume mode return precharge signal RSPC becomes HIGH level, and the resume standby return precharge circuit 24 is turned off.

  Since the inversion operation mode switching signal RSI is at the HIGH level and the delay inversion operation mode switching signal RSI_D is at the HIGH level, the precharge signal PC is at the HIGH level. Since the reed switch control signal CRSE is also at a high level, the precharge control signal CPC is at a LOW level. Accordingly, the normal operation precharge circuit 23 is turned on, and the bit line BT and the bit line BB are precharged to HIGH level.

  As described above, in the NOP state in the normal operation mode, the bit line BT and the bit line BB are held at the HIGH level by the normal operation precharge circuit 23. At this time, since the sources of the NMOS transistors N3 and N4 of the memory cell 1 are grounded (ground potential VSS), a load (PMOS transistors P1 and P2), a drive transistor (NMOS transistors N3 and N4), a transfer transistor ( A leak current flows from the power supply to the ground due to the channel leak of the NMOS transistors N1 and N2). Further, due to the transfer transistor GIDL, a leak current flows from the bit line (power supply) to the transfer transistor substrate (ground).

  Next, the operation when transitioning from the normal operation mode to the resume standby mode (timing T1 in FIG. 4) will be described. At this time, the word line WL remains at the LOW level, but the operation mode switching signal RS changes from the LOW level to the HIGH level. In the resume standby mode, the power of the address decoder (not shown) is cut off, so that the Y selection signals Y0 and Y1 are undefined.

  The inversion operation mode switching signal RSI transits from HIGH level to LOW level. The Y selection signals Y0 and Y1 are indefinite, but the PMOS transistor P71 is turned on, so that the reed switch control signal CRSE is driven to the HIGH level. Accordingly, the read column switch 26 is turned off, and the sense amplifier 22 is electrically disconnected from the bit line BT and the bit line BB.

  Since the read switch control signal CRSE is at a high level, the write switch control signal CWSE is at a LOW level. Therefore, the light column switch 25 is turned off, and the write driver 21 is electrically separated from the bit line BT and the bit line BB.

  Even when the inversion operation mode switching signal RSI changes from HIGH level to LOW level, the resume mode return precharge signal RSPC remains at HIGH level, and the resume standby return precharge circuit 24 is OFF.

  When the inversion operation mode switching signal RSI changes from HIGH level to LOW level, the precharge signal PC becomes LOW level. Accordingly, the precharge control signal CPC becomes HIGH level, and the normal operation precharge circuit is turned off.

  Since the word line WL is at the LOW level, the transfer transistor is off.

  As described above, in the resume standby mode, the bit line BT and the bit line BB are electrically disconnected from other circuits of the semiconductor memory device 100 and are in a floating state. For this reason, the potentials of the bit line BT and the bit line BB are naturally determined so as to minimize the leakage current of the memory cell 1 and other circuits. Therefore, the leakage current from the bit line by GIDL to the transfer transistor substrate can be reduced.

  Even if the inversion operation mode switching signal RSI changes from HIGH level to LOW level, the delay inversion operation mode switching signal RSI_D does not immediately change from HIGH level to LOW level. That is, the delayed inversion operation mode switching signal RSI_D changes from the HIGH level to the LOW level after a certain delay time has elapsed since the inversion operation mode switching signal RSI has changed from the HIGH level to the LOW level.

  As described above, in the resume standby mode, since the bit line BT and the bit line BB are in a floating state, leakage current from the bit line to the transfer transistor substrate due to GIDL can be reduced.

  Next, the operation when returning from the resume standby mode to the normal operation mode (timing T2 in FIG. 4) will be described. At this time, the word line WL remains at the LOW level, but the operation mode switching signal RS changes from the HIGH level to the LOW level. Although not shown, the address decoder is also powered off. Therefore, the Y selection signals Y0 and Y1 are indefinite. After a certain time when the power supply is restored, the Y selection signals Y0 and Y1 become LOW level.

  The inversion operation mode switching signal RSI changes from the LOW level to the HIGH level. The Y selection signals Y0 and Y1 are initially indefinite, but transition to the LOW level after a certain time, so that the reed switch control signal CRSE is driven to the HIGH level. Accordingly, the read column switch 26 is turned off, and the sense amplifier 22 is electrically disconnected from the bit line BT and the bit line BB.

  Since the read switch control signal CRSE is at a high level, the write switch control signal CWSE is at a LOW level. Accordingly, the write column switch 25 is turned off, and the write driver 21 is electrically disconnected from the bit line BT and the bit line BB.

  Even if the inversion operation mode switching signal RSI changes from the LOW level to the HIGH level, the delay inversion operation mode switching signal RSI_D does not immediately change from the LOW level to the HIGH level.

  When the inversion operation mode switching signal RSI becomes HIGH level, the resume mode return precharge signal RSPC becomes LOW level. Therefore, the resume standby recovery precharge circuit is turned on, and the bit line BT and the bit line BB are precharged to HIGH level.

  Since the delayed inversion operation mode switching signal RSI_D does not immediately shift from the LOW level to the HIGH level, the precharge signal PC is maintained at the LOW level even when the inversion operation mode switching signal RSI becomes the HIGH level. Therefore, the precharge control signal CPC is maintained HIGH, and the normal operation precharge circuit is also maintained off. Therefore, the normal operation precharge circuit does not perform precharge while the resume standby recovery precharge circuit 24 is performing the recovery precharge of the bit line BT and the bit line BB.

  The delay inversion operation mode switching signal RSI_D changes from the LOW level to the HIGH level after a lapse of a certain time after the inversion operation mode switching signal RSI changes from the LOW level to the HIGH level (timing T3 in FIG. 4). As a result, the resume mode return precharge signal RSPC transits to the HIGH level, so that the resume standby return precharge circuit 24 is turned off.

  On the other hand, the precharge signal PC transits to a HIGH level. Since the reed switch control signal CRSE is at a high level, the precharge control signal CPC transitions to a LOW level and the normal operation precharge circuit is turned on. Thereby, the semiconductor memory device 100 returns to the normal operation mode.

  As described above, when returning from the resume standby mode to the normal operation mode, the bit line BT and the bit line BB are charged to the HIGH level by the resume standby return precharge circuit 24 for a certain period after the return. After a predetermined period of time, the main body that precharges the bit lines BT and BT is switched from the resume standby return precharge circuit 24 to the normal operation precharge circuit 23, and the return to the normal operation mode is completed.

  As described above, when returning from the resume standby mode to the normal operation mode, both the bit line BT and the bit line BB of the semiconductor memory device 100 must be precharged. The current when performing is increased. For this reason, since a large number of bit lines are provided in the semiconductor memory device 100, if precharging is performed by the normal operation precharge circuit 23, the peak current required for precharging when returning from the resume standby mode to the normal operation mode is performed. Becomes larger.

  On the other hand, the semiconductor memory device 100 is designed such that the driving power of the resume standby recovery precharge circuit 24 is smaller than the driving power of the normal operation precharge circuit 23. Thereby, the peak current at the time of performing the precharge at the time of returning from the resume standby mode to the normal operation mode can be suppressed.

  Therefore, according to this configuration, compared to the case where the precharge circuit for returning from the resume standby mode to the normal operation mode is used, a reliability failure such as a drop in power supply potential or electromigration occurs. Can be prevented.

  Further, in this configuration, as described above, the bit line is floated in the resume standby mode. As a result, leakage current due to GIDL flowing from the bit line to the transfer transistor substrate can be reduced.

Embodiment 2
A semiconductor memory device 200 according to the second embodiment will be described. FIG. 5 is a circuit diagram schematically showing a configuration of the semiconductor memory device 200 according to the second embodiment. As shown in FIG. 5, the semiconductor memory device 200 includes a memory cell 1, an I / O circuit 4, and an operation mode control circuit 5.

  The I / O circuit 4 removes the resume standby return precharge circuit 24 from the I / O circuit 2 described in the first embodiment, and also replaces the normal operation precharge circuit 23 and the column I / O control circuit 27 with each other. These are replaced with the normal operation precharge circuit 43 and the column I / O control circuit 47, respectively. Since the other configuration of the I / O circuit 4 is the same as that of the I / O circuit 2, the description thereof is omitted.

  The normal operation precharge circuit 43 has a configuration in which the connection destination of the sources of the PMOS transistors P31 and P32 in the normal operation precharge circuit 23 is changed to the precharge power supply line PSL.

  The column I / O control circuit 47 has a configuration in which the NAND circuit 271 is removed from the column I / O control circuit 27 and an inverter 471 is added. The input terminal of the inverter 471, the drain of the PMOS transistor P71, the gates of the PMOS transistors P61 and P62 of the read column switch 26, the output terminal of the NAND circuit 272, and the input terminal of the inverter 273 are connected to each other. The output terminal of the inverter 471 is connected to the gates of the PMOS transistors P31 to P33 of the normal operation precharge circuit 23, and outputs a precharge control signal CPC. The other configuration of the column I / O control circuit 47 is the same as that of the column I / O control circuit 27, and thus the description thereof is omitted.

  The operation mode control circuit 5 includes an inverter 31, a delay circuit 32, an OR circuit 51, an NMOS transistor N5, and a PMOS transistor P5.

  The inverter 31 and the delay circuit 32 are the same as those in the operation mode control circuit 3 described in the first embodiment.

  The power supply potential VDD is applied to the drain and gate of the NMOS transistor N5. The source of the NMOS transistor N5 is connected to the precharge power supply line PSL. A power supply potential VDD is applied to the source of the PMOS transistor P5. The drain of the PMOS transistor P5 is connected to the precharge power supply line PSL.

  One input terminal of the OR circuit 51 is connected to the output terminal of the inverter 31 and receives the inverted operation mode switching signal RSI. The other input terminal of the OR circuit 51 is connected to the output terminal of the delay circuit 32, and the delay inversion operation mode switching signal RSI_D is input thereto. The output terminal of the OR circuit 51 is connected to the gate of the PMOS transistor P5.

  The operation of the semiconductor memory device 200 will be described. Signal timings in the semiconductor memory device 200 are the same as those in FIG.

  In the NOP state in the normal operation mode, the PMOS transistor P5 and the NMOS transistor N5 are turned on, and the power supply potential VDD is applied to the precharge power supply line PSL.

  On the other hand, in the resume standby mode (timing T1 in FIG. 4), the PMOS transistor P5 is turned off and the NMOS transistor N5 is turned on. Therefore, a potential that is lower than the power supply potential VDD by the Vth (threshold value) of the NMOS transistor N5 is applied to the precharge power supply line PSL. At this time, since the precharge control signal CPC is at the HIGH level, the normal operation precharge circuit 43 is off, and the bit line BT and the bit line BB are in a floating state.

  When returning from the resume standby mode to the normal operation mode (timing T2 in FIG. 4), the PMOS transistor P5 is off and the NMOS transistor N5 is on for a certain period. On the other hand, since the precharge control signal CPC becomes LOW level, the bit line BT and the bit line BB are precharged. At this time, a potential that is lower than the power supply potential VDD by the Vth (threshold value) of the NMOS transistor N5 is continuously applied to the precharge power supply line PSL. Therefore, the bit line is precharged slowly, and the peak current during precharge can be reduced as in the semiconductor memory device 100.

  As described above, according to this configuration, when the bit line is charged when returning from the resume standby mode to the normal operation mode, the power supply potential applied to the charging transistor of the normal operation precharge circuit 43 is lowered, Reduce driving ability. Thereby, like the semiconductor memory device 100, the magnitude of the peak current at the time of recovery can be suppressed.

  Therefore, according to this configuration, it can be understood that the same operational effects as the semiconductor memory device 100 according to the first embodiment can be obtained.

Embodiment 3
A semiconductor memory device 300 according to the third embodiment will be described. FIG. 6 is a block diagram schematically showing a configuration of the semiconductor memory device 300 according to the third embodiment. As shown in FIG. 6, the semiconductor memory device 300 has a configuration in which a word line driver 6 is added to the semiconductor memory device 100.

  FIG. 7 is a circuit diagram showing the word line driver 6 and the memory cell 1 according to the third embodiment. The word line driver 6 includes a control signal generation circuit 61, a driver circuit 62, a resume standby word line holding circuit 63, a return word line power switch 64, and a word line power switch 65.

  The control signal generation circuit 61 includes inverters 611 to 613, a NOR circuit 614, and a NAND circuit 615. The inverted operation mode switching signal RSI is input from the operation mode control circuit 3 to the input terminal of the inverter 611. A return word line power switch control signal LCM is output from the output terminal of the inverter 611. One input terminal of the NOR circuit 614 receives the inverted operation mode switching signal RSI from the operation mode control circuit 3. The other input terminal of the NOR circuit 614 receives the delayed inversion operation mode switching signal RSI_D from the operation mode control circuit 3. The output terminal of the NOR circuit 614 is connected to the input terminal of the inverter 612 and one input terminal of the NAND circuit 615. A word line power switch control signal LCMW is output from the output terminal of the inverter 612. The input terminal of the inverter 613 is connected to the output terminal of the inverter 612, and receives the word line power switch control signal LCMW. An inverted word line power switch control signal LCMWI is output from the output terminal of the inverter 612 to the other input terminal of the NAND circuit 615. From the output terminal of the NAND circuit 615, a resume standby word line holding control signal LCMWD is output.

  The return word line power switch 64 includes a PMOS transistor P6. A power supply potential VDD is applied to the source of the PMOS transistor P6. The drain of the PMOS transistor P6 is connected to the word line driver power supply line LCVDD. A return word line power switch control signal LCM is input to the gate of the PMOS transistor P6.

  The word line power switch 65 includes a PMOS transistor P7. The power supply potential VDD is applied to the source of the PMOS transistor P7. The drain of the PMOS transistor P7 is connected to the word line driver power supply line LCVDD. The gate of the PMOS transistor P7 is connected to the output terminal of the inverter 612, and receives the word line power switch control signal LCMW.

  The driver circuit 62 includes a PMOS transistor P11 and an NMOS transistor N11. The PMOS transistor P11 and the NMOS transistor N11 constitute an inverter circuit. The source of the PMOS transistor P11 is connected to the drain of the PMOS transistor P6 of the return word line power switch 64 and the drain of the PMOS transistor P7 of the word line power switch 65 (that is, the word line driver power line LCVDD). The drain of the PMOS transistor P11 is connected to the drain of the NMOS transistor N11 and the word line WL. The source of the NMOS transistor N11 is grounded (ground potential VSS). A word line selection signal WLS is input to the gates of the PMOS transistor P11 and the NMOS transistor N11.

  The resume standby word line holding circuit 63 has an NMOS transistor N6. The drain of the NMOS transistor N6 is connected to the word line WL between the driver circuit 62 and the memory cell 1. The source of the NMOS transistor N6 is grounded (ground potential VSS). The gate of the NMOS transistor N6 is connected to the output terminal of the NAND circuit 615, and the resume standby word line holding control signal LCMWD is input thereto.

  The operation of the semiconductor memory device 400 will be described. FIG. 8 is a timing diagram of signals in the semiconductor memory device 300 according to the third embodiment. First, the operation in the NOP state in the normal operation mode will be described. In the NOP state in the normal operation mode, the operation mode switching signal RS is at the LOW level.

  At this time, since the delayed inversion operation mode switching signal RSI_D is at the HIGH level, the word line power switch control signal LCMW is at the LOW level. Accordingly, the word line power switch 65 is turned on, and the word line driver power line LCVDD is driven to the HIGH level.

  At this time, the inversion operation mode switching signal RSI becomes HIGH level. Therefore, the return word line power switch control signal LCM is at the LOW level, the return word line power switch 64 is turned on, and the word line driver power supply line LCVDD is driven to the HIGH level.

  Since the word line power switch control signal LCMW is at the LOW level, the inverted word line power switch control signal LCMWI is at the HIGH level. Therefore, the resume standby word line holding control signal LCMWD becomes LOW level, and the resume standby word line holding circuit is turned off.

  As described above, in the normal operation mode, the word line driver power supply line LCVDD is driven to the HIGH level by both the word line power supply switch 65 and the return word line power supply switch 64.

  Next, the operation when transitioning from the normal operation mode to the resume standby mode (timing T1 in FIG. 8) will be described. At this time, the operation mode switching signal RS changes from the LOW level to the HIGH level.

  Since the operation mode switching signal RS becomes HIGH level, the word line power switch control signal LCMW becomes HIGH level, and the word line power switch 65 is turned off.

  Since the inversion operation mode switching signal RSI becomes LOW level, the return word line power switch control signal LCM becomes HIGH level, and the return word line power switch 64 is turned off.

  Since the word line power switch control signal LCMW goes high, the inverted word line power switch control signal LCMWI goes low. Therefore, the resume standby word line holding control signal LCMWD becomes HIGH level, the resume standby word line holding circuit 63 is turned on, and all the word lines WL are held at LOW level.

  As described above, in the resume standby mode, the word line driver power supply line LCVDD becomes floating, and the leakage current in the driver circuit 62 can be reduced. Further, instead of the driver circuit, the resume standby word line holding circuit 63 holds the word line WL at the LOW level.

  Next, the operation when returning from the resume standby mode to the normal operation mode (timing T2 in FIG. 8) will be described. At this time, the operation mode switching signal RS changes from HIGH level to LOW level.

  Even when the operation mode switching signal RS transits to the LOW level, the delayed inversion operation mode switching signal RSI_D does not immediately transit from the LOW level to the HIGH level. Since the word line power switch control signal LCMW does not immediately shift to the LOW level, the word line power switch 65 remains off.

  On the other hand, since the inversion operation mode switching signal RSI becomes HIGH level, the return word line power switch control signal LCM immediately becomes LOW, the return word line power switch 64 is turned on, and the word line driver power supply line LCVDD becomes HIGH. Charged to level.

  After the inversion operation mode switching signal RSI transitions from the LOW level to the HIGH level, the delay inversion operation mode switching signal RSI_D transitions from the LOW level to the HIGH level after a certain time (timing T3 in FIG. 8).

  As a result, the word line power switch control signal LCMW also transitions to the LOW level, so that the word line power switch 65 is turned on and the word line driver power line LCVDD is driven to the HIGH level.

  As described above, when returning from the resume standby mode to the normal operation mode, the word line driver power supply line LCVDD is charged to the HIGH level by the return word line power switch 64 for a certain period after the return. Thereafter, the word line power switch 65 is turned on, and the return to the normal operation mode is completed. The driving power of the return word line power switch 64 is designed to be sufficiently smaller than the word line power switch 65 so that the peak current when charging the word line driver power line LCVDD does not increase. Therefore, the word line driver power supply line LCVDD can be charged more slowly than when charging using the word line power switch 65. As a result, there is no problem that an instantaneous voltage drop or poor reliability is caused by an increase in peak current during charging.

Embodiment 4
A semiconductor memory device 400 according to the first embodiment will be described. FIG. 9 is a circuit diagram schematically showing a configuration of the semiconductor memory device 400 according to the fourth embodiment. As shown in FIG. 9, the semiconductor memory device 400 has a configuration in which a source level control circuit 7 is added to the semiconductor memory device 100.

  The source level control circuit 7 includes NMOS transistors N15 and N16. The drain and gate of the NMOS transistor N15 are connected to the source line ARVSS. The drain of the NMOS transistor N16 is connected to the source line ARVSS. An inverted operation mode switching signal RSI output from the operation mode control circuit 3 is input to the gate of the NMOS transistor N16. The sources of the NMOS transistors N15 and N16 are grounded (ground potential VSS).

  The operation of the semiconductor memory device 400 will be described. FIG. 10 is a timing diagram of signals in the semiconductor memory device 400 according to the fourth embodiment. Since the operation other than the source level control circuit 7 is the same as that of the semiconductor memory device 100, description thereof is omitted. Hereinafter, the operation of the source level control circuit 7 will be described.

  In the normal operation mode, the inversion operation mode switching signal RSI is at a HIGH level. Therefore, the source line ARVSS is driven to the LOW level by the source level control circuit 7.

  When the normal operation mode is changed to the resume standby mode (timing T1 in FIG. 10), the inverted operation mode switching signal RSI is changed from the HIGH level to the LOW level. Since the inverting operation mode switching signal RSI is at the LOW level, the NMOS transistor N16 of the source level control circuit 7 is turned off, and the source line ARVSS is driven by the diode-connected NMOS transistor N15. Therefore, the potential of the source line ARVSS is determined by the ratio between the leakage current of the memory cell 1 and the on-current of the diode-connected NMOS transistor N15. Thereby, the potential of the source line ARVSS rises to a level higher than the ground potential VSS, so that the leakage current of the memory cell can be reduced.

  As described above, according to this configuration, similarly to the semiconductor memory device 100, in the resume standby mode, the bit line BT and the bit line BB are in a floating state, and therefore leakage from the bit line to the transfer transistor substrate due to GIDL. Current can be reduced.

  Further, according to this configuration, the source line ARVSS is raised from the ground potential VSS level by the source level control circuit 7 in the resume standby mode. Thereby, leakage current due to channel leakage can also be reduced. Therefore, according to this configuration, it is possible to further reduce the leakage current.

Other Embodiments The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit of the present invention. For example, the I / O circuit 2 and the operation mode control circuit 3 of the semiconductor memory device according to the third and fourth embodiments may be replaced with the I / O circuit 4 and the operation mode control circuit 5 described in the second embodiment, respectively. Is possible.

  Further, both the word line driver 6 and the source level control circuit 7 may be provided in the semiconductor memory device according to the above-described embodiment.

  The transistors described in the above embodiments are merely examples. Needless to say, various changes can be made, such as switching other transistors or conductivity types, as long as the same operation can be realized.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Memory cell 2, 4 I / O circuit 3, 5 Operation mode control circuit 6 Word line driver 7 Source level control circuit 21 Write driver 22 Sense amplifier 23, 43 Normal operation precharge circuit 24 Resume standby return precharge circuit 25 Write column switch 26 Read column switch 27, 47 Column I / O control circuit 31, 34, 62, 273, 322, 323, 471, 611-613 Inverter 32 Delay circuit 33 AND circuit 35, 271, 272, 615 NAND circuit 51 OR circuit 61 Control signal generation circuit 62 Driver circuit 63 Resume standby word line holding circuit 64 Return word line power switch 65 Word line power switch 100, 200, 300, 400 Semiconductor memory device 321 Buffer 614 NOR circuit ARVS S source line BB bit line BT bit line CPC precharge control signal CRSE read switch control signal CWSE write switch control signal LCM recovery word line power switch control signal LCMW word line power switch control signal LCMWD resume standby word line holding control signal LCMWI inversion Word line power switch control signal LCVDD Word line driver power supply lines N1 to N6, N11, N15, N16, N51, N52 NMOS transistors P1 to P7, P11, P31 to 33, P41, P42, P61, P62, P71 PMOS transistor PC Pre Charge signal PSL Precharge power supply line RS Operation mode switching signal RSI Inversion operation mode switching signal RSI_D Delayed inversion operation mode switching signal RSPC Resume mode return precharge signal VDD Power supply potential VSS Ground potential WL Word line WLS Word line selection signal Y0, Y1 Y selection signal

Claims (5)

A power line;
Multiple word lines,
Multiple bit line pairs;
A plurality of memory cells each connected to one word line of the plurality of word lines and one bit line pair of the plurality of bit line pairs;
A plurality of input / output circuits connected to each of the plurality of bit line pairs, each including a first precharge circuit and a second precharge circuit;
A delay circuit that receives the first control signal and outputs the second control signal,
The first precharge circuit includes:
A source / drain path is provided between the power supply line and one of the bit line pairs connected to the first precharge circuit, and the first control signal is input to the gate electrode. A PMOS transistor;
A source / drain path is provided between the power supply line and the other bit line of the bit line pair connected to the first precharge circuit, and the first control signal is input to the gate electrode. Two PMOS transistors,
The second precharge circuit includes:
A source / drain path is provided between the power supply line and one of the bit line pairs connected to the second precharge circuit, and the second control signal is input to the gate electrode. 3 PMOS transistors;
A source / drain path is provided between the power supply line and the other bit line of the bit line pair connected to the second precharge circuit, and the second control signal is input to the gate electrode. 4 PMOS transistors,
The first precharge circuit connects the power supply line and a bit line pair connected to the first precharge circuit in response to the first control signal.
The second pre-charge circuit in response to the second control signal, to connect said power supply line, and a bit line pair connected to said second precharge circuit,
The delay circuit includes a plurality of cascaded buffers,
Each of the plurality of buffers is disposed in the vicinity of each of the plurality of input / output circuits.
Semiconductor device. Each of the plurality of memory cells has a flip-flop circuit,
The flip-flop circuit is
A first storage node;
A second storage node;
A first CMOS inverter having an output connected to the first storage node and an input connected to the second storage node;
A second CMOS inverter having an output connected to the second storage node and an input connected to the first storage node;
A first transfer NMOS transistor having a source / drain path between the first storage node and one of the bit line pairs connected to the memory cell;
A second transfer NMOS transistor connected to have a source / drain path between the second storage node and the other bit line of the bit line pair connected to the memory cell;
The first CMOS inverter includes a first load PMOS transistor and a first driving NMOS transistor,
The second CMOS inverter includes a second load PMOS transistor and a second driving NMOS transistor,
The first transfer NMOS transistor and the second transfer NMOS transistor have a gate electrode connected to a word line connected to the memory cell.
The semiconductor device according to claim 1. Each of the plurality of input / output circuits is
A write driver connected to a pair of bit lines connected to the input / output circuit;
A sense amplifier connected to the pair of bit lines connected to the input / output circuit;
The semiconductor device according to claim 2 . The write driver is connected to a bit line pair connected to the write driver via a first switch,
The sense amplifier is connected to a bit line pair connected to the sense amplifier via a second switch.
The semiconductor device according to claim 3 . The driving power of the second precharge circuit is greater than the driving power of the first precharge circuit,
The semiconductor device according to claim 3 .

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