CN114122148A - Thin film transistor, manufacturing method thereof, array substrate, display panel and device - Google Patents

Thin film transistor, manufacturing method thereof, array substrate, display panel and device Download PDF

Info

Publication number
CN114122148A
CN114122148A CN202111429653.8A CN202111429653A CN114122148A CN 114122148 A CN114122148 A CN 114122148A CN 202111429653 A CN202111429653 A CN 202111429653A CN 114122148 A CN114122148 A CN 114122148A
Authority
CN
China
Prior art keywords
layer
active layer
forming
substrate
active
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111429653.8A
Other languages
Chinese (zh)
Inventor
卢昱行
刘凤娟
童彬彬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202111429653.8A priority Critical patent/CN114122148A/en
Publication of CN114122148A publication Critical patent/CN114122148A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The invention discloses a thin film transistor and a manufacturing method thereof, an array substrate, a display panel and a device, wherein the thin film transistor comprises: a substrate; a first active layer on one side of the substrate and having a first middle region and first edge portions, the first middle portion being between the first edge portions; a second active layer at least on a surface of the first intermediate portion; a first protective layer covering at least a first edge portion of the first active layer; the source and drain electrodes are positioned on one side of the second active layer, which is far away from the substrate, and are connected with the second active layer; the gate layer is positioned on one side of the second active layer far away from the substrate or on the surface of the substrate close to the first active layer; wherein the materials of the first active layer and the second active layer are different. The thin film transistor can have better uniformity when the first active layer and the second active layer are made of materials with any etching selection ratio, and a hump phenomenon can not occur, so that the thin film transistor has good stability.

Description

Thin film transistor, manufacturing method thereof, array substrate, display panel and device
Technical Field
The disclosure relates to the technical field of display, in particular to a thin film transistor, a manufacturing method thereof, an array substrate, a display panel and a device.
Background
At present, thin film transistor devices with two active layers are an important development direction in the display technology field. However, in the manufacturing process of the conventional thin film transistor, when the etching rate of the material used for the lower active layer is much higher than that of the upper active layer, an undercut structure may occur on the lower active layer after etching, and thus the undercut structure may cause the uniformity of the thin film transistor to be poor and a hump phenomenon to occur.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to overcome the defects of the thin film transistor in the prior art that the uniformity is poor and the hump phenomenon occurs, and provides a thin film transistor with good uniformity, a manufacturing method thereof, an array substrate, a display panel and a device.
A first aspect of the present disclosure provides a thin film transistor, including:
a substrate;
a first active layer on one side of the substrate, the first active layer having a first middle portion and first edge portions, the first middle portion being between the first edge portions;
a second active layer at least at a surface of the first intermediate portion;
a first protective layer covering at least a first edge portion of the first active layer;
the source and drain electrodes are positioned on one side of the second active layer, which is far away from the substrate, and are connected with the second active layer;
the gate layer is positioned on one side of the second active layer far away from the substrate or on the surface of the substrate close to the first active layer;
wherein the first active layer and the second active layer are different in material.
In an exemplary embodiment of the present disclosure, the second active layer has a second middle portion and a second edge portion, wherein the second middle portion is located on a surface of the first middle portion, and the second edge portion is located on a surface of the first protection layer away from the first edge portion and a portion of the second middle portion; the thin film transistor further includes:
the first gate insulating layer at least covers the second active layer, and the gate layer is positioned on the surface of the first gate insulating layer far away from the first active layer.
In an exemplary embodiment of the present disclosure, the thin film transistor further includes:
the first interlayer dielectric layer is positioned on the surface, far away from the second active layer, of the first grid insulating layer and covers the grid layer, first through holes are formed in the first interlayer dielectric layer and the first grid insulating layer, and the source electrode and the drain electrode are positioned on the surface, far away from the second active layer, of the first interlayer dielectric layer and are connected with the second active layer through the first through holes.
In one exemplary embodiment of the present disclosure, the material of the first active layer is a crystalline oxide.
In an exemplary embodiment of the present disclosure, the first protective layer and the second active layer are the same material, and the first protective layer and the second active layer are connected to each other; the thin film transistor further includes:
and the second gate insulating layer covers the first protective layer and the second active layer, and the gate layer is positioned on the surface of the second gate insulating layer.
In an exemplary embodiment of the present disclosure, an edge of the first protective layer away from the first edge portion has a first distance therebetween, and the first distance is between 0.4 μm and 1.2 μm.
In an exemplary embodiment of the present disclosure, the thin film transistor further includes:
the second interlayer dielectric layer is positioned on the surface, far away from the second active layer, of the second gate insulating layer and covers the gate layer, second through holes are formed in the second interlayer dielectric layer and the second gate insulating layer, the source and drain electrodes are positioned on the surface of one side, far away from the second active layer, of the second interlayer dielectric layer, and the source and drain electrodes are connected with the first protective layer through the second through holes.
In an exemplary embodiment of the present disclosure, the gate layer is located on a surface of the substrate near the first active layer, and the thin film transistor further includes:
the third gate insulating layer covers the gate, and the first active layer is located on the surface of the third gate insulating layer far away from the substrate.
In an exemplary embodiment of the present disclosure, the second active layer has a third middle portion and a third edge portion, wherein the third middle portion is located on a surface of the first middle portion, the third edge portion is located on a surface of the first protection layer away from the first edge portion and a portion of the surface of the third middle portion, and the source and drain electrodes are located on at least a surface of the third edge portion.
In an exemplary embodiment of the disclosure, the first protection layer and the second active layer are made of the same material, the first protection layer and the second active layer are connected to each other, and the source and drain electrodes are at least located on the surfaces of the first protection layer and a part of the second active layer.
In an exemplary embodiment of the present disclosure, the thin film transistor further includes:
and the second protective layer at least covers the second active layer and the source and drain electrodes.
A second aspect of the present disclosure provides a method for manufacturing a thin film transistor, including:
providing a substrate;
forming a first active layer on one side of the substrate, the first active layer having a first middle portion and first edge portions, the first middle portion being located between the first edge portions;
arranging a first protective layer at a first edge part of the first active layer, enabling the first protective layer to at least cover the first edge part, and forming a second active layer on the surface of the first middle part;
forming a gate layer on the side of the second active layer far away from the substrate after forming the first protection layer, or forming a gate layer on the surface of the substrate near the first active layer before forming the first active layer;
forming a source drain on one side of the second active layer, which is far away from the substrate, and connecting the source drain with the second active layer;
wherein the first active layer and the second active layer are different in material.
In one exemplary embodiment of the present disclosure, after forming the first protective layer, a gate layer is formed on a side of the second active layer away from the substrate; the forming of the first active layer at one side of the substrate includes:
depositing a first active layer on one side of the substrate, and patterning the first active layer;
and annealing the patterned first active layer to crystallize the patterned first active layer.
In an exemplary embodiment of the present disclosure, the temperature of the annealing treatment is greater than or equal to 350 ℃, and the time range of the annealing treatment is: between 0.5 hours and 1.5 hours.
In an exemplary embodiment of the present disclosure, the disposing a first protection layer at a first edge portion of the first active layer, so that the first protection layer covers at least the first edge portion, and forming a second active layer on a surface of the first middle portion includes:
forming the first protective layer covering the first active layer;
etching the first protective layer to expose a first middle portion of the first active layer;
and depositing a second active layer on the surface of the remaining first protection layer far away from the first active layer and the surface of the first middle part, and patterning the second active layer.
In an exemplary embodiment of the disclosure, the forming a gate layer on a side of the second active layer away from the substrate after forming the first protection layer includes:
forming a first gate insulating layer at least covering the second active layer;
and forming a gate layer on one side of the first gate insulating layer, which is far away from the second active layer, and carrying out patterning treatment on the gate layer.
In an exemplary embodiment of the present disclosure, the second active layer may have a second middle portion and a second edge portion, the second edge portion is located on a surface of the first protection layer away from the first edge portion and a portion of a surface of the second middle portion, a source and a drain are formed on a side of the second active layer away from the substrate, and the source and the drain are connected to the second active layer, including:
forming a first interlayer dielectric layer on the surface of the first gate insulating layer far away from the second active layer, and enabling the first interlayer dielectric layer to cover the gate layer;
etching the first interlayer dielectric layer and the first gate insulating layer to form a first through hole and expose the surface of the second edge part;
and depositing a material for forming a source drain electrode on the surface of the first interlayer dielectric layer and in the first through hole, and performing patterning treatment to form the source drain electrode connected with the second edge part.
In one exemplary embodiment of the present disclosure, after forming the first protective layer, a gate layer is formed on a side of the second active layer away from the substrate; the disposing a first protection layer at a first edge portion of the first active layer, so that the first protection layer at least covers the first edge portion, and forming a second active layer on a surface of the first middle portion, includes:
and forming a first protective layer covering the first edge part and a second active layer positioned on the surface of the first middle part by using the same material and the same step, and connecting the first protective layer and the second active layer.
In an exemplary embodiment of the disclosure, the forming a gate layer on a side of the second active layer away from the substrate after forming the first protection layer includes:
forming a second gate insulating layer covering the first protective layer and the second active layer;
and forming a gate layer on the surface of the second insulating gate layer, and patterning the gate layer.
In an exemplary embodiment of the present disclosure, the forming a source drain on a side of the second active layer away from the substrate, and connecting the source drain and the second active layer includes:
forming a second interlayer dielectric layer on the surface, far away from the second active layer, of the second gate insulating layer, and enabling the second interlayer dielectric layer to cover the gate layer;
etching the second interlayer dielectric layer and the second gate insulating layer to form a second through hole and expose the surface of the first protective layer;
and depositing a material for forming a source and a drain on the surface of the second interlayer dielectric layer and in the second through hole, and performing patterning treatment to form the source and the drain connected with the first protective layer.
In one exemplary embodiment of the present disclosure, before forming the first active layer, forming a gate layer on a surface of the substrate adjacent to the first active layer, the forming the first active layer on one side of the substrate, includes:
forming a gate layer on one side of the substrate, and patterning the gate layer;
forming a third gate insulating layer to cover the gate layer after the patterning process;
forming the first active layer on the surface of the third gate insulating layer, which is far away from the substrate, and carrying out patterning treatment on the first active layer;
and annealing the patterned first active layer to crystallize the patterned first active layer.
In an exemplary embodiment of the present disclosure, the disposing a first protection layer at a first edge portion of the first active layer, so that the first protection layer covers at least the first edge portion, and forming a second active layer on a surface of the first middle portion includes:
forming the first protective layer covering the first active layer;
etching the first protective layer to expose a first middle portion of the first active layer;
and depositing a second active layer on the surface of the remaining first protection layer far away from the first active layer and the surface of the first middle part, and patterning the second active layer.
In an exemplary embodiment of the present disclosure, the disposing a first protection layer at a first edge portion of the first active layer, so that the first protection layer covers at least the first edge portion, and forming a second active layer on a surface of the first middle portion includes:
and forming a first protective layer covering the first edge part and a second active layer positioned on the surface of the first middle part by using the same material and the same step, and connecting the first protective layer and the second active layer.
In an exemplary embodiment of the present disclosure, the manufacturing method further includes:
and forming a second protective layer at least covering the second active layer and the source and drain electrodes.
A third aspect of the present disclosure provides an array substrate comprising the thin film transistor of any one of the above.
A fourth aspect of the present disclosure provides a display panel, which includes the array substrate described above.
A fifth aspect of the present disclosure provides a display device including the display panel described above.
The technical scheme provided by the disclosure can achieve the following beneficial effects:
the thin film transistor provided by the present disclosure is provided with a first active layer and a second active layer, and a first protective layer covers at least a first edge portion of the first active layer. Thus, the present disclosure can protect the first edge portion of the first active layer through the first protective layer. Therefore, when the second active layer on the first active layer is etched according to the present disclosure, the first protective layer can prevent the first edge portion of the first active layer from being etched, and thus the integrity of the first active layer and the second active layer structure can be ensured, and the stability of the thin film transistor can be ensured.
Meanwhile, the first protective layer can prevent the first edge of the first active layer from being etched, so that an undercut structure can be avoided when the second active layer is etched even if the etching selection ratio of the material of the first active layer to the material of the second active layer is too small (namely, the etching rate of the first active layer is greater than that of the second active layer).
Therefore, the thin film transistor provided by the disclosure can have better uniformity when the first active layer and the second active layer are made of materials with any etching selection ratio, and a hump phenomenon can not occur, so that the thin film transistor has good stability.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a schematic structural diagram of a thin film transistor according to a first embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a thin film transistor according to a second embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a thin film transistor according to a third embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a thin film transistor according to a fourth embodiment of the present disclosure;
fig. 5 is a schematic flow chart illustrating a method for fabricating a thin film transistor according to an embodiment of the present disclosure;
FIGS. 6 to 11 are schematic views illustrating a flow structure of a method for fabricating a thin film transistor according to a first embodiment of the present disclosure;
FIGS. 12-16 are schematic views illustrating a flow structure of a method for fabricating a thin film transistor according to a second embodiment of the present disclosure;
FIGS. 17-21 are schematic views illustrating a flow structure of a method for fabricating a thin film transistor according to a third embodiment of the present disclosure;
fig. 22 to 25 are schematic flow structure diagrams of a method for manufacturing a thin film transistor according to a fourth embodiment of the disclosure.
Description of reference numerals:
1. a substrate; 2. a first active layer; 3. a second active layer; 4. a first protective layer; 5. a second protective layer; 6. a third protective layer; 7. a fourth protective layer; 8. a fifth protective layer; 9. a first gate insulating layer; 10. a second gate insulating layer; 11. a third gate insulating layer; 12. a gate layer; 13. a first interlayer dielectric layer; 14. a second interlayer dielectric layer; 15. a source and a drain; 16. a first buffer layer; 17. a second buffer layer; 18. a first through hole; 19. a second through hole; 21. a first intermediate portion; 22. a first edge portion; 31. a second intermediate portion; 32. a second edge portion; 33. a third intermediate portion; 34. a third edge portion.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.
The related art stacked channel thin film transistor (i.e., a thin film transistor having two stacked active layers) covers the first active layer only with the second active layer, and the first active layer and the second active layer are simultaneously pattern-etched.
However, the inventors of the present disclosure have found that when the structure of the related art thin film transistor is employed and the etch rate of the material employed for the lower active layer is much greater than that of the upper active layer, the lower active layer may be caused to exhibit an undercut structure after etching. The damage to the surface of the undercut structure can be very severe, so that the concentration of oxygen vacancies in the undercut structure is high, and the oxygen lost in the undercut structure is difficult to supplement in the subsequent manufacturing process. Thus, the undercut structure may eventually cause a deterioration in uniformity of the thin film transistor, and a hump phenomenon occurs, thereby causing a deterioration in stability of the thin film transistor. That is to say, the structure of the existing thin film transistor cannot enable the thin film transistor to have better stability when the first active layer and the second active layer are made of materials with any etching selection ratio.
Therefore, the inventors of the present disclosure have made earnest thought and extensive creative efforts to solve the above-mentioned technical problems he found, and finally invented a new thin film transistor. The thin film transistor can have better uniformity when the two active layers are made of materials with any etching selection ratio, and a hump phenomenon can not occur, so that the thin film transistor has good stability when the two active layers are made of any materials.
Note that the materials of the two active layers of the stacked channel thin film transistor are different. Therefore, when the two active layers provided by the present disclosure can be selected from any materials, it is necessary to ensure that the materials of the two active layers are different.
A first aspect of the present disclosure provides a thin film transistor, as shown in fig. 1 to 4, which may include: the semiconductor device comprises a substrate 1, a first active layer 2, a second active layer 3, a first protective layer 4, a source drain 15 and a gate layer 12.
Specifically, the material of the substrate 1 may be glass, but is not limited thereto, and the substrate 1 may also have other materials, such as: one of polyolefin, polyether ketone, polyimide, polyethylene terephthalate, polyacrylate, silicone, polyethylene, glass resin, polycarbonate, fluoropolymer, or copolymers, mixtures, laminates of the above materials, and the like, are within the scope of the present disclosure and may be selected according to actual needs.
The first active layer 2 may be positioned at one side of the substrate 1, and the first active layer 2 may have a first middle portion 21 and a first edge portion 22. Wherein the first intermediate portion 21 is located between the first edge portions 22. The second active layer 3 may be located at least at the surface of the first intermediate portion 21, and the material of the second active layer 3 and the material of the first active layer 2 are different. The first protective layer 4 may cover at least the first edge portion 22 of the first active layer 2. The source-drain electrode 15 may be located on a side of the second active layer 3 away from the substrate 1, and the source-drain electrode 15 may be connected to the second active layer 3. The gate layer 12 may be located on a side of the second active layer 3 away from the substrate 1, or on a surface of the substrate 1 close to the first active layer 2.
Since the first protective layer 4 of the present disclosure may cover at least the first edge portion 22 of the first active layer 2, the present disclosure can protect the first edge portion 22 of the first active layer 2 by the first protective layer 4. Therefore, when the present disclosure etches the second active layer 3 on the first active layer 2, the first protective layer 4 can prevent the first edge portion 22 of the first active layer 2 from being etched, and thus the structural integrity of the first active layer 2 and the second active layer 3 can be ensured, and the stability of the thin film transistor can be ensured.
Meanwhile, since the first protective layer 4 can prevent the first edge portion 22 of the first active layer 2 from being etched, even if the etching selection ratio of the material of the first active layer 2 to the material of the second active layer 3 is too small (i.e., the etching of the first active layer 2 is of a rate greater than that of the second active layer), the first edge portion 22 of the first active layer 2 can be prevented from having an undercut structure when the second active layer 3 is etched.
Therefore, the thin film transistor provided by the present disclosure can have better uniformity when the first active layer 2 and the second active layer 3 are made of materials with any etching selection ratio, and no hump phenomenon occurs, so that the thin film transistor has good stability.
In a first embodiment of the present disclosure, as shown in fig. 1 and 6 to 11, the second active layer 3 may have a second middle portion 31 and a second edge portion 32. Where second intermediate portion 31 may be located on a surface of first intermediate portion 21, it will be appreciated that second intermediate portion 31 may be the same size as first intermediate portion 21 such that second intermediate portion 31 completely covers first intermediate portion 21. Without limitation, it is within the scope of the present disclosure that second intermediate portion 31 may also be smaller than the size of first intermediate portion 21. When the size of the second middle portion 31 is smaller than that of the first middle portion 21, the first protection layer 4 may also cover a part of the first middle portion 21, so that the first protection layer 4 contacts the second active layer 3, thereby preventing the first active layer 2 from being affected when the second active layer 3 is etched, and causing the performance of the thin film transistor to be damaged.
In addition, the second edge portion 32 of the second active layer 3 may be located on a surface of the first protective layer 4 away from the first edge portion 22 and a surface of a portion of the second middle portion 31 for connecting the source and drain electrodes 15.
In the present embodiment, the thickness of the second middle portion 31 is the same as that of the second edge portion 32, so that the second active layer 3 has good performance. That is, therefore, since the thickness of the second middle portion 31 is the same as that of the second edge portion 32, the shape of the second active layer 3 is stepped.
In the present embodiment, since the second edge portion 32 is located on the surface of the first protective layer 4 away from the first edge portion 22, it is necessary to form the first protective layer 4 before forming the second active layer 3. That is, in this embodiment, it is necessary to form the first protection layer 4 covering the first active layer 2, etch the first protection layer 4 to expose the surface of the first middle portion 21 of the first active layer 2, and then form the second active layer 3 on the surface of the first middle portion 21 and the surface of the first protection layer 4 away from the first edge portion 22.
The first protection layer 4 may be etched by dry etching, but is not limited thereto, and may also be etched by wet etching. The inventors of the present disclosure found that when the first protection layer 4 is etched by dry etching, the first active layer 2 is damaged by plasma generated by the dry etching, so that the first active layer 2 becomes conductive, and finally the thin film transistor loses the switching characteristic.
Accordingly, the inventors of the present disclosure have earnestly thought to find that a crystalline oxide can be utilized as the material of the first active layer 2. The crystalline oxide is less susceptible to plasma generated at the time of dry etching after crystallization, and thus switching characteristics of the thin film transistor can be ensured. Meanwhile, after the crystalline oxide is crystallized, the scattering of carriers can be reduced, so that the mobility of the thin film transistor can be greatly improved.
In this embodiment, the crystalline oxide may be: indium Gallium Zinc Oxide (IGZO), Indium Gallium Tin Oxide (IGTO), indium zinc praseodymium oxide (IZYO), and the like can be selected according to actual needs.
Further, the crystalline oxide may be crystallized using an annealing process. The annealing temperatures required for crystallization of different crystalline oxides are different, and the annealing temperatures generally need to be 350 ℃ or higher. The time for annealing the crystalline oxide is usually about 1 hour.
However, the inventors found that by changing the ratio of the IGZO material, the ratio of indium, gallium, and zinc in the IGZO material is adjusted to: indium (b): gallium: when zinc is 1:3:6, IGZO can be crystallized at room temperature. When the IGZO material with the proportion is adopted in the present disclosure, the annealing step can be omitted, so that the manufacturing steps of the thin film transistor can be reduced, and the time for manufacturing the thin film transistor in a large amount can be saved.
In this embodiment, the thin film transistor may further include: a first gate insulating layer 9. The first gate insulating layer 9 may cover at least the second active layer 3, and the gate electrode layer 12 may be located on a surface of the first gate insulating layer 9 away from the first active layer 2. By providing the first gate insulating layer 9, the gate layer 12 can be insulated from the second source layer, and planarization can be performed to facilitate provision of the gate layer 12. The material of the first gate insulating layer 9 may be silicon nitride, but is not limited thereto, and other materials with insulating property may also be used for the first gate insulating layer 9, which is within the protection scope of the present disclosure and can be selected according to actual needs. In addition, the projection of the gate layer 12 on the substrate 1 may be located within the projection of the second intermediate portion 31 on the substrate 1.
In this embodiment, the thin film transistor may further include: a first interlayer dielectric layer 13. The first interlayer dielectric layer 13 may be positioned on a surface of the first gate insulating layer 9 away from the second active layer 3 and cover the gate layer 12. By providing the first interlayer dielectric layer 13, the gate layer 12 and the source/drain electrode 15 can be isolated from each other, and the gate layer 12 and the source/drain electrode 15 are prevented from being influenced by each other.
In addition, the source-drain electrode 15 may be positioned on a surface of the first interlayer dielectric layer 13 on a side away from the second active layer 3. In order to connect the source-drain electrode 15 with the second active layer 3, a first via hole 18 may be provided on the first interlayer dielectric layer 13 and the first gate insulating layer 9, and the source-drain electrode 15 may be connected with the second active layer 3 through the first via hole 18.
Further, in order to further isolate the source-drain electrode 15 from the gate layer 12, the source-drain electrode 15 may be connected to the second edge portion 32. It is to be understood that the projection of the first via 18 on the substrate 1 may be located within the projection of the second edge portion 32 on the substrate 1, so that the source-drain 15 may be connected with the second insulating portion through the first via 18.
In this embodiment, the thin film transistor may further include: a first buffer layer 16 and a third protective layer 6. Here, the first buffer layer 16 may be located on a surface of the substrate 1, the first active layer 2 may be located on a surface of the first buffer layer 16 on a side away from the substrate 1, and a projection of the first active layer 2 on the substrate 1 may be located within a projection of the first buffer layer 16 on the substrate 1. Meanwhile, the first protective layer 4 may also cover a region on the first buffer layer 16 where the first active layer 2 is not disposed.
The third protective layer 6 may cover the first interlayer dielectric layer 13 and the source/drain electrode 15 to protect the source/drain electrode 15 and prevent the source/drain electrode 15 from being damaged. The material of the third protection layer 6 may be silicon nitride, but is not limited thereto, and the third protection layer 6 may also be other insulating materials, which are within the protection scope of the present disclosure and can be selected according to actual needs.
In a second embodiment of the present disclosure, as shown in fig. 2 and 12 to 16, the first protective layer 4 and the second active layer 3 may be the same material, and the first protective layer 4 and the second active layer 3 may be connected to each other. The first protective layer 4 and the second active layer 3 may be simultaneously formed in the same step through one process. Thus, the present disclosure may protect the first active layer 2 by the first and second protection layers 4 and 3 simultaneously formed through one process. For example, the material of the first protective layer 4 and the second active layer 3 may be any one of IGZO, IGTO and IZYO, but is not limited thereto, and other oxide semiconductor materials may be used for the first protective layer 4 and the second active layer 3 as long as it is ensured that they are different from the material of the first active layer 2, and this is within the protection scope of the present disclosure.
Further, in the present embodiment, in order to ensure the protective effect of the first protective layer 4 on the first active layer 2, it is necessary to make the edge of the first protective layer 4 away from the first edge portion 22 have a first distance from the first edge portion 22. It should be noted that, when the edge of the first protection layer 4 away from the first edge portion 22 has a first distance from the first edge portion 22, it can be understood that: the first protective layer 4 may extend a length of a first distance relative to the edge of the first edge portion 22. The first distance may be between 0.4 μm and 1.2 μm, for example: 0.4 μm, 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, etc. But not limited thereto, the first distance may also be set according to actual needs, for example, the first distance may also be greater than 1.2 μm or less than 0.4 μm.
In this embodiment, the thin film transistor provided by the present disclosure may further include a second gate insulating layer 10, the second gate insulating layer 10 may cover the first protective layer 4 and the second active layer 3, and the gate layer 12 may be located on a surface of the second gate insulating layer 10.
By providing the second gate insulating layer 10, the gate electrode layer 12 can be insulated from the second source layer and the first protective layer 4, and planarization can be achieved to facilitate provision of the gate electrode layer 12. The material of the second gate insulating layer 10 may be silicon nitride, but is not limited thereto, and other materials with insulating property may also be used for the second gate insulating layer 10, which is within the protection scope of the present disclosure and can be selected according to actual needs. In addition, the projection of the gate layer 12 on the substrate 1 may be located within the projection of the second intermediate portion 31 on the substrate 1.
The first active layer 2 may be protected due to the first protective layer 4 and the second active layer 3 simultaneously formed through one process according to the present disclosure. Accordingly, the second gate insulating layer 10 cannot contact the first active layer 2, and thus, when the second gate insulating layer 10 is etched, the first active layer 2 may be prevented from being damaged by plasma due to the protection of the first protective layer 4 and the second active layer 3. Therefore, since the first active layer 2 is not damaged by the plasma, in the present embodiment, the material of the first active layer 2 may be a crystalline oxide or an amorphous oxide. Therefore, compared with the structure adopted in the first embodiment, the structure adopted in the present embodiment has a higher degree of freedom in material selection and a simpler process.
In this embodiment, the thin film transistor may further include: a second interlayer dielectric layer 14. The second interlayer dielectric layer 14 may be positioned on a surface of the second gate insulating layer 10 away from the second active layer 3 and cover the gate layer 12. The gate layer 12 and the source/drain electrode 15 can be isolated by providing the second interlayer dielectric layer 14, and the gate layer 12 and the source/drain electrode 15 are prevented from being affected by each other.
In addition, the source-drain electrode 15 may be positioned on a surface of the second interlayer dielectric layer 14 on a side away from the second active layer 3. In order to connect the source and drain electrodes 15 to the second active layer 3, a second via hole 19 may be provided on the second interlayer dielectric layer 14 and the second gate insulating layer 10, and the source and drain electrodes 15 may be connected to the second active layer 3 through the second via hole 19.
Further, in order to further isolate the source-drain electrode 15 from the gate layer 12, the source-drain electrode 15 may be connected to the first protection layer 4 through the second via hole 19, and since the material of the first protection layer 4 is the same as that of the second active layer 3 and is connected to each other, the second via hole 19 may be connected to the second active layer 3 through the first protection layer 4. It is to be understood that the projection of the second via hole 19 on the substrate 1 may be located within the projection of the first protection layer 4 on the substrate 1, so that the source-drain electrode 15 may be connected with the first protection layer 4 through the second via hole 19.
In this embodiment, the thin film transistor may further include: a second buffer layer 17 and a fourth protective layer 7. Here, the second buffer layer 17 may be located on a surface of the substrate 1, the first active layer 2 may be located on a surface of the second buffer layer 17 on a side away from the substrate 1, and a projection of the first active layer 2 on the substrate 1 may be located within a projection of the second buffer layer 17 on the substrate 1. Meanwhile, the first protective layer 4 may also cover a region on the second buffer layer 17 where the first active layer 2 is not disposed, and the second gate insulating layer 10 may also cover a region on the second buffer layer 17 where the first active layer 2 and the first protective layer 4 are not disposed.
The fourth protective layer 7 may cover the second interlayer dielectric layer 14 and the source and drain electrodes 15 to protect the source and drain electrodes 15 and prevent the source and drain electrodes 15 from being damaged. The material of the fourth protection layer 7 may be silicon nitride, but is not limited thereto, and the fourth protection layer 7 may also be other insulating materials, which are within the protection scope of the present disclosure and can be selected according to actual needs.
As can be seen from the above, in this embodiment, since the second active layer 3 and the first protection layer 4 are formed simultaneously by one process, compared with the first embodiment, this embodiment can provide a thin film transistor with one etching step saved in the manufacturing process. In this embodiment, the material of the first active layer 2 may be a crystalline oxide or an amorphous oxide. Therefore, compared with the structure adopted in the first embodiment, the structure adopted in the present embodiment has a higher degree of freedom in material selection and a simpler process.
In a third embodiment of the present disclosure, as shown in fig. 3 and fig. 17 to 21, the gate layer 12 may be located on a surface of the substrate 1 near the first active layer 2. The thin film transistor may further include a third gate insulating layer 11, the third gate insulating layer 11 may cover the gate electrode, and the first active layer 2 may be positioned on a surface of the third gate insulating layer 11 away from the substrate 1. Meanwhile, the first protective layer 4 may also cover a region of the third gate insulating layer 11 where the first active layer 2 is not disposed.
In the present embodiment, the second active layer 3 may have a third middle portion 33 and a third edge portion 34. Wherein the third intermediate portion 33 may be located on a surface of the first intermediate portion 21, it is understood that the third intermediate portion 33 may be the same size as the first intermediate portion 21 such that the third intermediate portion 33 completely covers the first intermediate portion 21. Without limitation, it is within the scope of the present disclosure that third intermediate portion 33 may also be smaller than the size of first intermediate portion 21. When the size of the third middle portion 33 is smaller than that of the first middle portion 21, the first protection layer 4 may also cover a portion of the first middle portion 21, so that the first protection layer 4 is connected to the second active layer 3, thereby preventing the first active layer 2 from being affected when the second active layer 3 is etched, and causing damage to the performance of the thin film transistor.
In addition, the third edge portion 34 of the second active layer 3 may be located on a surface of the first protective layer 4 away from the first edge portion 22 and a surface of a portion of the third middle portion 33 for connecting the source-drain electrodes 15.
In the present embodiment, the thickness of the third middle portion 33 is the same as that of the third edge portion 34, so that the second active layer 3 has good performance. That is, therefore, since the thickness of the second middle portion 31 is the same as that of the second edge portion 32, the shape of the second active layer 3 in the present embodiment is stepped.
In the present embodiment, since the third edge portion 34 is located on the surface of the first protective layer 4 away from the first edge portion 22, it is necessary to form the first protective layer 4 before forming the second active layer 3. That is, in this embodiment, it is necessary to form the first protection layer 4 covering the first active layer 2, etch the first protection layer 4 to expose the surface of the first middle portion 21 of the first active layer 2, and then form the second active layer 3 on the surface of the first middle portion 21 and the surface of the first protection layer 4 away from the first edge portion 22.
In this embodiment, the first protection layer 4 may be etched by dry etching, but is not limited thereto, and may also be etched by wet etching. When the present disclosure etches the first protective layer 4 by dry etching, crystalline oxide may be used as the material of the first active layer 2. The crystalline oxide is less susceptible to plasma generated at the time of dry etching after crystallization, and thus switching characteristics of the thin film transistor can be ensured. Meanwhile, after the crystalline oxide is crystallized, the scattering of carriers can be reduced, so that the mobility of the thin film transistor can be greatly improved.
Further, the crystalline oxide may be crystallized using an annealing process. The annealing temperatures required for crystallization of different crystalline oxides are different, and the annealing temperatures generally need to be 350 ℃ or higher. The time for annealing the crystalline oxide is usually about 1 hour.
However, by changing the ratio of the IGZO material, the ratio of indium, gallium, and zinc in the IGZO material is adjusted to: indium (b): gallium: when zinc is 1:3:6, IGZO can be crystallized at room temperature. When the IGZO material with the proportion is adopted in the present disclosure, the annealing step can be omitted, so that the manufacturing steps of the thin film transistor can be reduced, and the time for manufacturing the thin film transistor in a large amount can be saved.
In this embodiment, the source and drain electrodes 15 may be located at least on the surface of the third edge portion 34, so as to directly connect the source and drain electrodes 15 with the third edge portion 34. Thus, this embodiment does not require an interlayer dielectric layer and also does not require a via hole connecting the source-drain electrode 15 and the third edge portion 34, as compared with the first and second embodiments. Therefore, the process flow of this embodiment is simpler than that of the first and second embodiments.
In this embodiment, the thin film transistor may further include a second protective layer 5, where the second protective layer 5 may at least cover the second active layer 3 and the source/drain 15, so as to protect the second active layer 3 and the source/drain 15 and prevent the second active layer 3 and the source/drain 15 from being damaged. The material of the second protection layer 5 may be silicon nitride, but is not limited thereto, and the second protection layer 5 may also be other insulating materials, which are within the protection scope of the present disclosure and can be selected according to actual needs.
Further, the thin film transistor may further include a fifth protective layer 8, and the fifth protective layer 8 may be located on a surface of the second protective layer 5 on a side away from the second active layer 3. Through the fifth protective layer 8, the second protective layer 5 can be supplemented, so that the second active layer 3 and the source/drain electrode 15 are further prevented from being damaged.
In a fourth embodiment of the present disclosure, as shown in fig. 4 and fig. 22 to 25, the gate layer 12 may be located on a surface of the substrate 1 near the first active layer 2. The thin film transistor may further include a third gate insulating layer 11, the third gate insulating layer 11 may cover the gate electrode, and the first active layer 2 may be positioned on a surface of the third gate insulating layer 11 away from the substrate 1. Meanwhile, the first protective layer 4 may also cover a region of the third gate insulating layer 11 where the first active layer 2 is not disposed.
The first protective layer 4 and the second active layer 3 may be the same material, and the first protective layer 4 and the second active layer 3 may be connected to each other. The first protective layer 4 and the second active layer 3 may be simultaneously formed through one process. Thus, the present disclosure may protect the first active layer 2 by the first and second protection layers 4 and 3 simultaneously formed through one process. For example, the material of the first protective layer 4 and the second active layer 3 may be any one of IGZO, IGTO and IZYO, but is not limited thereto, and other oxide semiconductor materials may be used for the first protective layer 4 and the second active layer 3 as long as it is ensured that they are different from the material of the first active layer 2, and this is within the protection scope of the present disclosure.
Further, in the present embodiment, in order to ensure the protective effect of the first protective layer 4 on the first active layer 2, it is necessary to make the edge of the first protective layer 4 away from the first edge portion 22 have a first distance from the first edge portion 22. It should be noted that, when the edge of the first protection layer 4 away from the first edge portion 22 has a first distance from the first edge portion 22, it can be understood that: the first protective layer 4 may extend a length of a first distance relative to the edge of the first edge portion 22. The first distance may be between 0.4 μm and 1.2 μm, for example: 0.4 μm, 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, etc. But not limited thereto, the first distance may also be set according to actual needs, for example, the first distance may also be greater than 1.2 μm or less than 0.4 μm.
In this embodiment, the source and drain electrodes 15 may be at least located on the surface of the first protective layer 4, so as to directly connect the source and drain electrodes 15 with the first protective layer 4 and the second active layer 3. Thus, in this embodiment, compared to the first and second embodiments, it is not necessary to provide an interlayer dielectric layer, and it is also not necessary to provide a via hole connecting the source-drain electrode 15 and the third edge portion 34. Therefore, the process flow of this embodiment is simpler than that of the first and second embodiments. In addition, since the second active layer 3 and the first protective layer 4 of this embodiment are formed simultaneously by one process, compared with the third embodiment, the thin film transistor provided in this embodiment can save one etching step in the manufacturing process. Meanwhile, in the present embodiment, the material of the first active layer 2 may be a crystalline oxide, and may also be an amorphous oxide. Therefore, compared with the structure adopted in the third embodiment, the structure adopted in the present embodiment has a higher degree of freedom in material selection and a simpler process.
In this embodiment, the thin film transistor may further include a second protective layer 5, where the second protective layer 5 may at least cover the second active layer 3 and the source/drain 15, so as to protect the second active layer 3 and the source/drain 15 and prevent the second active layer 3 and the source/drain 15 from being damaged. The material of the second protection layer 5 may be silicon nitride, but is not limited thereto, and the second protection layer 5 may also be other insulating materials, which are within the protection scope of the present disclosure and can be selected according to actual needs.
Further, the thin film transistor may further include a fifth protective layer 8, and the fifth protective layer 8 may be located on a surface of the second protective layer 5 on a side away from the second active layer 3. Through the fifth protective layer 8, the second protective layer 5 can be supplemented, so that the second active layer 3 and the source/drain electrode 15 are further prevented from being damaged.
The second aspect of the present disclosure provides a method for manufacturing a thin film transistor, where the thin film transistor manufactured by the method for manufacturing a thin film transistor can have better uniformity and no hump phenomenon when two active layers are made of materials with any etching selection ratio, so that the thin film transistor has good stability when two active layers are made of any materials. In addition, the method for manufacturing the thin film transistor can be used for manufacturing the thin film transistor, and therefore, for the specific structure of the thin film transistor, reference can be made to the explanation of the thin film transistor.
As shown in fig. 5, the method for manufacturing a thin film transistor may include:
step S10, providing a substrate 1;
step S20, forming a first active layer 2 on one side of the substrate 1, the first active layer 2 having a first middle portion 21 and first edge portions 22, the first middle portion 21 being located between the first edge portions 22;
step S30, disposing the first protective layer 4 on the first edge portion 22 of the first active layer 2, so that the first protective layer 4 covers at least the first edge portion 22, and forming the second active layer 3 on the surface of the first middle portion 21;
step S40, after forming the first protection layer 4, forming the gate layer 12 on the side of the second active layer 3 away from the substrate 1, or forming the gate layer 12 on the surface of the substrate 1 close to the first active layer 2 before forming the first active layer 2;
step S50 is to form a source/drain electrode 15 on the side of the second active layer 3 away from the substrate 1, and to connect the source/drain electrode 15 with the second active layer 3.
Wherein the materials of the first active layer 2 and the second active layer 3 are different.
The above steps are explained in detail below, specifically:
in step S10, a substrate 1 may be provided, the material of the substrate 1 may be glass, but is not limited thereto, and the substrate 1 may also have other materials, such as: one of polyolefin, polyether ketone, polyimide, polyethylene terephthalate, polyacrylate, silicone, polyethylene, glass resin, polycarbonate, fluoropolymer, or copolymers, mixtures, laminates of the above materials, and the like, are within the scope of the present disclosure and may be selected according to actual needs.
In the first embodiment of the present disclosure, as shown in fig. 6 to 11, after the first protective layer 4 is formed, the gate layer 12 is formed on the side of the second active layer 3 away from the substrate 1, and in step S20, the first active layer 2 may be deposited on the side of the substrate 1 and the patterning process may be performed on the first active layer 2. And annealing the patterned first active layer 2 to crystallize the patterned first active layer 2.
In this embodiment, the material of the first active layer 2 may be a crystalline oxide, which may include IGZO, IGTO, IZYO, and the like, and may be selected according to actual needs. When the annealing process is performed on the patterned first active layer 2, the temperature of the annealing process may be greater than or equal to 350 ℃, and the time of the annealing process may range from 0.5 hours to 1.5 hours, but is not limited thereto.
However, by changing the ratio of the IGZO material, the ratio of indium, gallium, and zinc in the IGZO material is adjusted to: indium (b): gallium: when zinc is 1:3:6, IGZO can be crystallized at room temperature. When the IGZO material with the proportion is adopted in the present disclosure, the annealing step can be omitted, so that the manufacturing steps of the thin film transistor can be reduced, and the time for manufacturing the thin film transistor in a large amount can be saved.
In this embodiment, step S30 may include: the first protective layer 4 covering the first active layer 2 may be formed, and the first protective layer 4 may be etched to expose the first middle portion 21 of the first active layer 2. Specifically, the first protective layer 4 may be etched by dry etching. Since the material of the first active layer 2 is crystalline oxide, the crystallized first active layer 2 can prevent the first active layer 2 from being affected by plasma generated when the first protection layer 4 is dry etched, and meanwhile, the crystallized first active layer 2 can reduce carrier scattering, thereby improving the mobility of the thin film transistor.
Next, the second active layer 3 may be deposited on the surface of the remaining first protective layer 4 away from the first active layer 2 and the surface of the first middle portion 21, and the second active layer 3 may be subjected to a patterning process to make the shape of the second active layer 3 stepped.
The second active layer 3 may have a second middle portion 31 and a second edge portion 32. Wherein the second edge portion 32 may be located at a surface of the first protective layer 4 remote from the first edge portion 22 and at a surface of a portion of the second intermediate portion 31. By the patterning process, the thickness of the second edge portion 32 can be made the same as that of the second middle portion 31, thereby enabling the second active layer 3 to have better performance.
In this embodiment, step S40 may include: a first gate insulating layer 9 is formed to cover at least the second active layer 3. And forming a gate electrode layer 12 on a side of the first gate insulating layer 9 away from the second active layer 3, and patterning the gate electrode layer 12 so that a projection of the gate electrode layer 12 on the substrate 1 is located within a projection of the second intermediate portion 31 on the substrate 1.
Further, the second active layer 3 may be doped with the gate layer 12 as a mask to make the second active layer 3 conductive. Specifically, the gate layer 12 may be used as a mask, and materials such as boron and phosphorus may be doped into the second active layer 3 through a doping process, so as to make the second active layer 3 conductive.
Further, in step S50, a first interlayer dielectric layer 13 may be formed on the surface of the first gate insulating layer 9 away from the second active layer 3, and the first interlayer dielectric layer 13 may cover the gate layer 12. The first trench is etched and the first gate insulating layer 9 is etched to form the first via hole 18 and expose the surface of the second edge portion 32. A material for forming the source and drain electrodes 15 is deposited on the surface of the first interlayer dielectric layer 13 and within the first via hole 18 and subjected to a patterning process to form the source and drain electrodes 15 connected to the second edge portion 32.
In this embodiment, the thin film transistor may further include: a first buffer layer 16 and a third protective layer 6. The manufacturing method of the thin film transistor can further comprise the following steps:
between steps S10 and S20, the first buffer layer 16 may be formed on the surface of the substrate 1. The first active layer 2 and the first protective layer 4 may be formed on a surface of the first buffer layer 16 on a side away from the substrate 1, and a projection of the first active layer 2 on the substrate 1 may be located within a projection of the first buffer layer 16 on the substrate 1.
After step S50, a third protective layer 6 may be formed to cover the first interlayer dielectric layer 13 and the source/drain electrodes 15 to protect the source/drain electrodes 15 from damage. The material of the third protection layer 6 may be silicon nitride, but is not limited thereto, and the third protection layer 6 may also be other insulating materials, which are within the protection scope of the present disclosure and can be selected according to actual needs.
Through the manufacturing method of the thin film transistor, the patterning process can be respectively carried out on the first active layer 2 and the second active layer 3, and the first edge part 22 is protected by forming the first protective layer 4, so that the phenomenon that the first active layer 2 is cut backwards can not be caused when the etching selection ratio of the materials of the first active layer 2 and the second active layer 3 is too small, and the problems that the uniformity of the thin film transistor is poor and the hump phenomenon occurs can be effectively solved.
In the second embodiment of the present disclosure, as shown in fig. 12 to 16, after the first protective layer 4 is formed, the gate layer 12 is formed on the side of the second active layer 3 away from the substrate 1, and in step S20, the first active layer 2 may be formed on the side of the substrate 1 and the patterning process may be performed on the first active layer 2. The material of the first active layer 2 may be a crystalline oxide or an amorphous oxide. Therefore, compared to the previous embodiment, the present embodiment has a wider selection range of the material of the first active layer 2 and a higher process freedom.
In step S30 of the present embodiment, the first protective layer 4 covering the first edge portion 22 and the second active layer 3 on the surface of the first middle portion 21 may be formed using the same material and using the same step, and the first protective layer 4 and the second active layer 3 may be connected. Specifically, materials for forming the first protective layer 4 and the second active layer 3 may be deposited on the surface of the first active layer 2, and the materials for the first protective layer 4 and the second active layer 3 may be etched to form the first protective layer 4 and the second active layer 3.
Thus, in the present embodiment, the etching of the first protective layer 4 and the second active layer 3 can be completed by one etching step. Therefore, compared with the first embodiment, the present embodiment can reduce one etching step, thereby simplifying the manufacturing process of the thin film transistor and shortening the manufacturing time of the thin film transistor.
In step S40 of the present embodiment, the second gate insulating layer 10 covering the first protective layer 4 and the active layer may be formed. A gate layer 12 is formed on the surface of the second gate insulating layer 10, and patterning is performed on the gate layer 12 so that the projection of the gate layer 12 on the substrate 1 is located within the projection of the second active layer 3 on the substrate 1. The material of the second gate insulating layer 10 may be silicon nitride, but is not limited thereto, and other materials may also be adopted, which is within the protection scope of the present disclosure.
Further, in this step, the second active layer 3 and the first protective layer 4 may be doped with the gate layer 12 as a mask to make the second active layer 3 and the first protective layer 4 conductive. Specifically, the gate layer 12 may be used as a mask, and materials such as boron and phosphorus may be doped into the second active layer 3 and the first protective layer 4 through a doping process, so that the second active layer 3 and the first protective layer 4 are made conductive.
Further, in step S50 of the present embodiment, a second interlayer dielectric layer 14 may be formed on the surface of the second gate insulating layer 10 away from the second active layer 3, and the second interlayer dielectric layer 14 may cover the gate layer 12. The second interlayer dielectric layer 14 and the second gate insulating layer 10 are etched to form a second via hole 19 and expose a surface of the first protective layer 4. A material for forming the source and drain electrodes 15 may be deposited on the surface of the second interlayer dielectric layer 14 and in the second via hole 19, and a patterning process may be performed to form the source and drain electrodes 15 connected to the first protective layer 4.
In addition, in this embodiment, the thin film transistor may further include: a second buffer layer 17 and a fourth protective layer 7. The manufacturing method of the thin film transistor can further comprise the following steps:
between steps S10 and S20, a second buffer layer 17 may be formed on the surface of the substrate 1. The first active layer 2 and the first protective layer 4 may be formed on a surface of the second buffer layer 17 on a side away from the substrate 1, and a projection of the first active layer 2 on the substrate 1 may be located within a projection of the second buffer layer 17 on the substrate 1.
After step S50, a fourth protection layer 7 may be formed to cover the second interlayer dielectric layer 14 and the source/drain electrodes 15 to protect the source/drain electrodes 15 from being damaged. The material of the fourth protection layer 7 may be silicon nitride, but is not limited thereto, and the fourth protection layer 7 may also be other insulating materials, which are within the protection scope of the present disclosure and can be selected according to actual needs.
In a third embodiment of the present disclosure, as shown in fig. 17 to 21, before the first active layer 2 is formed, the gate layer 12 is formed on the surface of the substrate 1 near the first active layer 2. In the present embodiment, the steps S20 and S40 may include:
a gate layer 12 is formed on one side of the substrate 1, and patterning processing is performed on the gate layer 12. The third gate insulating layer 11 may be formed to cover the patterned gate electrode layer 12, the first active layer 2 may be formed on a surface of the third gate insulating layer 11 away from the substrate 1, and the patterning process may be performed on the first active layer 2. After the patterning process is performed on the first active layer 2, the patterned first active layer 2 may be subjected to an annealing process to crystallize the patterned first active layer 2.
In this embodiment, the material of the first active layer 2 may be a crystalline oxide, which may include IGZO, IGTO, IZYO, and the like, and may be selected according to actual needs. When the annealing process is performed on the patterned first active layer 2, the temperature of the annealing process may be greater than or equal to 350 ℃, and the time of the annealing process may range from 0.5 hours to 1.5 hours, but is not limited thereto.
However, by changing the ratio of the IGZO material, the ratio of indium, gallium, and zinc in the IGZO material is adjusted to: indium (b): gallium: when zinc is 1:3:6, IGZO can be crystallized at room temperature. When the IGZO material with the proportion is adopted in the present disclosure, the annealing step can be omitted, so that the manufacturing steps of the thin film transistor can be reduced, and the time for manufacturing the thin film transistor in a large amount can be saved.
Further, in step S30 of the present embodiment, the first protective layer 4 covering the first active layer 2 may be formed, and the first protective layer 4 may be etched to expose the first middle portion 21 of the first active layer 2. Specifically, the first protective layer 4 may be etched by dry etching. Since the material of the first active layer 2 is crystalline oxide, the crystallized first active layer 2 can prevent the first active layer 2 from being affected by plasma generated when the first protection layer 4 is dry etched, and meanwhile, the crystallized first active layer 2 can reduce carrier scattering, thereby improving the mobility of the thin film transistor.
Step S30 may further include: the second active layer 3 is deposited on the surface of the remaining first protective layer 4 away from the first active layer 2 and the surface of the first intermediate portion 21, and the second active layer 3 is patterned so that the shape of the second active layer 3 is stepped.
The second active layer 3 may have a third middle portion 33 and a third edge portion 34. Wherein the third edge portion 34 may be located at a surface of the first protective layer 4 remote from the first edge portion 22 and at a surface of a portion of the second intermediate portion 31. By the patterning process, the thickness of the third edge portion 34 can be made the same as that of the third intermediate portion 33, thereby enabling the second active layer 3 to have better performance.
In step S50, a material for forming the source and drain electrodes 15 may be deposited directly on the surface of the third edge portion 34 and etched to form the source and drain electrodes 15 directly on the surface of the third edge portion 34, so that the third edge portion 34 and the source and drain electrodes 15 may be directly connected. Thus, in this embodiment, compared to the first and second embodiments described above, it is not necessary to provide an interlayer dielectric layer, and it is also not necessary to provide a via hole connecting the second active layer 3 and the source/drain electrode 15. Therefore, the process flow of this embodiment is simpler than that of the first and second embodiments.
Further, in this embodiment, the thin film transistor may further include a second protective layer 5 and a fifth protective layer 8, and the method for manufacturing the thin film transistor may further include:
the second protective layer 5 is formed to cover the second active layer 3 and the source and drain electrodes 15 so that the second active layer 3 and the source and drain electrodes 15 are protected from damage by the second protective layer 5.
Further, a fifth protective layer 8 may be formed to cover the second protective layer 5, so as to further protect the second active layer 3 and the source/drain electrode 15 by the fifth protective layer 8.
In a fourth embodiment of the present disclosure, as shown in fig. 22 to 25, before the first active layer 2 is formed, the gate layer 12 is formed on the surface of the substrate 1 near the first active layer 2. In the present embodiment, the steps S20 and S40 may include:
a gate layer 12 is formed on one side of the substrate 1, and patterning processing is performed on the gate layer 12. The third gate insulating layer 11 may be formed to cover the patterned gate electrode layer 12, the first active layer 2 may be formed on a surface of the third gate insulating layer 11 away from the substrate 1, and the patterning process may be performed on the first active layer 2.
In step S30, the first protective layer 4 covering the first edge portion 22 and the second active layer 3 on the surface of the first middle portion 21 may be formed using the same material and using the same step, and the first protective layer 4 and the second active layer 3 may be connected. Specifically, materials for forming the first protective layer 4 and the second active layer 3 may be deposited on the surface of the first active layer 2, and the materials for the first protective layer 4 and the second active layer 3 may be etched to form the first protective layer 4 and the second active layer 3.
Thus, in the present embodiment, the etching of the first protective layer 4 and the second active layer 3 can be completed by one etching step. Therefore, compared with the third embodiment, the present embodiment can reduce one etching step, thereby simplifying the manufacturing process of the thin film transistor and shortening the manufacturing time of the thin film transistor.
Further, in step S50, a material for forming the source/drain electrode 15 may be directly deposited on the surface of the first protection layer 4 and etched to directly form the source/drain electrode 15 on the surface of the first protection layer 4, so that the first protection layer 4 and the source/drain electrode 15 may be directly connected. Since the first protective layer 4 and the second active layer 3 are formed through the same step, and the materials are the same and are connected to each other, the source and drain electrodes 15 of the present disclosure may be connected to the second active layer 3 by being connected to the first protective layer 4.
Thus, in this embodiment, compared to the first and second embodiments, it is not necessary to provide an interlayer dielectric layer, and it is also not necessary to provide a via hole connecting the source-drain electrode 15 and the third edge portion 34. Therefore, the process flow of this embodiment is simpler than that of the first and second embodiments. In this embodiment, the material of the first active layer 2 may be a crystalline oxide or an amorphous oxide. Therefore, compared with the manufacturing method adopted in the third embodiment, the manufacturing method adopted in the present embodiment has a higher degree of freedom in material selection and a simpler process.
In addition, in this embodiment, the thin film transistor may further include a second protective layer 5 and a fifth protective layer 8, and the method for manufacturing the thin film transistor may further include:
the second protective layer 5 is formed to cover the second active layer 3 and the source and drain electrodes 15 so that the second active layer 3 and the source and drain electrodes 15 are protected from damage by the second protective layer 5. It should be noted that when the source/drain electrode 15 does not cover the entire surface of the first protection layer 4, the second protection layer 5 may also cover the remaining portion on the first protection layer 4.
Further, a fifth protective layer 8 may be formed to cover the second protective layer 5, so as to further protect the second active layer 3 and the source/drain electrode 15 by the fifth protective layer 8.
It should be noted that although the steps of the method for fabricating a thin film transistor in the present disclosure are depicted in the drawings in a particular order, this does not require or imply that all of the steps must be performed in this particular order to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
A third aspect of the present disclosure provides an array substrate, which may include the thin film transistor described above. Therefore, the thin film transistor in the array substrate can have better uniformity and no hump phenomenon when the first active layer 2 and the second active layer 3 are made of materials with any etching selection ratio. This makes it possible to provide the array substrate 1 with good operational stability.
A fourth aspect of the present disclosure provides a display panel, which may include the array substrate described above. The thin film transistor in the array substrate can have better uniformity and no hump phenomenon when the first active layer 2 and the second active layer 3 are made of materials with any etching selection ratio. Therefore, the display panel can have good working stability.
A fifth aspect of the present disclosure provides a display device, which may include the display panel described above. The thin film transistor in the display panel can have better uniformity and no hump phenomenon when the first active layer 2 and the second active layer 3 are made of materials with any etching selection ratio. Therefore, the display device can have good working stability.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (27)

1. A thin film transistor, comprising:
a substrate;
a first active layer on one side of the substrate, the first active layer having a first middle portion and first edge portions, the first middle portion being between the first edge portions;
a second active layer at least at a surface of the first intermediate portion;
a first protective layer covering at least a first edge portion of the first active layer;
the source and drain electrodes are positioned on one side of the second active layer, which is far away from the substrate, and are connected with the second active layer;
the gate layer is positioned on one side of the second active layer far away from the substrate or on the surface of the substrate close to the first active layer;
wherein the first active layer and the second active layer are different in material.
2. The thin film transistor of claim 1, wherein the second active layer has a second middle portion and a second edge portion, wherein the second middle portion is located on a surface of the first middle portion, and the second edge portion is located on a surface of the first protective layer away from the first edge portion and a portion of the second middle portion; the thin film transistor further includes:
the first gate insulating layer at least covers the second active layer, and the gate layer is positioned on the surface of the first gate insulating layer far away from the first active layer.
3. The thin film transistor according to claim 2, further comprising:
the first interlayer dielectric layer is positioned on the surface, far away from the second active layer, of the first grid insulating layer and covers the grid layer, first through holes are formed in the first interlayer dielectric layer and the first grid insulating layer, and the source electrode and the drain electrode are positioned on the surface, far away from the second active layer, of the first interlayer dielectric layer and are connected with the second active layer through the first through holes.
4. The thin film transistor according to claim 2, wherein a material of the first active layer is a crystalline oxide.
5. The thin film transistor according to claim 1, wherein the first protective layer and the second active layer are made of the same material, and the first protective layer and the second active layer are connected to each other; the thin film transistor further includes:
and the second gate insulating layer covers the first protective layer and the second active layer, and the gate layer is positioned on the surface of the second gate insulating layer.
6. The thin film transistor of claim 5, wherein an edge of the first protective layer away from the first edge portion has a first distance from the first edge portion, the first distance being between 0.4 μm and 1.2 μm.
7. The thin film transistor according to claim 5, further comprising:
the second interlayer dielectric layer is positioned on the surface, far away from the second active layer, of the second gate insulating layer and covers the gate layer, second through holes are formed in the second interlayer dielectric layer and the second gate insulating layer, the source and drain electrodes are positioned on the surface of one side, far away from the second active layer, of the second interlayer dielectric layer, and the source and drain electrodes are connected with the first protective layer through the second through holes.
8. The thin film transistor of claim 1, wherein the gate layer is on a surface of the substrate adjacent to the first active layer, the thin film transistor further comprising:
the third gate insulating layer covers the gate, and the first active layer is located on the surface of the third gate insulating layer far away from the substrate.
9. The thin film transistor of claim 8, wherein the second active layer has a third middle portion and a third edge portion, wherein the third middle portion is located on a surface of the first middle portion, the third edge portion is located on a surface of the first protection layer away from the first edge portion and a portion of the third middle portion, and the source and drain electrodes are located on at least a surface of the third edge portion.
10. The thin film transistor according to claim 8, wherein the first protective layer and the second active layer are made of the same material, the first protective layer and the second active layer are connected to each other, and the source and drain electrodes are at least located on the surfaces of the first protective layer and a portion of the second active layer.
11. The thin film transistor according to claim 9 or 10, further comprising:
and the second protective layer at least covers the second active layer and the source and drain electrodes.
12. A method for manufacturing a thin film transistor includes:
providing a substrate;
forming a first active layer on one side of the substrate, the first active layer having a first middle portion and first edge portions, the first middle portion being located between the first edge portions;
arranging a first protective layer at a first edge part of the first active layer, enabling the first protective layer to at least cover the first edge part, and forming a second active layer on the surface of the first middle part;
forming a gate layer on the side of the second active layer far away from the substrate after forming the first protection layer, or forming a gate layer on the surface of the substrate near the first active layer before forming the first active layer;
forming a source drain on one side of the second active layer, which is far away from the substrate, and connecting the source drain with the second active layer;
wherein the first active layer and the second active layer are different in material.
13. The method according to claim 12, wherein after the first protective layer is formed, a gate layer is formed on a side of the second active layer away from the substrate; the forming of the first active layer at one side of the substrate includes:
depositing a first active layer on one side of the substrate, and patterning the first active layer;
and annealing the patterned first active layer to crystallize the patterned first active layer.
14. The method for manufacturing a thin film transistor according to claim 13, wherein the temperature of the annealing is 350 ℃ or higher, and the time range of the annealing is: between 0.5 hours and 1.5 hours.
15. The method of claim 13, wherein the disposing a first passivation layer on the first edge portion of the first active layer such that the first passivation layer covers at least the first edge portion and forming a second active layer on the surface of the first middle portion comprises:
forming the first protective layer covering the first active layer;
etching the first protective layer to expose a first middle portion of the first active layer;
and depositing a second active layer on the surface of the remaining first protection layer far away from the first active layer and the surface of the first middle part, and patterning the second active layer.
16. The method of claim 15, wherein forming a gate layer on a side of the second active layer away from the substrate after forming the first passivation layer comprises:
forming a first gate insulating layer at least covering the second active layer;
and forming a gate layer on one side of the first gate insulating layer, which is far away from the second active layer, and carrying out patterning treatment on the gate layer.
17. The method of claim 16, wherein the second active layer has a second middle portion and a second edge portion, the second edge portion is located on a surface of the first protection layer away from the first edge portion and a portion of a surface of the second middle portion, and the forming of the source and drain electrodes on a side of the second active layer away from the substrate and the connecting of the source and drain electrodes to the second active layer includes:
forming a first interlayer dielectric layer on the surface of the first gate insulating layer far away from the second active layer, and enabling the first interlayer dielectric layer to cover the gate layer;
etching the first interlayer dielectric layer and the first gate insulating layer to form a first through hole and expose the surface of the second edge part;
and depositing a material for forming a source drain electrode on the surface of the first interlayer dielectric layer and in the first through hole, and performing patterning treatment to form the source drain electrode connected with the second edge part.
18. The method according to claim 12, wherein after the first protective layer is formed, a gate layer is formed on a side of the second active layer away from the substrate; the disposing a first protection layer at a first edge portion of the first active layer, so that the first protection layer at least covers the first edge portion, and forming a second active layer on a surface of the first middle portion, includes:
and forming a first protective layer covering the first edge part and a second active layer positioned on the surface of the first middle part by using the same material and the same step, and connecting the first protective layer and the second active layer.
19. The method of claim 18, wherein forming a gate layer on a side of the second active layer away from the substrate after forming the first passivation layer comprises:
forming a second gate insulating layer covering the first protective layer and the second active layer;
and forming a gate layer on the surface of the second insulating gate layer, and patterning the gate layer.
20. The method of claim 19, wherein forming a source/drain on a side of the second active layer away from the substrate and connecting the source/drain to the second active layer comprises:
forming a second interlayer dielectric layer on the surface, far away from the second active layer, of the second gate insulating layer, and enabling the second interlayer dielectric layer to cover the gate layer;
etching the second interlayer dielectric layer and the second gate insulating layer to form a second through hole and expose the surface of the first protective layer;
and depositing a material for forming a source and a drain on the surface of the second interlayer dielectric layer and in the second through hole, and performing patterning treatment to form the source and the drain connected with the first protective layer.
21. The method of claim 12, wherein forming a gate layer on a surface of the substrate adjacent to the first active layer before forming the first active layer, the forming the first active layer on one side of the substrate comprises:
forming a gate layer on one side of the substrate, and patterning the gate layer;
forming a third gate insulating layer to cover the gate layer after the patterning process;
forming the first active layer on the surface of the third gate insulating layer, which is far away from the substrate, and carrying out patterning treatment on the first active layer;
and annealing the patterned first active layer to crystallize the patterned first active layer.
22. The method of claim 21, wherein the disposing a first passivation layer on the first edge portion of the first active layer such that the first passivation layer covers at least the first edge portion and forming a second active layer on the surface of the first middle portion comprises:
forming the first protective layer covering the first active layer;
etching the first protective layer to expose a first middle portion of the first active layer;
and depositing a second active layer on the surface of the remaining first protection layer far away from the first active layer and the surface of the first middle part, and patterning the second active layer.
23. The method of claim 21, wherein the disposing a first passivation layer on the first edge portion of the first active layer such that the first passivation layer covers at least the first edge portion and forming a second active layer on the surface of the first middle portion comprises:
and forming a first protective layer covering the first edge part and a second active layer positioned on the surface of the first middle part by using the same material and the same step, and connecting the first protective layer and the second active layer.
24. The method for manufacturing a thin film transistor according to claim 22 or 23, further comprising:
and forming a second protective layer at least covering the second active layer and the source and drain electrodes.
25. An array substrate comprising the thin film transistor according to any one of claims 1 to 11.
26. A display panel comprising the array substrate of claim 25.
27. A display device, characterized in that it comprises a display panel as claimed in claim 26.
CN202111429653.8A 2021-11-29 2021-11-29 Thin film transistor, manufacturing method thereof, array substrate, display panel and device Pending CN114122148A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111429653.8A CN114122148A (en) 2021-11-29 2021-11-29 Thin film transistor, manufacturing method thereof, array substrate, display panel and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111429653.8A CN114122148A (en) 2021-11-29 2021-11-29 Thin film transistor, manufacturing method thereof, array substrate, display panel and device

Publications (1)

Publication Number Publication Date
CN114122148A true CN114122148A (en) 2022-03-01

Family

ID=80370974

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111429653.8A Pending CN114122148A (en) 2021-11-29 2021-11-29 Thin film transistor, manufacturing method thereof, array substrate, display panel and device

Country Status (1)

Country Link
CN (1) CN114122148A (en)

Similar Documents

Publication Publication Date Title
KR101613029B1 (en) Thin film transistor and manufacturing method thereof, and display device
CN111415948B (en) Array substrate, display panel, display device and preparation method of array substrate
CN101840865B (en) Manufacturing method of thin film transistor and transistor manufactured by method
KR20080104860A (en) Fabrication method of zno family thin film transistor
CN106449732B (en) Thin film transistor, manufacturing method thereof and display panel
EP1536482A1 (en) Thin film transistor with tapered edges
US9159746B2 (en) Thin film transistor, manufacturing method thereof, array substrate and display device
CN103094359A (en) High voltage Schottky diode and manufacturing method thereof
CN105097829A (en) Array substrate and preparation method thereof
US9570482B2 (en) Manufacturing method and manufacturing equipment of thin film transistor substrate
CN112397573B (en) Array substrate, preparation method thereof and display panel
CN112259553B (en) Array substrate, preparation method thereof and display panel
CN105140291A (en) Film transistor, manufacturing method thereof, array substrate and display device
CN109119427B (en) Manufacturing method of back channel etching type TFT substrate and back channel etching type TFT substrate
CN114122148A (en) Thin film transistor, manufacturing method thereof, array substrate, display panel and device
CN105633171A (en) Thin film transistor and manufacturing method therefor, and display apparatus
CN106711155B (en) Array substrate, display panel and display device
KR20120067108A (en) Array substrate and method of fabricating the same
CN101976685B (en) Transistor structure with etch stop layer and manufacturing method thereof
CN111048523A (en) Array substrate and preparation method thereof
KR101973269B1 (en) Oxide Semiconductor Thin Film Transistor and Fabricating Method Thereof
KR101950834B1 (en) Oxide thin film transistor and method for fabricating the same
CN115036271B (en) Metal oxide semiconductor thin film transistor array substrate, manufacturing method thereof and display device
KR102145978B1 (en) Array substrate and method for fabricating of the same
CN113224172B (en) Thin film transistor and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination