CN114067760B - 显示驱动设备和方法 - Google Patents
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Abstract
本发明涉及一种具有降低功耗的功率控制电路的显示驱动设备和方法,显示驱动设备包含:移位寄存器,接收显示数据信号且输出多个数据信号;第一锁存器,接收多个数据信号中的第N数据信号且根据第一栅极驱动信号来输出第一锁存数据信号;模拟信号处理电路,包含第二锁存器,第二锁存器耦合到第一锁存器且根据第二栅极驱动信号来输出第二锁存数据信号;数据比较器,将第一锁存数据信号与第二锁存数据信号进行比较;以及功率控制器,耦合到数据比较器且控制模拟信号处理电路的功率电平。
Description
技术领域
本公开涉及一种显示驱动设备和一种显示驱动方法。
背景技术
通常,显示面板的像素元件(即,液晶或发光二极管)由源极驱动器充电/放电以根据由源极驱动器接收到的显示数据信号来形成用于显示的像素电压。源极驱动器根据对应于显示面板的每一通道的多个栅极驱动信号对显示面板的每一通道进行充电/放电。以图5中的源极驱动信号(Y[n])和栅极驱动信号(G[m]、G[m+1])的信号时序图作为实例,源极驱动器输出源极驱动信号(Y[n],实线),且根据栅极驱动信号(G[m])的下降沿将源极驱动信号(Y[n])传输到显示面板的第m通道并根据栅极驱动信号(G[m+1])的下降沿将源极驱动信号(Y[n])传输到显示面板的第(m+1)通道。
由于根据栅极驱动信号的对应下降沿将源极驱动信号(Y[n])传输到显示面板的每一通道,因此根据栅极驱动信号的对应下降沿之前的显示数据信号将源极驱动信号(Y[n])的电压充电/放电到电压电平。用于产生源极驱动信号(Y[n])的源极驱动器的一部分可设定成在从A到A'或从B到B'的时间间隔中断电以降低功耗。
本文中的任何内容都不应解释为对本公开的任何部分的现有技术中的知识的认可。
发明内容
介绍一种显示驱动设备和方法,其中源极驱动器的一部分设定成在时间间隔中断电以产生到显示面板的每一通道的源极驱动信号。此外,根据由源极驱动器接收到的显示数据信号来设定源极驱动器的所述部分的断电时间间隔。
在本公开的实施例中,所述显示驱动设备包含:移位寄存器,接收显示数据信号且输出多个数据信号;第一锁存器,接收多个数据信号中的第N数据信号且根据第一栅极驱动信号来输出第一锁存数据信号;模拟信号处理电路,包含第二锁存器,所述第二锁存器耦合到第一锁存器且根据第二栅极驱动信号来输出第二锁存数据信号;数据比较器,将第一锁存数据信号与第二锁存数据信号进行比较;以及功率控制器,耦合到数据比较器且控制模拟信号处理电路的功率电平。
在本公开的实施例中,所述显示驱动方法包含:接收显示数据信号且输出多个数据信号;接收多个数据信号中的第N数据信号,其中N为正整数;根据第一栅极驱动信号来输出第一锁存数据信号;根据第二栅极驱动信号来输出第二锁存数据信号;将第一锁存数据信号与第二锁存数据信号进行比较;控制源极驱动信号的功率电平;以及输出源极驱动信号。
总而言之,由本公开提供的显示驱动设备和方法通过根据由源极驱动器接收到的显示数据信号将源极驱动器的部分设定成在时间间隔中断电来产生到显示面板的每一通道的源极驱动信号,以降低功耗。
为了可更好地理解前述内容,如下详细地描述附有图的若干实施例。
附图说明
包含附图以提供对本公开的进一步理解,且附图并入本说明书中并构成本说明书的一部分。附图示出本公开的示范性实施例,且与实施方式一起用来解释本公开的原理。
图1为根据本公开的实施例的显示驱动设备100的示意图。
图2为根据本公开的实施例的显示驱动设备100的示意图。
图3为根据本公开的实施例的显示驱动设备100的信号时序图。
图4为根据本公开的另一实施例的显示驱动设备100的信号时序图。
图5为根据本公开的实施例的显示驱动设备100的信号时序图。
附图标号说明
100:显示驱动设备;
101:输出缓冲器;
102:模拟信号处理电路;
t1、t2、t3、t4:断电时间间隔;
AA'、BB':时间间隔;
ABS(Data[N](t)-Data[N](t-1)):比较结果;
Data[1]、Data[2]、Data[N]:数据信号;
Data[N](t):第一锁存数据信号;
Data[N](t-1):第二锁存数据信号;
G[0]、G[1]、G[2]、G[3]、G[m]、G[m+1]:栅极驱动信号;
V_0、V_128、V_130、V_255:电压电平;
Y[1]、Y[2]、Y[n]、Y[N]:源极驱动信号。
具体实施方式
下文中参考附图描述本公开的实施例。
图1为根据本公开的实施例的显示驱动设备100的示意图。显示驱动设备100包含接收器RX、移位寄存器、多个第一锁存器(锁存器1)以及模拟信号处理电路102和功率控制电路(图1中未绘示)。模拟信号处理电路102包含多个第二锁存器(锁存器2)、电平移位器、数模转换器(digital to analog converter;DAC)以及输出缓冲器101。接收器RX接收显示数据信号。移位寄存器从接收器RX串行地接收数据信号且将数据信号Data[1]、数据信号Data[2]……数据信号Data[N]并行输出到多个第一锁存器(锁存器1)。模拟信号处理电路102耦合到多个第一锁存器(锁存器1)且将源极驱动信号Y[1]、源极驱动信号Y[2]……源极驱动信号Y[N]输出到显示面板的每一通道,且源极驱动信号Y[1]、源极驱动信号Y[2]……源极驱动信号Y[N]的电压电平由模拟信号处理电路102根据数据信号Data[1]、数据信号Data[2]……数据信号Data[N]分别设定,其中数据信号Data[1]、数据信号Data[2]……数据信号Data[N]包含灰度值。功率控制电路根据数据信号Data[1]、数据信号Data[2]……数据信号Data[N]来控制模拟信号处理电路102的一部分的断电时间间隔。
图2为根据本公开的实施例的显示驱动设备100的示意图。如图1和图2中所绘示,模拟信号处理电路102的第n分支耦合到接收数据信号Data[N]的锁存器1且将源极驱动信号Y[N]输出到显示面板的每一通道。锁存器1接收数据信号Data[N]且根据第一栅极驱动信号将第一锁存数据信号Data[N](t)输出到数据比较器。锁存器2耦合到锁存器1且根据第二栅极驱动信号将第二锁存数据信号Data[N](t-1)输出到数据比较器,其中显示面板的相邻通道受第一栅极驱动信号和第二栅极驱动信号控制。
数据比较器将第一锁存数据信号Data[N](t)与第二锁存数据信号Data[N](t-1)进行比较,且将包含第一锁存数据信号与第二锁存数据信号之间的差的绝对值的比较结果ABS(Data[N](t)-Data[N](t-1))输出到功率控制器。功率控制器根据比较结果来控制模拟信号处理电路102的部分(例如电平移位器、DAC以及输出缓冲器)的断电时间间隔。
图3为根据本公开的实施例的显示驱动设备100的信号时序图。图3绘示产生源极驱动信号Y[1]的模拟信号处理电路102的第1分支以及产生源极驱动信号Y[2]的模拟信号处理电路102的第2分支的通电-断电时序图。数据信号Data[1]由锁存器2根据栅极驱动信号G[0](图3中未绘示)锁存为等于灰度值0的Data[1](t=1),数据信号Data[1]由锁存器1根据栅极驱动信号G[1]锁存为等于灰度值255的Data[1](t=2),数据比较器将Data[1](t=1)与Data[1](t=2)进行比较且将等于255的比较结果ABS(255-0)输出到功率控制器。在对应于栅极驱动信号G[1]的循环周期期间,功率控制器根据比较结果ABS(255-0)将模拟信号处理电路102的部分的断电时间间隔控制成t1。当功率控制器将模拟信号处理电路102的部分从断电时间间隔t1设定成通电时间间隔时,在对应于栅极驱动信号G[1]的循环周期期间,模拟信号处理电路102将源极驱动信号Y[1]的电压电平从V_0设定成V_255。
在对应于栅极驱动信号G[2]的下一循环周期期间,数据信号Data[1]由锁存器2根据栅极驱动信号G[1]锁存为等于灰度值255的Data[1](t=2),数据信号Data[1]由锁存器1根据栅极驱动信号G[2]锁存为等于灰度值128的Data[1](t=3),数据比较器将Data[1](t=2)与Data[1](t=3)进行比较且将等于127的比较结果ABS(128-255)输出到功率控制器。在对应于栅极驱动信号G[2]的循环周期期间,功率控制器根据比较结果ABS(128-255)将模拟信号处理电路102的部分的断电时间间隔控制成t2。当功率控制器将模拟信号处理电路102的部分从断电时间间隔t2设定成通电时间间隔时,在对应于栅极驱动信号G[2]的循环周期期间,模拟信号处理电路102将源极驱动信号Y[1]的电压电平从V_255设定成V_128。
在对应于栅极驱动信号G[3]的下一循环周期期间,数据信号Data[1]由锁存器2根据栅极驱动信号G[2]锁存为等于灰度值128的Data[1](t=3),数据信号Data[1]由锁存器1根据栅极驱动信号G[3]锁存为等于灰度值130的Data[1](t=4),数据比较器将Data[1](t=3)与Data[1](t=4)进行比较且将等于2的比较结果ABS(130-128)输出到功率控制器。在对应于栅极驱动信号G[3]的循环周期期间,功率控制器根据比较结果ABS(130-128)将模拟信号处理电路102的部分的断电时间间隔控制成t3。当功率控制器将模拟信号处理电路102的部分从断电时间间隔t3设定成通电时间间隔时,在对应于栅极驱动信号G[3]的循环周期期间,模拟信号处理电路102将源极驱动信号Y[1]的电压电平从V_128设定成V_130。
另外,功率控制器控制产生源极驱动信号Y[2]的模拟信号处理电路102的第2分支的断电时间间隔设定成t4。由于由锁存器1和锁存器2锁存的数据信号Data[N]的变化越大(即,ABS(255-0)>ABS(128-255)>ABS(130-128)>ABS(0-0)),需要的充电/放电时间越长,所以模拟信号处理电路102的每一分支的断电时间间隔可由功率控制器设定为与比较结果(即,t1<t2<t3<t4)成反比。
图4为根据本公开的另一实施例的显示驱动设备100的信号时序图。模拟信号处理电路102的每一分支的断电时间间隔可由功率控制器根据由锁存器1锁存的数据信号Data[N]与由锁存器2锁存的数据信号Data[N]之间的最大差(即,ABS(255-0))来设定为相同的。
根据以上实施例,具有根据显示数据信号来控制模拟信号处理电路102的每一分支的断电时间间隔的功率控制器的显示驱动设备100降低显示驱动设备100的功耗。
对本领域的技术人员显而易见的是,可在不脱离本公开的范围或精神的情况下对所公开的实施例进行各种修改和变化。鉴于是以上内容,希望本公开在所述修改和变化属于所附权利要求书和其等效物的范围内的条件下,涵盖所述修改和变化。
Claims (17)
1.一种适于驱动显示面板的显示驱动设备,包括:
移位寄存器,接收显示数据信号且输出多个数据信号;
第一锁存器,接收所述多个数据信号中的第N数据信号且根据第一栅极驱动信号来输出第一锁存数据信号,其中N为正整数;
模拟信号处理电路,包括:
第二锁存器,耦合到所述第一锁存器且根据第二栅极驱动信号来输出第二锁存数据信号;
数据比较器,将所述第一锁存数据信号与所述第二锁存数据信号进行比较;以及
功率控制器,耦合到所述数据比较器且控制所述模拟信号处理电路的功率电平。
2.根据权利要求1所述的显示驱动设备,其中所述显示面板的相邻通道受所述第一栅极驱动信号和所述第二栅极驱动信号控制。
3.根据权利要求1所述的显示驱动设备,其中所述数据比较器输出包括所述第一锁存数据信号与所述第二锁存数据信号之间的差的绝对值的比较结果。
4.根据权利要求3所述的显示驱动设备,其中所述功率控制器根据所述比较结果来控制所述模拟信号处理电路的断电时间间隔。
5.根据权利要求4所述的显示驱动设备,其中所述模拟信号处理电路的所述断电时间间隔设定为与所述比较结果成反比。
6.根据权利要求4所述的显示驱动设备,其中根据所述第一锁存数据信号与所述第二锁存数据信号之间的最大差将所述模拟信号处理电路的所述断电时间间隔设定为相同的。
7.根据权利要求1所述的显示驱动设备,其中所述多个数据信号包括灰度值。
8.根据权利要求1所述的显示驱动设备,其中所述模拟信号处理电路进一步包括:
电平移位器,耦合到所述第二锁存器;
数模转换器,耦合到所述电平移位器;以及
输出缓冲器,耦合到所述数模转换器且输出源极驱动信号。
9.根据权利要求8所述的显示驱动设备,其中所述输出缓冲器输出具有与所述第N数据信号的灰度值成比例的电压电平的所述源极驱动信号。
10.一种适于驱动显示面板的显示驱动方法,包括:
接收显示数据信号且输出多个数据信号;
接收所述多个数据信号中的第N数据信号,其中N为正整数;
根据第一栅极驱动信号来输出第一锁存数据信号;
根据第二栅极驱动信号来输出第二锁存数据信号;
将所述第一锁存数据信号与所述第二锁存数据信号进行比较;
控制源极驱动信号的功率电平;以及
输出所述源极驱动信号。
11.根据权利要求10所述的显示驱动方法,其中所述显示面板的相邻通道受所述第一栅极驱动信号和所述第二栅极驱动信号控制。
12.根据权利要求10所述的显示驱动方法,其中输出包括所述第一锁存数据信号与所述第二锁存数据信号之间的差的绝对值的比较结果。
13.根据权利要求12所述的显示驱动方法,其中根据所述比较结果来控制模拟信号处理电路的断电时间间隔。
14.根据权利要求13所述的显示驱动方法,其中所述模拟信号处理电路的所述断电时间间隔设定为与所述比较结果成反比。
15.根据权利要求13所述的显示驱动方法,其中根据所述第一锁存数据信号与所述第二锁存数据信号之间的最大差将所述模拟信号处理电路的所述断电时间间隔设定为相同的。
16.根据权利要求10所述的显示驱动方法,其中所述多个数据信号包括灰度值。
17.根据权利要求10所述的显示驱动方法,其中所述源极驱动信号具有与所述第N数据信号的灰度值成比例的电压电平。
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