CN114040598A - Method for removing flash of metalized half hole of electric gold plate - Google Patents
Method for removing flash of metalized half hole of electric gold plate Download PDFInfo
- Publication number
- CN114040598A CN114040598A CN202111287027.XA CN202111287027A CN114040598A CN 114040598 A CN114040598 A CN 114040598A CN 202111287027 A CN202111287027 A CN 202111287027A CN 114040598 A CN114040598 A CN 114040598A
- Authority
- CN
- China
- Prior art keywords
- board
- hole
- production board
- layer
- production
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- 229910052737 gold Inorganic materials 0.000 title claims abstract description 18
- 239000010931 gold Substances 0.000 title claims abstract description 18
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 52
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 20
- 229910052802 copper Inorganic materials 0.000 claims abstract description 17
- 239000010949 copper Substances 0.000 claims abstract description 17
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000007747 plating Methods 0.000 claims abstract description 9
- 238000005553 drilling Methods 0.000 claims abstract description 8
- 238000009713 electroplating Methods 0.000 claims abstract description 8
- 230000008021 deposition Effects 0.000 claims abstract description 7
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 7
- 238000010030 laminating Methods 0.000 claims description 4
- 239000011889 copper foil Substances 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 3
- 238000004381 surface treatment Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000003786 synthesis reaction Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 52
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 229910052759 nickel Inorganic materials 0.000 description 7
- 230000007547 defect Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000012360 testing method Methods 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000002274 desiccant Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
Abstract
The invention discloses a method for removing a flash of a metallized half hole of an electric gold plate, which comprises the following steps: drilling a hole on the production plate, and then sequentially carrying out copper deposition and full-plate electroplating to metalize the hole; plating a tin layer on the surface of the production plate; routing half holes on a production plate through a forming process; removing burrs in the hole and at the hole opening through alkaline etching, and then removing the tin layer; pasting a film on the production board, and then sequentially exposing and developing to form an outer layer circuit pattern; carrying out electroless nickel-gold treatment on the production plate; pasting a second layer of film on the production board, and windowing at the position corresponding to the position of the outer layer circuit pattern needing the electric gold; carrying out local electrogilding treatment on the production plate, and then stripping the film; and etching the production board to form an outer layer circuit. According to the method, a tinning process, half-hole routing and alkaline etching are added before the outer-layer circuit is manufactured, and the flash of the half-hole is etched and removed under the condition of tin layer protection, so that the metallized half-hole manufacturing is realized.
Description
Technical Field
The invention relates to the technical field of printed circuit board manufacturing, in particular to a method for removing a plated metal half-hole flash.
Background
In the PCB production process, the half-via metallization of the electrical board is generally performed by drilling a through-hole on the PCB, then sequentially performing copper deposition, board electroplating, pattern nickel gold plating, and the like on the through-hole to metallize the through-hole and plate the gold layer, and then forming the through-hole by routing half of the through-hole to form the half-via metallization. The main process flow is as follows: front process → drilling → copper deposition, board electric → outer layer pattern → pattern nickel gold → outer layer pattern (2) → local electrogilding → shaping (routing half-hole) → alkaline etching (stripping, etching) → next process
The prior art has the following defects:
through an alkaline etching method, copper wires at the half-hole positions are etched completely relatively easily, but nickel wires and gold wires at the half-hole positions cannot be etched completely due to the nickel and gold alkaline-resistant etching liquid, so that a metal burr is formed; these metal burrs can seriously influence the efficiency of client end parts loading and are not accepted by clients, and the problems of difficult repair, labor cost waste and the like exist for manufacturing enterprises, finally the yield is reduced, and the enterprise cost is increased.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a method for removing a metalized half-hole flash of an electric gold plate.
In order to solve the above technical problem, the present invention provides a method for removing a flash of a metallized half-hole of an electric metal plate, comprising the following steps:
s1, drilling holes on the production board, and then sequentially carrying out copper deposition and full-board electroplating to metalize the holes;
s2, plating a tin layer on the surface of the production board;
s3, routing half holes on the production board through a forming process;
s4, removing burrs in and at the hole by alkaline etching, and then removing the tin layer;
s5, pasting a film on the production board, and then sequentially exposing and developing to form an outer circuit pattern;
s6, performing electroless nickel-gold treatment on the production board;
s7, pasting a second layer of film on the production board, and windowing at the position corresponding to the position of the outer layer circuit pattern needing the electrogilding;
s8, carrying out local electrogilding treatment on the production board, and then stripping the film;
and S9, etching the production board to form an outer layer circuit.
Further, in step S1, the production board is a core board.
Further, in step S1, the production board is a multi-layer board formed by laminating an inner core board and an outer copper foil together by a prepreg, and the inner core board is manufactured with an inner circuit before lamination.
Further, in step S2, a tin layer is plated on the production board through a pattern plating process.
Further, the thickness of the tin layer is 3-5 μm.
Further, step S9 is followed by the following steps:
and S10, sequentially manufacturing a solder mask layer and performing surface treatment and light synthesis on the production board to manufacture the electric gold plate.
Compared with the prior art, the invention has the following beneficial effects:
according to the method, the process of routing the half holes is placed before the outer layer circuit is manufactured, so that the problem of nickel and gold burrs does not exist after the half holes are routed, etching can be completely performed during etching, namely, a tinning process, routing the half holes and alkaline etching are added before the outer layer circuit is manufactured, the burrs of the half holes are etched and removed under the condition of tin layer protection, the metallized half holes are manufactured, nickel and gold burrs are not left, and the product quality is guaranteed.
Detailed Description
The present invention will be further described and illustrated with reference to specific embodiments in order to more fully understand the technical content of the present invention; it is to be understood that the embodiments described below are only a few embodiments of the present invention, and not all embodiments; all other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The features, benefits and advantages of the present invention will become apparent to those skilled in the art from a reading of the present disclosure.
Examples
The manufacturing method of the circuit board shown in this embodiment includes a variegated ink solder mask process, and sequentially includes the following processing steps:
(1) cutting: the core board is cut according to the size of the jointed board of 520mm multiplied by 620mm, the thickness of the core board is 0.5mm, and the thickness of the copper layers on the two surfaces of the core board is 0.5 oz.
(2) Inner layer circuit manufacturing (negative film process): transferring the inner layer pattern, coating a photosensitive film with a vertical coating machine, controlling the film thickness of the photosensitive film to be 8 μm, completing the exposure of the inner layer circuit by using a full-automatic exposure machine and 5-6 exposure rulers (21 exposure rulers), and forming the inner layer circuit pattern after development; etching the inner layer, etching the exposed and developed core board to form an inner layer circuit, wherein the line width of the inner layer is measured to be 3 mil; and (4) inner layer AOI, and then, detecting defects of an inner layer circuit, such as open short circuit, circuit notch, circuit pinhole and the like, and performing defect scrapping treatment, wherein a defect-free product is discharged to the next flow.
(3) And (3) laminating: and (3) brown-oxidizing at the speed of brown-oxidizing according to the thickness of the bottom copper, sequentially laminating the core plate, the prepreg and the outer copper foil according to requirements, and then pressing the laminated plate by selecting proper lamination conditions according to the Tg of the plate to form the production plate.
(4) Drilling: according to the existing drilling technology, drilling processing is carried out on the production plate according to design requirements.
(5) Copper deposition: and (3) depositing a layer of thin copper on the plate surface and the hole wall by using an electroless copper plating method, and testing the backlight to 10 grades, wherein the thickness of the deposited copper in the hole is 0.5 mu m.
(6) Electroplating the whole plate: and performing full-plate electroplating for 120min at the current density of 18ASF to increase the thickness of the hole copper and the plate surface copper layer.
(7) Pattern electroplating: plating a tin layer with the thickness of 3-5 mu m on the board surface of the production board by a tin plating process in the pattern electroplating process as an anti-corrosion layer, and showing a metal burr generated when half holes are milled at the later stage.
(8) Routing half holes: and routing half holes at the through holes needing to be manufactured through a forming process.
(9) Alkaline etching: and removing the metal burrs in the hole and at the hole opening by alkaline etching, and then removing the tin layer.
(10) Manufacturing an outer layer circuit (negative film process): the method sequentially comprises the following steps:
a. pasting a first layer of film on the surface of the production board, adopting a full-automatic exposure machine and a line film, completing outer-layer line exposure by using 5-7 exposure rulers (21 exposure rulers), and forming an outer-layer line pattern on the production board through development;
b. performing chemical nickel-gold treatment on the production board so as to sequentially plate a nickel layer and a gold layer on the exposed outer layer circuit pattern;
c. the production board is adhered with a second layer of film on the basis of the first layer of film, and windowing is carried out on the position, corresponding to the position needing the electrogilding, of the outer layer of circuit pattern in the second layer of film;
d. performing local electro-gold treatment at the windowing position of the production plate, thickening the thickness of a gold layer at the windowing position, and then removing the film;
e. etching the production board to form an outer layer circuit;
f. and the outer layer AOI uses an automatic optical detection system to detect whether the outer layer circuit has the defects of open circuit, gap, incomplete etching, short circuit and the like by comparing with CAM data.
(11) Solder resist and silk screen printing of characters: after the solder resist ink is silk-screened on the surface of the multilayer board, the solder resist ink is cured into a solder resist layer through pre-curing, exposure, development and thermosetting treatment in sequence; specifically, the TOP surface solder resist ink is added with a UL mark on the TOP surface character, so that a protective layer which prevents bridging between circuits during welding and provides a permanent electrical environment and chemical corrosion resistance is coated on the circuits and the base materials which do not need welding, and the protective layer plays a role in beautifying the appearance.
(12) Surface treatment (nickel-gold deposition): the copper surface of the welding pad at the solder stop windowing position is communicated with a chemical principle, a nickel layer and a gold layer with certain required thickness are uniformly deposited, and the thickness of the nickel layer is as follows: 3-5 μm; the thickness of the gold layer is as follows: 0.05-0.1 μm.
(13) And electrical test: testing the electrical conduction performance of the finished board, wherein the board use testing method comprises the following steps: and (5) flying probe testing.
(14) And forming: according to the prior art and according to the design requirement, routing the shape, and obtaining the circuit board with the external tolerance of +/-0.05 mm.
(15) FQC: according to the customer acceptance standard and the inspection standard of my department, the appearance of the circuit board is inspected, if a defect exists, the circuit board is repaired in time, and the excellent quality control is guaranteed to be provided for the customer.
(16) FQA: and (5) measuring whether the appearance, the hole copper thickness, the dielectric layer thickness, the green oil thickness, the inner layer copper thickness and the like of the circuit board meet the requirements of customers or not again.
(17) And packaging: and hermetically packaging the circuit boards according to the packaging mode and the packaging quantity required by customers, putting a drying agent and a humidity card, and then delivering.
The technical solutions provided by the embodiments of the present invention are described in detail above, and the principles and embodiments of the present invention are explained herein by using specific examples, and the descriptions of the embodiments are only used to help understanding the principles of the embodiments of the present invention; meanwhile, for a person skilled in the art, according to the embodiments of the present invention, there may be variations in the specific implementation manners and application ranges, and in summary, the content of the present description should not be construed as a limitation to the present invention.
Claims (6)
1. A method for removing flash of a metallized half-hole of an electric gold plate is characterized by comprising the following steps:
s1, drilling holes on the production board, and then sequentially carrying out copper deposition and full-board electroplating to metalize the holes;
s2, plating a tin layer on the surface of the production board;
s3, routing half holes on the production board through a forming process;
s4, removing burrs in and at the hole by alkaline etching, and then removing the tin layer;
s5, pasting a film on the production board, and then sequentially exposing and developing to form an outer circuit pattern;
s6, performing electroless nickel-gold treatment on the production board;
s7, pasting a second layer of film on the production board, and windowing at the position corresponding to the position of the outer layer circuit pattern needing the electrogilding;
s8, carrying out local electrogilding treatment on the production board, and then stripping the film;
and S9, etching the production board to form an outer layer circuit.
2. The method of claim 1, wherein in step S1, the production board is a core board.
3. The method according to claim 1, wherein the production board is a multi-layer board formed by laminating an inner core board and an outer copper foil together by a prepreg, and the inner core board is formed with inner circuits before lamination in step S1.
4. The method of claim 1, wherein in step S2, the tin layer is plated on the production board by a pattern plating process.
5. The method of claim 4, wherein the tin layer has a thickness of 3-5 μm.
6. The method according to claim 5, further comprising the following steps after step S9:
and S10, sequentially manufacturing a solder mask layer and performing surface treatment and light synthesis on the production board to manufacture the electric gold plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111287027.XA CN114040598A (en) | 2021-11-02 | 2021-11-02 | Method for removing flash of metalized half hole of electric gold plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111287027.XA CN114040598A (en) | 2021-11-02 | 2021-11-02 | Method for removing flash of metalized half hole of electric gold plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114040598A true CN114040598A (en) | 2022-02-11 |
Family
ID=80135995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111287027.XA Pending CN114040598A (en) | 2021-11-02 | 2021-11-02 | Method for removing flash of metalized half hole of electric gold plate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114040598A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114599162A (en) * | 2022-03-25 | 2022-06-07 | 景旺电子科技(龙川)有限公司 | Circuit board burr processing method and circuit board |
| CN114867218A (en) * | 2022-03-28 | 2022-08-05 | 诚亿电子（嘉兴）有限公司 | Environment-friendly metallized semi-hole PCB preparation process |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61129853A (en) * | 1984-11-29 | 1986-06-17 | Nec Corp | Manufacture of hybrid ic |
| CN107041077A (en) * | 2017-04-27 | 2017-08-11 | 广东依顿电子科技股份有限公司 | A kind of circuit board producing method of turmeric and the golden compound base amount method of electricity |
| CN110248475A (en) * | 2019-06-10 | 2019-09-17 | 江门崇达电路技术有限公司 | A method of removal PCB metallized semi-pore burr |
-
2021
- 2021-11-02 CN CN202111287027.XA patent/CN114040598A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61129853A (en) * | 1984-11-29 | 1986-06-17 | Nec Corp | Manufacture of hybrid ic |
| CN107041077A (en) * | 2017-04-27 | 2017-08-11 | 广东依顿电子科技股份有限公司 | A kind of circuit board producing method of turmeric and the golden compound base amount method of electricity |
| CN110248475A (en) * | 2019-06-10 | 2019-09-17 | 江门崇达电路技术有限公司 | A method of removal PCB metallized semi-pore burr |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114599162A (en) * | 2022-03-25 | 2022-06-07 | 景旺电子科技(龙川)有限公司 | Circuit board burr processing method and circuit board |
| CN114867218A (en) * | 2022-03-28 | 2022-08-05 | 诚亿电子（嘉兴）有限公司 | Environment-friendly metallized semi-hole PCB preparation process |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110831336B (en) | Resin hole plugging method for large-aperture back drilling hole | |
| CN110351955B (en) | Manufacturing method of PCB with local electrical thick gold PAD | |
| CN111050484B (en) | Manufacturing method of ultra-precise circuit | |
| CN109195344B (en) | Method for enhancing dry film adhesion of fine circuit printed board | |
| CN110248473B (en) | Method for solving problem of small pressing hole of VIA-IN-PAD resin hole-plugged PCB (printed circuit board) | |
| CN108770238B (en) | Inner layer graph design method for improving copper pulling in drilling | |
| CN114040598A (en) | Method for removing flash of metalized half hole of electric gold plate | |
| CN110839319A (en) | Method for manufacturing high-precision impedance circuit | |
| CN110913601B (en) | Method for manufacturing solder mask translation film | |
| CN114158195B (en) | Method for manufacturing precise circuit with assistance of laser | |
| CN111867266A (en) | Circuit design method for preventing short circuit of isolated circuit of PCB | |
| CN110545633A (en) | Manufacturing method of circuit board of blind hole plug-in | |
| CN109548321B (en) | Manufacturing method of positive undercut PCB | |
| CN110121239B (en) | Manufacturing method of mechanical blind hole and half hole | |
| CN110785013A (en) | Manufacturing method for improving foaming and explosion of circuit board | |
| CN113660794A (en) | Manufacturing method of high-reliability printed circuit board | |
| CN111836485A (en) | Manufacturing process of twice stepped plate | |
| CN111050494A (en) | Manufacturing method of back drilling hole in circuit board | |
| CN113301734B (en) | Method for improving back drilling capability of high-multilayer circuit board | |
| CN109640520B (en) | Manufacturing method of buried resistance circuit board | |
| CN113784545A (en) | Method for preventing hole of resin plug from being broken by printed board | |
| CN112969287A (en) | Method for improving roughness of pore wall of PTFE (polytetrafluoroethylene) material | |
| CN112757380A (en) | Method for improving drilling efficiency of high-density micro holes of circuit board | |
| CN115038253B (en) | Method for manufacturing multiple types of PADs (PAD area data) on circuit board accurately and equally | |
| CN114630508A (en) | Manufacturing method of local thick-hole copper PCB |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20220211 |