CN113990270B

CN113990270B - Display device

Info

Publication number: CN113990270B
Application number: CN202111314316.4A
Authority: CN
Inventors: 姚晓慧; 傅华; 徐志达
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2021-11-08
Filing date: 2021-11-08
Publication date: 2023-03-17
Anticipated expiration: 2041-11-08
Also published as: CN113990270A; US20240038131A1; WO2023077557A1

Abstract

The application discloses display device includes: the circuit board, display panel, many clock signal lines and a plurality of ground resistance. Each clock signal line extends from the circuit board to a non-display area of the display panel. A plurality of ground resistors are provided on the circuit board. Each grounding resistor is connected with a corresponding clock signal line and is configured to reduce the voltage value of the high level of the clock signal. According to the display device, the grounding resistor connected with the clock signal lines is arranged on the circuit board of the display device to eliminate the load difference between the clock signal lines, and further the problem that unexpected black and white horizontal lines appear on a display picture is solved.

Description

Display device

Technical Field

The application relates to the technical field of display, in particular to a display device.

Background

As the display technology becomes mature, the conventional thin film transistor liquid crystal display (TFT-LCD) has been able to realize a narrow frame and an ultra-high resolution (e.g., 8K), and has been developed towards higher performance such as large size, high resolution, and high contrast.

However, the conventional ultra-high resolution display device is prone to various display defects, such as black and white horizontal lines, frame crosstalk, and image sticking. These undesirable defects seriously affect the display quality of the display device and the viewing experience of the customer. The black and white horizontal lines are generated due to a large in-plane load of the ultra-high resolution display device. Further, as the size of the display device increases, the in-plane load also increases. In particular, for clock signal lines that are designed to be driven row by row within the plane of the display device (e.g., the display surface of a display panel), there is a significant load difference between clock signal lines located in different rows. The display device displays a desired picture by controlling a plurality of pixels located in a plane to emit light. The difference in load between the clock signal lines causes the difference in potential after the pixels are charged, and thus the difference in brightness between different pixel rows. Therefore, there are dense black and white horizontal lines in the displayed picture.

Currently, one improvement to the above-described drawbacks is to adjust the in-plane load difference between the clock signal lines by changing the manufacturing process. However, this improvement cannot completely solve the load difference between the clock signal lines, and is liable to cause the problems of reduced yield, reduced throughput, and reduced efficiency of the product.

In view of the above, a need exists for a display device to solve the problems in the prior art.

Disclosure of Invention

To solve the above problems of the prior art, it is an object of the present application to provide a display device that can improve the problem that the display device displays an unexpected black and white horizontal line.

To achieve the above object, the present application provides a display device including: the circuit board is configured to output a clock signal, wherein the clock signal is a signal with high level and low level alternately appearing; the display panel is connected with the circuit board and comprises a display area and a non-display area; a plurality of clock signal lines configured to transfer the clock signals, wherein each of the clock signal lines extends from the circuit board to the non-display area of the display panel; a plurality of ground resistors disposed on the circuit board, wherein each ground resistor is connected to a corresponding clock signal line and configured to reduce a voltage value of the high level of the clock signal; a gate driver disposed in the non-display region of the display panel, connected to the clock signal line, and configured to generate a gate signal according to the clock signal that decreases the voltage value of the high level; and a gate line disposed in the display region of the display panel, connected to the gate driver, and configured to transmit the gate signal.

In some embodiments, the plurality of clock signal lines are sequentially arranged from the display region toward the non-display region of the display panel, and have different values from two of the ground resistances to which two of the clock signal lines are correspondingly connected.

In some embodiments, the display device includes an Mth clock signal line, an M-1 th clock signal line, and an M-2 th clock signal line, which are sequentially arranged; and the value of the ground resistance connected to the mth clock signal line is R (M), the value of the ground resistance connected to the M-1 th clock signal line is R (M-1), and the value of the ground resistance connected to the M-2 nd clock signal line is R (M-2), where R (M) < R (M-1) < R (M-2) or R (M) > R (M-1) > R (M-2).

In some embodiments, the display device includes a K-th clock signal line and a K-1-th clock signal line that are adjacent; and the numerical value of the grounding resistor connected with the Kth clock signal line is R (K), and the numerical value of the grounding resistor connected with the Kth clock signal line is R (K-1), wherein R (K) = R (K-1).

In some embodiments, the display device further includes a plurality of matching resistors disposed on the circuit board, and each matching resistor is connected to a corresponding clock signal line.

In some embodiments, each of the clock signal lines includes a first section disposed on the circuit board and a second section connected to the first section, the second section is disposed on the non-display region of the display panel, and each of the ground resistors is connected to the first section of the corresponding clock signal line.

In some embodiments, the circuit board comprises a first circuit board and a second circuit board; the first section of each clock signal line comprises a first subsection and a second subsection, the first subsection is arranged on the first circuit board, and the second subsection is arranged on the second circuit board; the second section of each clock signal line comprises a third subsection and a fourth subsection which are respectively arranged at two opposite sides of the display panel; the gate driver comprises a first gate driver and a second gate driver, the first gate driver is connected with the third subsection, the second gate driver is connected with the fourth subsection, and the first gate driver and the second gate driver are respectively connected with two opposite ends of the gate line; each of the ground resistors includes a first ground resistor disposed on the first circuit board and connected to the first subsection of the corresponding clock signal line, and a second ground resistor disposed on the second circuit board and connected to the second subsection of the corresponding clock signal line.

In some embodiments, the first ground resistance and the second ground resistance connected to the same clock signal line have the same value.

In some embodiments, the first ground resistance and the second ground resistance connected to the same clock signal line have different values.

In some embodiments, the same clock signal line, the RC circuit of the first ground resistor, the RC circuit of the second ground resistor, and the RC circuit of the corresponding gate line constitute an electronic circuit.

Compared with the prior art, the ground resistor and the matching resistor which are connected with the clock signal line are arranged on the circuit board of the display device, so that the circuit design of the clock signal line can be optimized, the load difference of the clock signal line can be eliminated, the problem that an unexpected black-and-white horizontal line appears on a display picture is solved, and the yield and the product quality of a product are greatly improved.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 shows a schematic diagram of a display device according to an embodiment of the present application.

Fig. 2 is a partial circuit block diagram of the display device of fig. 1.

Fig. 3 is a schematic diagram illustrating a wiring area of a non-display area of a display panel of the display device of fig. 1.

Fig. 4 shows a circuit diagram of a clock signal line according to an embodiment of the present application.

Fig. 5 shows a waveform diagram of a clock signal according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1, a schematic diagram of a display device 10 according to an embodiment of the present application is shown. The display device 10 includes a processor 100, a timing controller 110, a first circuit board 121, a second circuit board 122, a flexible circuit board 130, a display panel 140, a first gate driver 151, a second gate driver 152, and a source driver. The timing controller 110 is connected to the processor 100. The first and

second circuit boards

121 and 122 are connected to the timing controller 110, and are connected to the display panel 140 through the corresponding flexible circuit boards 130, respectively. The display panel 140 includes a display area 141 and a non-display area 142 surrounding the display area 141. The first and

second gate drivers

151 and 152 are disposed at opposite sides of the display panel 140, respectively, and disposed in the non-display region 142 between the outer circumference 143 of the display panel 140 and the display region 141. The source driver may be integrated in the first circuit board 121 and the second circuit board 122, integrated in the flexible circuit board 130, or disposed in the non-display region 142 of the display panel 140, without being limited thereto. The display area 141 of the display panel 140 includes a plurality of gate lines GL, a plurality of data lines and a plurality of pixels, wherein each gate line GL may drive at least one row of pixels. The first and

second gate drivers

151 and 152 are connected to the gate lines GL, and are connected to opposite ends of the gate lines GL, respectively. The source driver is connected to the data line.

Referring to fig. 1 and 2, fig. 2 is a partial circuit block diagram of the display device of fig. 1. The display device 10 also includes a voltage generation unit 101 and a timing generation unit 123. In the present embodiment, the voltage generating unit 101 may be disposed in the processor 100, and the timing generating unit 123 may be disposed in the first circuit board 121 and the second circuit board 122. The timing generation unit 123 is connected to the voltage generation unit 101 and the timing controller 110. The timing generation unit 123 is connected to the first gate driver 151 and the second gate driver 152 through a plurality of signal lines, such as a clock signal line CLK, a scan start signal line, a scan sequence control signal line, and the like. In the present embodiment, the signal lines between the timing generation unit 123 of the first circuit board 121 and the first gate driver 151 include 12 clock signal lines (CLK 1 to CLK 12), and the signal lines between the timing generation unit 123 of the second circuit board 122 and the second gate driver 152 also include 12 clock signal lines (CLK 1 to CLK 12). It should be understood that other numbers of clock signal lines CLK may be employed in other embodiments, without limitation.

As shown in fig. 1 and 2, in the present embodiment, the processor 100 outputs driving signals such as an image signal, an enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. The timing controller 110 receives the driving signals from the processor 100. The timing controller 110 generates a data control signal based on the driving signal. The source driver generates a data signal according to the data control signal and outputs the data signal to a corresponding data line. Furthermore, the voltage generating unit 101 provides a voltage to the timing generating unit 123. The timing controller 110 generates a control signal based on the driving signal. The timing generation unit 123 generates a gate control signal including a clock signal according to the voltage and the control signal, and controls the corresponding clock signal line CLK to transfer the clock signal to the first gate driver 151 and/or the second gate driver 152. The first and

second gate drivers

151 and 152 generate gate signals according to the gate control signals and output the gate signals to corresponding gate lines. The pixels in the display panel 140 display an image in response to the data signals and the gate signals.

As shown in fig. 1, the non-display area 142 of the display panel 140 includes a first wiring area 1421 and a second wiring area 1422. The first wiring region 1421 is located between the first gate driver 151 and the outer periphery 143 of the display panel 140, and the second wiring region 1422 is located between the second gate driver 152 and the outer periphery 143 of the display panel 140.

As shown in FIGS. 1 and 2, each clock signal line CLK extends from the circuit boards 121/122 to the routing regions 1421/1422 of the non-display region 142 of the display panel 140. Specifically, the same clock signal line CLK (e.g., the first clock signal line CLK 1) includes a first section disposed on the circuit boards 121/122 and a second section disposed on the display panel 140. Since the dual gate driving technique is adopted in the present embodiment, the same clock signal line CLK extends on two opposite sides of the display device 10.

As shown in fig. 1, in one clock signal line CLK, a first section of the clock signal line CLK includes a first subsection 161 located at the first circuit board 121 and a second subsection 162 located at the second circuit board 122. The second segment of the clock signal line CLK includes the third subsegment 163 at the first wiring region 1421 and the fourth subsegment 164 at the second wiring region 1422. The first subsection 161 and the second subsection 162 receive clock signals generated based on the same signal of the timing controller 110, i.e., the first subsection 161 and the second subsection 162 are used to deliver the same clock signals. The first subsection 161 is connected to the third subsection 163 and the second subsection 162 is connected to the fourth subsection 164. The third subsection 163 is connected to the first gate driver 151, and the fourth subsection 164 is connected to the second gate driver 152. The first gate driver 151 and the second gate driver 152 control the same gate line GL based on the same clock signal.

It should be noted that the different clock signal lines CLK may have a load difference due to the panel process difference, which may affect the clock signal transmitted to the display panel 140. Secondly, the process differences of the circuit boards 121/122, the design differences (such as structure design, trace layout design, etc.) of the display panel 140 and the circuit boards 121/122 also cause the aforementioned load differences. For example, referring to fig. 3, a schematic diagram of the wiring regions 1421/1422 of the non-display region 142 of the display panel 140 of the display device of fig. 1 is shown. In the

wiring areas

1421 and 1422 of the display panel 140, the common electrode lines CF _ COM and DBS (data line bm less) of the color film substrate, the twelfth clock signal line CLK12 to the first clock signal line CLK1, the second pull-down circuit control signal line LC2, the first pull-down circuit control signal line LC1, and the reference potential line VSS are sequentially arranged in the direction from the non-display area 142 (or the outer periphery 143) of the display panel 140 toward the display area 141. In the display panel 140, the clock signal of each clock signal line CLK is coupled to the peripheral signal lines. Due to the influence of the wiring design, different clock signals generate different coupling quantities, and therefore different loads are generated among different clock signal lines. In order to improve the load difference between the clock signal lines, the display device of the present application further includes a ground resistor connected to the clock signal lines, as described in detail below.

As shown in fig. 1 and 2, a ground resistor R is provided on the circuit boards 121/122 and connected to the first segment of the corresponding clock signal line CLK. Specifically, please refer to fig. 4, which shows a circuit diagram of a clock signal line according to an embodiment of the present application. The ground resistor 1 connected to the same clock signal line CLK includes a first ground resistor RL1 and a second ground resistor RR1. The first ground resistance RL1 is disposed on the first circuit board 121 and connected to the first subsection 161 of the clock signal line CLK. The second ground resistor RR1 is disposed on the second circuit board 122 and connected to the second segment 162 of the clock signal line CLK. The third sub-segment 163 of the clock signal line CLK has a first load (including the first load resistor RL2 and the first load capacitor CL 2) due to process variations and routing layout effects. Similarly, the fourth subsection 164 of the clock signal line CLK has a second load (including a second load resistor RR2 and a second load capacitor CR 2). The gate line GL driven based on the same clock signal also has a third load (including a third load resistor R3 and a third load capacitor C3). The same clock signal line CLK, the RC circuits of the first ground resistor RL1 and the second ground resistor RR1, and the RC circuit of the corresponding gate line GL form an electronic circuit. The current of the clock signal line CLK on the display panel is I1, the current of the clock signal line CLK on the first circuit board 121 is I2, and the current of the clock signal line CLK on the second circuit board 122 is I3. The total current I of the clock signal line CLK is I1+ I2+ I3.

In this embodiment, by setting the ground resistance R, the voltage drop of the clock signal can be enhanced, so that the voltage value of the high level of the clock signal is reduced. Specifically, please refer to fig. 5, which shows a waveform diagram of a clock signal according to an embodiment of the present application. The timing generation unit 123 generates an initial clock signal W1 according to the received voltage and the control signal of the timing controller 110, and transfers the initial clock signal W1 through a corresponding clock signal line CLK. The initial clock signal W1 is a signal in which a high level VGH and a low level VGL alternately appear. The ground resistor R connected to the clock signal line CLK may reduce a voltage value of a high level of the clock signal to obtain the adjusted clock signal W2. Specifically, the total resistance of the circuit is reduced by the ground resistance R, and the total current I is increased, so that the voltage drop of the clock signal on the circuit board is increased, thereby reducing the voltage value of the high level of the clock signal input to the display panel. In some embodiments, the difference Δ V between the high level VGH of the initial clock signal W1 and the high level VGH' of the adjusted clock signal W2 is about 0.375V. According to the feed-through effect, when the gate line of the Nth row is turned on, the gate line of the N-1 th row is turned off. At this time, the pixel electrode of the N-1 th row reduces the driving voltage due to the influence of the parasitic capacitance, so that the brightness of the pixel of the N-1 th row becomes dark. In the present application, the ground resistor R is provided to reduce the driving voltage drop caused by the feedthrough effect, thereby improving the brightness of the corresponding dark-area pixel. Therefore, the problem of black and white horizontal lines due to a load difference between the clock signal lines CLK is eliminated, thereby improving picture quality.

In the present embodiment, the ground resistor R is disposed on the circuit boards 121/122, not on the wiring regions 1421/1422 of the display panel 140. Therefore, the ground resistor R can be prevented from occupying the wiring space of the display panel 140, and the ground resistor R can be prevented from increasing the load of the display panel 140.

It should be noted that the value of the ground resistance R is determined according to the wiring position of the clock signal line connected thereto. In the present embodiment, the value of the ground resistor R is between 1 and 500 kilo-ohms (K Ω) in consideration of the wiring position difference of different clock signal lines. It should be understood that the value of the ground resistance R outside this range may affect the normal display of the panel or may not contribute much to the elimination of black and white horizontal lines. If the value of the resistor is too large (e.g., greater than 500K Ω), the circuit principle will make the clock signal in the display panel less affected, and the improvement effect of eliminating black and white horizontal lines will not be obtained. On the other hand, if the value of the resistor is too small (e.g., less than 1K Ω), the clock signal lines in the display panel are short-circuited due to the circuit principle, thereby affecting the display.

In some embodiments, the display device 10 includes a plurality of clock signal lines sequentially arranged from the non-display area 142 of the display panel 140 toward the display area 141. By designing the values of two ground resistors correspondingly connected to at least two of the clock signal lines to be different, the load difference caused by the different wiring positions of the clock signal lines can be eliminated. For example, the display device 10 includes N clock signal lines sequentially arranged from the outer periphery 143 of the display panel 140 toward the display area 141. The value of the ground resistance connected to the nth clock signal line is R (N), and the value of the ground resistance connected to the first clock signal line is R (1), where R (N) ≠ R (1).

In some embodiments, the display device 10 includes N clock signal lines sequentially arranged from the outer periphery 143 of the display panel 140 toward the display area 141. Since the wiring difference between adjacent clock signal lines is small, the numerical values of two adjacent ground resistors R connected corresponding to two adjacent ones of the clock signal lines are designed to be the same. For example, the display device 10 includes adjacent Kth and K-1 clock signal lines, where N ≦ K <1. The value of the ground resistance connected to the K-th clock signal line is R (K), and the value of the ground resistance connected to the K-1 th clock signal line is R (K-1), where R (K) = R (K-1). It should be noted that R (K) ≠ R (N) or R (K) ≠ R (1). By adopting the design of the same resistance value for part of the grounding resistors R, the manufacturing complexity of the circuit boards 121/122 can be reduced, and the yield and the productivity can be improved.

In some embodiments, the display device 10 includes a plurality of clock signal lines sequentially arranged from the outer periphery 143 of the display panel 140 toward the display area 141. Since different clock signal lines have different process differences and different clock signals have different coupling values due to the stage transmission relationship, the values of the grounding resistors R connected corresponding to the plurality of clock signal lines may be designed to be entirely or mostly different. In response to the difference in the values of the ground resistance R, the values may adopt an ordered or unordered arrangement scheme, wherein the ordered scheme includes a gradual change. Specifically, the values of the ground resistances R gradually change, such as increase or decrease, from the outer periphery toward the display region. For example, the display device 10 includes N clock signal lines sequentially arranged from the outer periphery 143 of the display panel 140 toward the display area 141, including an Mth clock signal line, an M-1 th clock signal line, and an M-2 th clock signal line sequentially arranged, and N ≦ M <1. The value of the ground resistance connected to the Mth clock signal line is R (M), the value of the ground resistance connected to the M-1 th clock signal line is R (M-1), and the value of the ground resistance connected to the M-2 th clock signal line is R (M-2), where R (M) < R (M-1) < R (M-2) or R (M) > R (M-1) > R (M-2). In some embodiments, the ground resistors R have an arithmetic progression with a tolerance of 1K Ω, such as 1K Ω, 2K Ω, 3K Ω, 4K Ω, 5K Ω, 6K Ω, 7K Ω, 8K Ω, 9K Ω, 10K Ω, 11K Ω, and 12K Ω connected to the first to twelfth clock signal lines CLK1 to CLK12, respectively. All or most of the grounding resistors R adopt the design of different resistance values, and the effect of improving black and white horizontal lines is better.

In some embodiments, the first ground resistance RL1 and the second ground resistance RR1 of the ground resistance R connected to the same clock signal line CLK may be designed to be the same (the value of the ground resistance R is equal to the first ground resistance RL1 and equal to the second ground resistance RR1 as described above). The first grounding resistor RL1 and the second grounding resistor RR1 connected with the same clock signal line CLK are designed to have the same resistance value, so that the manufacturing complexity is reduced, and the yield and the capacity are improved.

In some embodiments, the first ground resistor RL1 and the second ground resistor RR1 of the ground resistor R connected to the same clock signal line CLK may be designed differently in consideration of process variations and wiring variations that may exist on both sides of the display device 10 (including a circuit board and a display panel) in the same clock signal line CLK. By means of the design, the load difference of the same clock signal line on different sides of the display device can be effectively improved.

As shown in fig. 2 and 4, the display device 10 further includes a plurality of matching resistors R _ PCB disposed on the circuit boards 121/122, and each matching resistor R _ PCB is connected in series with the first segment of the corresponding clock signal line CLK. Specifically, the matching resistor R _ PCB connected to the same clock signal line CLK includes a first matching resistor RL _ PCB and a second matching resistor RR _ PCB. The first matching resistor RL _ PCB is disposed on the first circuit board 121 and is connected to the first subsection 161 of the clock signal line CLK. The second matching resistor RR _ PCB is disposed on the second circuit board 122 and connected to the second subsection 162 of the clock signal line CLK.

In the manufacturing process of the display device 10, the ground resistor R is first set, and then the matching resistor R _ PCB is set. Specifically, a lighting test is performed on the display device 10 to confirm the picture quality. If the horizontal dense lines appear in the frame, all clock signals are measured to determine the load difference between the clock signal lines. Then, the voltage value corresponding to the high level of the clock signal is reduced by the design scheme of the grounding resistor R. Accordingly, a load difference between clock signal lines is eliminated, thereby eliminating black and white horizontal lines and improving display quality. Next, the resistances of the clock signal lines CLK on the circuit boards 121/122 are referenced to identify the clock signal lines CLK causing the dark lines, and the clock signal lines CLK are string resistance-matched. Therefore, the problem of black and white horizontal lines can be further solved by the setting of the matching resistor R _ PCB. Therefore, through the arrangement of the grounding resistor R and the matching resistor R _ PCB, the charging difference of the clock signals of different clock signal lines CLK to the pixel rows can be effectively reduced, so that the brightness uniformity of each pixel row is improved, the problem of black and white horizontal lines is eliminated, and the picture quality is improved.

The above embodiments are explained with respect to a display device using a dual gate driving technique. It should be understood that the scheme of the present application is also applicable to a display device using single gate driving technology, and the principle and design scheme of the ground resistance and the matching resistance are similar to those of the display device using dual gate driving technology, which are not described herein again.

In summary, the ground resistor and the matching resistor connected with the clock signal line are arranged on the circuit board of the display device, so that the circuit design of the clock signal line can be optimized, the load difference of the clock signal line can be eliminated, the problem that an unexpected black-and-white horizontal line appears on a display picture can be solved, and the yield and the product quality of a product can be greatly improved.

A display device provided in an embodiment of the present application is described in detail above. The principles and implementations of the present application are described herein using specific examples. The above description of the embodiments is only for assisting understanding of the technical solutions of the present application and the core ideas thereof. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display device, characterized in that the display device comprises:

the circuit board is configured to output a clock signal, wherein the clock signal is a signal with high level and low level which appear alternately;

the display panel is connected with the circuit board and comprises a display area and a non-display area;

a plurality of clock signal lines configured to transfer the clock signals, wherein each of the clock signal lines extends from the circuit board to the non-display area of the display panel;

a plurality of ground resistors disposed on the circuit board, wherein one end of each ground resistor is connected to the corresponding clock signal line, and the other end of each ground resistor is grounded, and configured to reduce a total resistance corresponding to the clock signal and increase a total current flowing through the clock signal, so as to reduce a voltage value of the high level of the clock signal;

a gate driver disposed in the non-display region of the display panel, connected to the clock signal line, and configured to generate a gate signal according to the clock signal that decreases the voltage value of the high level; and

and a gate line disposed in the display region of the display panel, connected to the gate driver, and configured to transmit the gate signal.

2. The display device according to claim 1, wherein the plurality of clock signal lines are arranged in order from the display region of the display panel toward the non-display region, and are different in value from two of the ground resistances to which two of the clock signal lines are correspondingly connected.

3. The display device according to claim 1, wherein the display device includes an mth clock signal line, an M-1 clock signal line, and an M-2 clock signal line arranged in this order; and

the ground resistance connected to the Mth clock signal line has a value of R (M), the ground resistance connected to the M-1 th clock signal line has a value of R (M-1), and the ground resistance connected to the M-2 th clock signal line has a value of R (M-2), wherein R (M) < R (M-1) < R (M-2) or R (M) > R (M-1) > R (M-2).

4. The display device according to claim 1, wherein the display device includes a K-th clock signal line and a K-1-th clock signal line adjacent to each other; and

the numerical value of the grounding resistor connected with the Kth clock signal line is R (K), and the numerical value of the grounding resistor connected with the Kth clock signal line is R (K-1), wherein R (K) = R (K-1).

5. The display device according to claim 1, wherein the display device further comprises a plurality of matching resistors provided on the circuit board, and each of the matching resistors is connected to a corresponding one of the clock signal lines.

6. The display device according to claim 1, wherein each of the clock signal lines includes a first segment and a second segment connected to the first segment, the first segment is provided on the circuit board, the second segment is provided in the non-display region of the display panel, and each of the ground resistors is connected to the first segment of the corresponding clock signal line.

7. The display device of claim 6, wherein the circuit board comprises a first circuit board and a second circuit board;

the first section of each clock signal line comprises a first subsection and a second subsection, the first subsection is arranged on the first circuit board, and the second subsection is arranged on the second circuit board;

the second section of each clock signal line comprises a third subsection and a fourth subsection which are respectively arranged at two opposite sides of the display panel;

the gate driver comprises a first gate driver and a second gate driver, the first gate driver is connected with the third subsection, the second gate driver is connected with the fourth subsection, and the first gate driver and the second gate driver are respectively connected with two opposite ends of the gate line;

each of the ground resistors includes a first ground resistor disposed on the first circuit board and connected to the first subsection of the corresponding clock signal line, and a second ground resistor disposed on the second circuit board and connected to the second subsection of the corresponding clock signal line.

8. The display device according to claim 7, wherein the first ground resistance and the second ground resistance connected to the same clock signal line have the same value.

9. The display device according to claim 7, wherein the first ground resistance and the second ground resistance connected to the same clock signal line have different values.

10. The display device according to claim 7, wherein the same clock signal line constitutes an electronic circuit with the RC circuit of the first ground resistance, the second ground resistance, and the RC circuit of the corresponding gate line.