JPH09311665A - Driving circuit of liquid crystal display apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen the electric consumption in an optimized way by providing shift resistors in N stages in total number divided into L blocks, shift resistors for shift clock masks in stages L, a means to mask a clock, and specifying the L value. SOLUTION: Corresponding to the cycle of clock signal MCLK, mask signals M(1)-M(L) are successively sent out from respective stages of shift resistor MSR for shift clock mask signals. Clock signals CLK for shift resistors SR in N stages are divided corresponding to the number L of the stages of the shift resistors MSR for shift clock mask signals, masked by respective mask signals M(1)-M(L), and sent to the shift resistor SR as clock signals LCLK (1)-LCLK(L). The number L is set to be an integer near the value m obtained from an equation m=<3> √ (N<2> /2), where<3> √ stands for a cube root. Consequently, the electric power consumption of a driving circuit can be lessened to the minimum limit.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a driving circuit for a liquid crystal display.

[0002]

2. Description of the Related Art Conventionally, a drive circuit of a liquid crystal display device generally inputs a display signal and sequentially outputs the display signal to liquid crystal drive elements forming one row. It has a built-in circuit. The shift clock input to the shift register becomes faster in proportion to the number of pixels of the display device, and the power consumed in the shift register becomes larger in proportion to the shift clock frequency.

The number of pixels of liquid crystal display devices has been increased in order to improve the image quality of the display devices, and accordingly, the power consumption of the drive circuit including the shift register has increased.

As a method of suppressing the power consumption which is increasing in relation to the operation of the shift register, a method in which the clock input to the shift register is partially stopped is disclosed in Japanese Patent Laid-Open No. 58-75196. It is disclosed in the gazette and the like.

[0005]

However, in such a conventional method, the shift register is operated by detecting the input of the mask pulse, and moreover, since it is the mask of the driver IC unit, it is not always consumed. The power is not the lowest.

Further, in order to perform the shift register operation after detecting the mask pulse as in this conventional method, an operation faster than the clock signal is required, and c-Si is required.
Although it can be applied to a (single crystal silicon) driver IC, it cannot be applied to a circuit such as p-Si (polycrystalline silicon) having a low element performance and a large delay.

It is an object of the present invention to optimally reduce power consumption in a drive circuit for such a liquid crystal display device.

[0008]

In order to achieve this object, a drive circuit of a liquid crystal display device of the present invention uses L and N as integers and a timing for sequentially outputting signals to a signal line to a liquid crystal element. With a total of N stages of the first shift register divided into L blocks, a second shift register for the L stages of shift clock mask signals, and an output of the second shift register. Means for masking the clock of the first shift register, wherein L is the following (Equation 1)

[0009]

(Equation 3)

It is configured to be an integer near the value m obtained by. With such a configuration, it is possible to reduce the power consumption of the drive circuit by reducing the power consumption of the N-stage shift register to 1 / L. Moreover, by setting the value of L to be an integer near the value m, the power consumption can be minimized for the reason described below.

[0011]

The present invention according to claim 1 is a liquid crystal display device in which liquid crystal elements are arranged in a matrix, wherein L and N are integers, and signals are sequentially supplied to signal lines to the liquid crystal elements. A total of N stages of first shift registers divided into L blocks, a second shift register for L stages of shift clock mask signals, and a second shift register for generating timing for outputting. Means for masking the clock of the first shift register with the output of the shift register, wherein L is the following (Equation 1)

[0012]

(Equation 4)

It is characterized in that it is an integer in the vicinity of the value m obtained in. With this configuration, the power consumption of the drive circuit can be minimized as will be described later.

According to a second aspect of the present invention, in a liquid crystal display device in which liquid crystal elements are arranged in a matrix, L, N
Is an integer, the timing for sequentially outputting signals to the signal line to the liquid crystal element is generated by (2L−
1) A total of N stages of first shift registers divided into blocks and a second stage of L stages of shift clock mask signals.
Shift register, an L-stage third shift register operating in a phase shifted from the second shift register by a half cycle, each output of the second shift register and each output of the third shift register. Means for masking the clock of the first shift register with the logical sum of

[0015]

(Equation 5) It is characterized in that it is an integer in the vicinity of the value n obtained in.
With such a configuration, the power consumption of the drive circuit can be minimized as will be described later.

According to a third aspect of the present invention, the circuit according to the first or second aspect is built in a liquid crystal panel formed of a-Si (amorphous silicon) or p-Si (polycrystalline silicon). Is. According to such a configuration, there is an effect that the power consumption can be reduced without being limited by the number of stages of the shift register incorporated in the driver IC.

According to a fourth aspect of the present invention, there is provided a configuration including a means for generating a clock signal of the shift register for the shift clock mask signal of the L stage from the input clock signal for the shift register of the N stages. Such a structure not only has the effect of reducing power consumption, but also has an effect of suppressing an increase in the number of signal lines of the external interface.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 1 shows a configuration diagram of a drive circuit according to a first embodiment of the present invention. In this FIG.
SR is an N-stage shift register incorporated in the liquid crystal display drive circuit. MSR is a shift clock mask signal shift register, which is provided with L stages and has an initial value MAS of the clock signal MCLK and the mask signal.
K_PULSE is input. Outputs M (1), M (2) to M of each stage of the mask signal shift register MSR
(L) becomes a mask signal of the clock signal of the shift register SR. CLK is a clock signal of the shift register SR before being masked by these mask signals. The clock signals NCLK (1) to NCLK are obtained by masking the clock signal CLK with the mask signals M (1) to M (L).
It is input to the shift register SR as CLK (L).
PULSE is the initial value of the output of the shift register SR, OU
T (1) to OUT (N) are outputs of the shift register SR.

Next, the operation of the drive circuit shown in FIG. 1 will be described with reference to FIG. Mask signals M (1) to M (L) are sequentially output from each stage of the shift clock mask signal shift register MSR in accordance with the cycle of the clock signal MCLK. The clock signal CLK for the shift register SR is divided corresponding to the number of stages L of the shift clock mask signal shift register MSR, and is masked by the mask signals of M (1) to M (L) to obtain the clock signal LCLK.
(1) to LCLK (L) are input to the shift register SR. Since the shift register built in the drive circuit of the liquid crystal display device only sends one pulse in sequence within a constant period, even if the clock signal is partially stopped by the mask signal, there is no problem in operation.

Next, the shift register S in this configuration
R and shift clock mask signal shift register MSR
Calculate the power consumption with. Generally, the power consumption P when driving a capacitive load can be calculated by (Equation 3), where C is the load capacitance, f is the operating frequency, and V is the power supply voltage.

[0021]

(Equation 6) Here, in the circuit for each stage of the shift register circuit, it can be assumed that the load capacitance C is the same in both the shift register SR and the shift clock mask signal shift register MSR. Further, it can be assumed that the power supply voltage V is the same in the same chip, and the operating frequency f is proportional to the number of stages of each shift register. When the frequencies of the shift register SR and the shift clock mask signal shift register MSR are fN and fL, respectively, and these are represented by N and L, fN =
a · N and fL = a · L.

From this, the power consumption PSR1 and PMSR1 per stage in the shift register SR and the shift clock mask signal shift register MSR are respectively PSR1 = C.V.V.a.N PMSR1 = C. It becomes V ・ V ・ a ・ L. Further, the number of stages of registers operating simultaneously in the shift register SR and the shift clock mask signal shift register MSR is N / L stages in SR and L stages in MSR.
Since it is a stage, the power consumption PSR and PMSR of SR and MSR are respectively PSR = C · V · V · a · N · N / L PMSR = C · V · V · a · L·L. Therefore, when the sum P of the power consumptions of the shift register SR and the shift clock mask signal shift register MSR is expressed as a function of the number of stages L of the mask signal shift register, P = a · C · V · V (L·L + N · N / L). The electric power P is differentiated by L, and the minimum value of the electric power P is when the differential expression becomes 0.

In this way, L when the power P becomes minimum
When the value of is calculated, this value becomes m in (Equation 1), and the power P
The value of is (Equation 4).

[0024]

(Equation 7) Specifically, when the number of stages N of the shift register SR is 160, L is about 23, and when N is 80, L is about 15.

In this method, the clock signal NCLK is
If the delay of the switching portion between (x) and NCLK (x + 1) is shorter than one half of the cycle of the clock signal CLK, the circuit operates, and a circuit with low element performance such as p-Si can be realized. is there.

FIG. 3 is a block diagram of a drive circuit according to the second embodiment of the present invention. In FIG. 3, SR
Is an N-stage shift register incorporated in the drive circuit of the liquid crystal display device. MSR1 is an L-stage first shift clock mask signal shift register, and MSR2 is also an L-stage second shift clock mask signal shift register. Thus, a pair of shift registers MSR1, MS
R2 is provided. The shift register MSR1 has
The clock signal MCLK1 and this shift register MSR
The initial value MASK_P of the first mask signal which is the output of 1
ULSE1 is input. Also shift register MSR
2 includes the clock signal MCLK2 and the initial value MA of the second mask signal which is the output of the shift register MSR2.
SK_PULSE2 is input. M11, M12 ~
M1L is the above-mentioned first mask signal, M21, M22 to M22.
2L is a second mask signal.

M (1), M (2) to M (2L-1) are
The logical sum of the first mask signals M11, M12 to M1L and the second mask signals M21, M22 to M2L functions as a signal for masking the shift clock signal of the shift register SR. CLK is the mask signal M (1),
It is a clock signal of the shift register SR before being masked by M (2) to M (2L-1). This clock signal CL
The clock signals NCLK (1) to NCLK are obtained by masking K with the mask signals M (1) and M (2) to M (2L-1).
It is input to the shift register SR as CLK (2L-1). PULSE is an initial value of the output of the shift register SR, and OUT (1) to OUT (N) are the shift register SR.
Is the output of

Next, the operation of the drive circuit shown in FIG. 3 will be described with reference to FIG. The clock signals MCLK1 and MCLK2 have the same frequency but are deviated from each other by a half cycle. The initial value MASK_PULSE2 of the mask signal is 2 of the clock signal with respect to the initial value MASK_PULSE1.
It is input to the shift register MSR2 with a delay of one-half cycle time. In this way, the clock signals MCLK1 and MC
LK2 and mask signal initial value MASK_PULSE1,
By inputting MASK_PULSE2, shift clock mask signal shift registers MSR1 and MSR2
The outputs M11 to M1L and M21 to M2L are output by being overlapped by one half cycle of the clock signals MCLK1 and MCLK2, respectively.

As shown in FIG. 3, the outputs M11 to M11 of the shift clock mask signal shift registers MSR1 and MSR2.
Logical sum of M1L and M21 to M2L M (1) to M (2L
-1) is used as a mask signal for the clock signal of the shift register SR, in the clock signals NCLK (1) to NCLK (2L-1) of the shift register SR, two consecutive clock signal blocks are simultaneously blocked. There is a period for outputting the clock signal. Therefore, in the configuration of FIG. 1, even when the clock signal may be interrupted due to a delay of the constituent circuit, the circuit of FIG. 3 can continuously supply the clock signal.

Power consumption PSR1, PMSR11, PMSR2 per stage of shift register SR and mask signal shift registers MSR1, MSR2 in this configuration.
1, the operating frequencies fN and fL are fN = a.N fL = a.L, respectively, and PSR1 = C.V.V.a.N PMSR11 = C.V.V.a.L PMSR21 = C.V. It becomes V ・ a ・ L. Further, since the number of stages operating simultaneously in the shift register SR and the mask signal shift registers MSR1 and MSR2 is 3N / 2L stages, L stages, and L stages, the shift register SR and the mask signal shift Power consumption PSR and PMSR with registers MSR1 and MSR2
1 、 Calculating PMSR2, PSR = C ・ V ・ V ・ a ・ N ・ 3N / 2L PMSR1 = C ・ V ・ V ・ a ・ L ・ L PMSR2 = C ・ V ・ V ・ a ・ L ・ L . Therefore, when the sum P of the power consumptions of the shift register SR and the mask signal shift registers MSR1 and MSR2 is expressed as a function of the number of stages L of the mask signal shift register, only one line or two lines of the clock signal at the start end and the end are output. Ignoring the non-existing period as an error, P = a ・ C ・ V ・ V (2 ・ L ・ L + 3 ・ N ・ N / L /
2) When this power P is differentiated by L and the value of L when the minimum power is obtained, this value becomes n in (Equation 2). Specifically, when the number of stages N of the shift register SR is 160, L is about 21, and when N is 80, L is about 13. Also in the second embodiment, as in the first embodiment,
A circuit having low element performance and a long delay can be realized, and a delay within one cycle of the clock signal NCLK causes normal operation.

FIG. 5 is a block diagram of a drive circuit according to the third embodiment of the present invention. In FIG. 5, CLK
_GEN is a circuit that generates a clock signal MCLK having a different frequency based on the input clock signal CLK. In FIG. 5, the other components are the same as those of the first embodiment, that is, those shown in FIG.

By incorporating a circuit for generating a clock signal like that shown in FIG. 5, it is possible to eliminate the clock signal MCLK from the input signal of the external interface. Further, by incorporating this circuit in the structure shown in FIG. 3, it is possible to eliminate the two input signals of the clock signals MCLK1 and MCLK2.

[0033]

As described above, according to the present invention, the power consumption of the shift register portion of the drive circuit of the liquid crystal display device can be minimized.

The present invention can also be applied to a liquid crystal display device such as p-Si which has a low element performance and a long circuit delay time. Furthermore, according to the present invention, by including the clock signal generation circuit, it is possible to suppress an increase in the number of external interfaces for reducing power consumption.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a drive circuit of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the operation of the drive circuit configured as shown in FIG.

FIG. 3 is a configuration diagram of a drive circuit of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 4 is a timing chart of the operation of the drive circuit configured as shown in FIG.

FIG. 5 is a configuration diagram of a drive circuit of a liquid crystal display device according to a third embodiment of the present invention.

[Explanation of symbols]

 SR shift register MSR shift clock mask signal shift register L number of stages N number of stages

Claims (4)

[Claims] 1. In a liquid crystal display device in which liquid crystal elements are arranged in a matrix, L and N are integers, and L is generated so as to generate a timing for sequentially outputting a signal to a signal line to the liquid crystal element. Total N divided into blocks
Stage first shift register, L stage shift clock mask signal second shift register, and means for masking the first shift register clock with the output of the second shift register. , L is the following (Equation 1) A driving circuit for a liquid crystal display device, wherein the driving circuit is an integer close to the value m obtained in (1). 2. In a liquid crystal display device in which liquid crystal elements are arranged in a matrix, L and N are integers so as to generate timings for sequentially outputting signals to signal lines to the liquid crystal elements. 2L-1) a total of N stages of first shift registers divided into blocks, a second shift register for L stages of shift clock mask signals, and a phase shifted by a half cycle from the second shift register. L that works with
A third shift register of stages, and means for masking the clock of the first shift register with the logical sum of each output of the second shift register and each output of the third shift register, Where L is the following (Equation 2) A driving circuit for a liquid crystal display device, wherein the driving circuit is an integer close to the value n obtained in (1). 3. The drive circuit for a liquid crystal display device according to claim 1, which is incorporated in a liquid crystal panel made of amorphous silicon or polycrystalline silicon. 4. A unit for generating a clock signal for an L-stage shift clock mask signal shift register from an N-stage shift register input clock signal, according to any one of claims 1 to 3. A drive circuit for the liquid crystal display device according to the item.