JP3222882B2 - Driver driving method and display device for driving display panel - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device using a dot matrix display panel and a driver driving method for the display device of the display panel.

[Prior Art] A conventional liquid crystal display device includes a liquid crystal panel controller including a liquid crystal panel having a matrix-like liquid crystal panel, a common driver for driving a common side, and a column driver for driving a column. A display synchronizing signal for displaying and driving the matrix liquid crystal panel and display data are output, and the display of the liquid crystal panel is thereby driven. This conventional liquid crystal display device is shown in FIG. 2 and FIG.

In FIG. 2, the liquid crystal display controller 1 sequentially transfers display data D0 to D7 for displaying one horizontal line of the liquid crystal panel to the column driver 4 via the display data line 6 in a serial manner. The column driver 4 converts the display data by a display data shift clock CL2 which is sent via the signal line 5-2 in the display signal line 5 and is synchronized with the display data.
The data is shifted and latched inside the column drivers 4-1, 4-2, 4-3, 4-4. When the display data latch in one column driver 4-1 has been latched, a carrier signal ▼ is output to the next-stage column driver 4-2 via a carrier signal line 9-1. The stage column driver 4-2 inputs the display data as an enable signal for shift and latch operations, and starts the shift latch operation. The above operation is performed by each of the column drivers 4-1 to 4-
Step 4 is repeated.

When the display data for one horizontal line displayed on the liquid crystal panel is latched, a voltage corresponding to the display data for one horizontal line is output to the liquid crystal panel 2 and one horizontal line output from the common driver 3 is selectively displayed. The liquid crystal cell of the liquid crystal panel 2 is displaced by a potential difference from a voltage output for the display, and display data is displayed. FIG. 4 shows the output timing of the display data shift clock CL2, the display data D0 to D7, and the carrier signal ▲ output from each column driver.

[Problems to be Solved by the Invention] In the above-described conventional technology, the following problem arises when the frequency of the display synchronization signal for driving the column driver 4 is increased to increase the transfer speed of the display data.

That is, due to the characteristics of the semiconductor integrated circuit, the column driver responds to the display synchronization signal input to the column driver and the carrier signal output from the display synchronization signal.
Output of ▼ is delayed. On the other hand, in the transfer of display data, since the transfer speed is constant, the period is such that the delay time generated in each column driver can be absorbed in order to prevent the driver in the subsequent stage from disturbing the timing of taking in the display data. Lower the clock frequency
The transfer speed must be reduced. Therefore, as shown in FIG. 2, when the liquid crystal panel 2 is displayed, the column driver 4 is arranged in series, and the frequency of the display data shift clock CL2 in the display synchronization signal 5 for transferring the display data is set to the carrier signal. ▲
It must be a constant frequency with a period sufficiently longer than the displacement time of ▼. As a result, the conventional technology has a problem that the transfer speed of display data cannot be increased.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a dot matrix type display device capable of transferring display data at high speed, and a method for driving the same.

[Means for Solving the Problems] In order to achieve the above object, the present invention relates to a driver connected to a plurality of stages and driving a display panel, the amount corresponding to the shift amount in each internal shift register, The display data shift clock supplied to each driver is sequentially counted and obtained for each driver. Based on the amount corresponding to the obtained shift amount, the driver that is currently acquiring the display data shift-enables the next driver. The output of the display data shift clock is delayed for a predetermined time longer than the output delay time of the shift enable signal output from the driver to the next driver from the detected time. It is characterized by making it.

In addition, the present invention also provides a method of transferring display data from a higher-level device to each of drivers connected to a plurality of stages and driving a display panel, after completion of display data capture by a driver that is currently capturing display data. The output of the shift enable signal output from the driver to the next stage driver is suppressed for a predetermined time as a time longer than the output delay time, and the output of the clock signal for the display data to be fetched by the driver is suppressed, and the display sent from the host device during that time is suppressed. The transmission of the display data is resumed when the clock signal is released by suppressing the transfer to the driver by delaying the data accordingly.

Here, the suppression of the display data and the synchronization signal (clock) may be considered as a temporary conversion of these frequencies.
That is, according to the present invention, the transfer frequency of the display synchronization signal and the display data for displaying the display panel is temporarily changed during the transfer of the display data to the driver, and is output as the converted display synchronization signal and the converted display data. This solves the above problem.

Further, in order to achieve the above object, the present invention includes a display panel, a driver connected to the display panel in a plurality of stages and driving the display panel, and a display controller for transferring display data from a higher-level device together with a synchronization signal to the driver. After the display data is captured by the driver that is currently capturing the display data, the driver captures the display data for a predetermined time longer than the output delay time of the shift enable signal output from the driver to the next driver. Signal transfer control means for suppressing the output of the synchronization signal, and the display data sent from the higher-level device in the meantime is delayed accordingly to suppress the transfer to the driver, and the suppression of the synchronization signal is released. Display data transfer control means for restarting the transfer of the display data when the An indication device is provided.

According to another aspect of the present invention, there is provided a display device comprising: a display panel; and a driver that is connected in a plurality of stages, receives display data from a higher-level device together with a synchronization signal, and drives the display panel. After the display data capturing by the driver that is currently capturing display data is completed, the driver takes in the display data for a predetermined time longer than the output delay time of the shift enable signal output from the driver to the next driver. Synchronous signal transfer control means for suppressing the output of the synchronous signal, and display data sent from the host device in the meantime are delayed in accordance with the synchronous signal transfer control means, transfer to the driver is suppressed, and the suppression of the synchronous signal is released. A display data transfer control means for restarting the transfer of the display data.

In the present invention, for example, a liquid crystal panel can be used as the display panel. Further, the present invention can be applied to a display panel capable of performing color display.

[Operation] The present invention relates to display data of a driver that is currently fetching display data when transferring display data from a higher-level device to each driver, particularly a column driver, connected to a plurality of stages and driving a display panel. After the capture, the output of the clock signal for the driver to capture the display data is suppressed until the driver at the next stage can capture the display data. Due to this suppression, during this time, even if the driver at the next stage is in a state in which display data can be taken in, display data is not taken in. Therefore, inaccurate capture of data is prevented.

After capturing the display data of the driver that is currently capturing the display data, until the next driver can capture the display data, for example, using a counter circuit, in synchronization with the display data capturing of each driver. The counting of the clock signal is started, the first time when the counted value reaches a certain value corresponding to the time required for each driver to take in the display data, and from that time, the driver of the next stage set in advance is displayed. The determination can be made by detecting the second time point at which the value corresponds to the time when data can be taken.

Using the first time point and the second time point, the transfer of the clock signal to each driver can be suppressed.

In addition, the present invention suppresses the transfer of data to the driver by delaying the display data sent from the host device while the transfer of the clock is suppressed, in addition to the control of the transfer of the clock. This delay can be performed by the shift circuits of the number of stages corresponding to the number of clock pulses corresponding to the length of the inhibition period. In this case, the number of shift stages is cumulatively increased according to the arrangement order of the drivers to which the display data is to be transferred. That is, assuming that the number of shift stages is m and the number of driver arrangement stages is n, m × (n−1) stages. Here, for the first driver with n = 1, the number of shift stages is 0, and the display data is sent without delay. As for the second and subsequent drivers, the number of shifts increases by m stages each time the order becomes later.

In this way, when display data is sequentially transferred to a plurality of drivers, if display data is not continuously delayed between drivers, that is, even if a wait time is required to send the display data to the next driver, display is performed. Since the data is held with a delay, the host device can continuously transfer the display data in synchronization with the capture of the driver. Therefore, compared to the case of transferring according to the cycle of the waiting time,
Display data can be transferred at high speed.

Examples Examples of the present invention will be described below with reference to the drawings.

FIGS. 1, 5, and 6A show the configuration of the first embodiment of the present invention.

This embodiment is a display device using a liquid crystal panel 2 of 640 horizontal dots × 320 vertical dots, and further includes a liquid crystal display controller 1, a common driver 3, a column driver 4, and a display signal conversion circuit 10. . In the present embodiment, two common drivers 3 are shown in the present embodiment in order to simplify the notation in the drawings, but two common drivers 3 are not necessarily configured. Further, the present invention does not limit the present invention, but includes driving by dividing the vertical direction into two.

The liquid crystal display controller 1 receives a horizontal synchronization signal (hereinafter referred to as CL1).
Display data shift clock (hereinafter abbreviated as CL2) and vertical synchronization signal (hereinafter abbreviated as FLM).
Display synchronization signal and an alternating signal (hereinafter abbreviated as M)
And display data D0 to D7 are transmitted to corresponding display signal line 5-1.
To 5-4 through the display data line 6.

As shown in FIG. 6A, the display signal conversion circuit 10 includes a counter circuit 100, a clock mask circuit 200, and a shift circuit group.
300, and transfers display data from a higher-level device to a driver together with a synchronization signal.

The counter circuit 100 inputs and counts CL2, detects the timing at which the column driver 4 outputs a carrier signal (hereinafter abbreviated as ▼) via the carrier signal line 9-1, and outputs a detection signal. I do. This detection is performed in advance by performing CL2 by counting a constant value (known value) corresponding to the shift amount of the shift register in the column driver 4, as will be described later. During the time corresponding to the time when the driver at the next stage can capture display data,
This detection signal is continuously output.

The clock mask circuit 200 normally receives the CL2,
Although the same frequency clock is output, the input signal CL2 is masked by the detection signal, and the
The output is converted into a Tclock pulse whose timing is delayed for a time longer than the output delay time Tdelay of ▼ and output as a converted display data shift clock (hereinafter, CL2 ′) 7-2.

The shift circuit group 300 detects ▲ by the detection signal.
▼ The display data at the time of output change is shifted so as to be output as converted display data synchronized with CL2 ′.
The display synchronizing signals such as 1, FLM, M, etc. are also shifted in order to synchronize with CL2 ', and correspond to CL1', FLM ', M' as the corresponding display data line 8 and display signal lines 7-1 to 7-4. Output via.

Common driver 3 for driving the common side of liquid crystal panel 2
On the other hand, the display signal conversion circuit 10 sends the display signal lines 7-1,
7-3 and 7-4 are connected to send CL1 ', FLM' and M '. On the other hand, the display signal conversion circuit 10 supplies the display signal lines 7-1, 7-2 and 7- to the column drivers 4-1 to 4-4 for driving the column electrodes of the liquid crystal panel 2.
4 and the display data line 8 are connected, and CL1 ', CL2' and M 'and display data D0 to D7 are sent.

The above-described counter circuit 100 and clock mask circuit 2
At 00, after the display data of the column driver i of the corresponding stage is captured, the output of the synchronization signal for the column driver 4 to capture the display data is performed until the column driver (i + 1) of the next stage can capture the display data. Synchronous signal transfer control means for suppressing is configured. The shift circuit group 300
In the meantime, the display data sent from the host device via the liquid crystal display controller 1 is delayed in accordance with the delay, the transfer to the column driver 4 is suppressed, and when the suppression of the synchronization signal is released, Display data transfer control means for restarting the transfer of display data is configured.

Next, the operation of the display device of the present embodiment configured as described above will be described with reference to FIGS. Each signal and display data are denoted by reference numerals of signal lines and data lines in order to show the correspondence.

FIG. 7 shows the column drivers 4-1, 4-2, 4-3, 4-
4 shows the timing of CL1 ', CL2' and converted display data input to 4, and ▲ output from each column driver.

Each of the column drivers 4-1, 4-2, 4-3, and 4-4 has 160 column-side electrode drive terminals (hereinafter, Y1-160) of the liquid crystal panel 2, and conversion display data D0 for driving these. 7
Since 8-bit data is transferred with one clock of CL2 ', C
With 20 clocks of L2 ', display data of 160 dots for one column driver is latched in the column driver. Therefore, 20 clocks, 40 clocks, 60 clocks, 80 clocks of CL2 '
Clock signals are output from the column drivers 4-1 to 4-4 to the respective carrier signal lines 9-1 to 9-4.
The signal is enabled one after another, reset at the falling edge of the pulse of CL1 ', and disabled.

CL2 and display data D input to the display signal conversion circuit 10
0 to 7, CL2 'to be output and converted display data D0 to 7
FIG. 8 shows the timing of ▲ and ▼.

When the point of the count 20, 40, 60, 80 of the CL2 is defined as a, the counter circuit 100 detects the count of the point a and outputs a detection signal. The above-described clock mask circuit 200 masks CL2 with the point a detection signal,
Output CL2 ′ from Tclock1, Tclo with longer cycle than Tdelay
Convert to ck2 and output.

At the same time, the shift circuit 300 also outputs D (a + 1) and D (a +) after Da of the display data 8 at the point a.
2), ..., and shift to point b (C
After the counts 21, 41, 61, and 81 of L2 '), the data is delayed as latchable and output as converted display data 8.
At this time, the shift circuit 300 shifts CL1, FLM and M by the time Tclock2 by the a-point detection signal to obtain CL2 ', FLM' and M '.
It is output at the timing when -1, 4-2, 4-3 and 4-4 can operate normally.

Here, CL2 ′ is normally output at the period Tclock1, and
One cycle after the point detection is output at Tclock2, and after the point b, the cycle returns to the cycle Tclock1 again. Column driver 4-1, 4-2, 4
Output delay time of ▲ ▼ of -3 and 4-4 output is Td
If elay is set, Tclock1 and Tclock2 are set so that Tclock1 <Tdelay <Tclock2.

If the liquid crystal panel 2 is to be driven for display without using the display signal conversion circuit 10, it is necessary to set the cycle of CL2 to Tclock3 and Tdelay <Tclock3 as shown in FIG.

The above embodiment is an example in which a liquid crystal panel is used as a dot matrix flat panel.
The present invention is not limited to this, and can be similarly applied to other types of dot matrix flat panels. This is the same for the following embodiments.

Next, including the embodiments described above, one embodiment of a display signal conversion circuit preferably used in the present invention, FIG.
This will be described with reference to FIG. 6E.

The display signal conversion circuit according to the present embodiment includes the column driver 4
The counting of the clock signal is started in synchronization with the start of the display data capture of -1 to 4-4, and the count value is constant corresponding to the time required for each column driver 4-1 to 4-4 to capture the display data. A first time point when the value reaches the value, and a second time point corresponding to a time period during which a preset next-stage column driver can take in the display data from that time point.
And a clock for preventing the CL2 from being transferred to each of the column drivers 4-1 to 4-4 from the first time to the second time according to the detection signal. It comprises a mask 200 and a shift circuit group 300 having a plurality of shift circuits for delaying display data and various synchronization signals.

The counter circuit 100 includes a 5-bit synchronous counter 110 that counts CL2, an AND gate circuit 120 that calculates the logical product of the outputs of Q2 and Q4 and the inverted output of Q3, and uses the output of the AND gate circuit 120 as a data input to CL2. D-flip-flop circuit 130 which takes in with the clock of the above, NOR gate circuit 140 which performs a logical OR of the output of flip-flop circuit 130 and the output of AND gate circuit 120, and the logical sum of the output of NOR gate 140 and CL1 OR gate circuit 1 that takes the signal as a clear signal for the 5-bit synchronous counter 110
50 and a counter 160 forming a counter 160 which operates using CL1 as a reset signal and the output of the AND gate 120 as a clock.
The flip-flop circuits 161 and 162 are provided.

The 5-bit synchronization counter 110 is configured, for example, as shown in FIG. 6C. This 5-bit synchronous counter 110
Are five stages of D-flip-flop circuits 111-1 to 111-5 corresponding to the outputs of Q0 to Q4,
Exclusive OR gate circuit to control carry from -2 to 1115
112-1 to 112-4 and NAND gate circuits 113-1 to 113
-3 and an inverter 114 for inverting the input clock.

The clock mask circuit 200 includes CL2 and the counter circuit 10 described above.
It has an AND gate circuit 210 that performs a logical AND operation with the output of the AND gate circuit 120 of 0.

The shift synchronization group 300 includes 11 shift circuits 300 having the same configuration.
-0 to 10 are arranged in parallel, among which 300-0
8 are used for data, and three of 300-8 to 10 are used for CL1 ', FLM' and M 'display signals.

The shift circuit 300-0 is configured by cascading shifters for shifting the display data by the number of pulses of the clock signal between the first time point and the second time point by the number of stages less than the number of stages of the driver. A shifter unit 310 and a selector unit 320 for sequentially selecting and transferring and outputting the output of each shifter in the column order of the shifter every time the clock is suppressed, and then the display data which is not shifted.

The shifter section 310 includes four D-flip-flop circuits 301.
Are connected in tandem in this order.

Note that the shifter unit 310 can be configured using a line memory as shown in FIG. 6F.

The selector section 320 outputs the unshifted data input DATA0,
Data 6-1 output from four-stage shifter 311; data 6-2 output from four-stage shifter 312; and four-stage shifter 313
The data 6-3 output from the counter circuit 100
And selectors 321 to 324 using AND gate circuits, which are gate-controlled by the outputs of the D-flip-flops 161 and 162 and selectively output, and an OR gate circuit 325 which takes a logical wheel of these outputs. The number of selections of the selector section 320 is 4 because it corresponds to the column drivers 4-1 to 4-4. That is, each column driver 4
This corresponds to accumulation of delays in -1 to 4-3.

Next, the operation of the display signal conversion circuit of the present embodiment will be described.

FIG. 6D shows CL1, CL2 and display data DATA0, ON timing of each of the selectors 321 to 324 of the selector section 320, and display data DATA0 'output from the shift circuit 300-0 of the shift circuit shift circuit group 300. Show the relationship. Also, the 6E
The figure shows CL2, display data DATA0 and shift DATA, CL2
The relation between the mask signal, the 5-bit synchronous counter output and the counter reset, and CL2 'and display data DATA0' is shown. In FIG. 6D and FIG. 6E, in order to clarify the correspondence relationship with the signal lines, reference numerals of the signal lines are added.

Further, in the present embodiment, display data for 8 bits is transferred in parallel, but for simplicity of the following description, DA data is transferred.
Only one bit of TA0 is shown.

When sending data for one horizontal line of the liquid crystal pulse to the column drivers 4-1 to 4-4, first, CL1 is output. Thereby, the 5-bit synchronization counter 110 and the D flip-flops 161 and 162 are reset. In this state, each flip-flop circuit 161 of the counter 160 and
Since the Q output of 162 is at a low level, the shift circuit 300−
0 (the same applies to 300-1 to 300-10).
Then, only the selector 321 is in the output enabled state (ON state). That is, DATA0 (display data line 6) is selected.

Thereafter, the 5-bit synchronization counter 110 counts CL2 at its falling edge. Also, CL2 is supplied as a clock to each flip-flop 301 of the shifter section 310, and DATA0 is fetched and DATA0 is shifted in synchronization with CL2.

Next, data DATA0 is sent to D152, and the count value of the 5-bit synchronization counter 110 is 20, that is, “0” in binary notation.
When it becomes “0101”, a CL2 mask signal is output. In response to this, the clock mask circuit 200 blocks the passage of CL2 that has been passed. The output of the flip-flop circuit 130 goes high. Further, the Q output of the flip-flop circuit 161 becomes high level.

When the Q output of the flip-flop circuit 161 becomes high level, the selector 321 of the selector section 320 is turned off, and only the selector 322 is turned on. Therefore, the display data line 6-1 which is the output of the four-stage shifter 311 is selected.

In this state, in the four-stage shifter 311, four bits of data from D128 to D152 are sequentially stored in the flip-flop 301 of each stage. Thereafter, in synchronization with CL2, data after D160 is sequentially taken in, and data D128 to D152 are sequentially shifted and output. Note that even if the column driver 4-2 becomes ready for data input while the bit is being shifted, the clock mask circuit 20
Since the output of CL2 is suppressed by 0, the display data is not taken into the column driver 4-2 during this suppression period. These are shown in FIG. 6E.

Next, when the count value of the 5-bit synchronization counter 110 becomes 24, that is, “00011” in binary notation, the CL2 mask signal 11
-1 changes to low level. Thereby, the suppression of the clock mask circuit is released, and CL2 is output as CL2 '. Also, since the inputs of the NOR gate 140 are both at the low level, the 5-bit synchronization counter 110 is cleared.

In this state, the states of flip-flops 161 and 162 do not change. Therefore, the on state of the selector 322 is maintained. Therefore, the display data line 6- of the four-stage shifter 311 is
The display data from 1 to D160 and thereafter is output as DATA0 '. At this time, as described above, since CL2 'is output as it is to CL2', the column driver 4-2 receives D160.
Subsequent data is fetched sequentially.

Then, the count value of the 5-bit synchronization counter 110 becomes 20 again.
, The CL2 mask signal 11-1 is turned on, and the masking of CL2 is performed as described above, and the selector unit 3
Twenty switches are performed.

That is, in the above-described state, the Q output of the flip-flop circuit 161 which has been at the high level changes to the low level, and accordingly, the Q output of the flip-flop circuit 162 attains the high level. Therefore, the selector 322 is turned off, and only the selector 323 is turned on. Accordingly, the display data line 6-2, which is the output of the four-stage shifter 312, is selected.

Thereafter, the same operation as described above is performed, and the column driver 4-3 fetches display data from the D320. Further, by repeating the synchronization operation, the column driver 4-4 takes in the display data from the D480. This is shown in FIG. 6D.

As described above, in the present embodiment, when the capture of the display data is switched from the preceding column driver to the subsequent column driver, the time required for switching, that is,
Since the display data is buffered by the shift circuit during a period sufficiently including the displacement time of the carrier signal, the liquid crystal display controller 1 can continue the transfer of the display data as it is. Accordingly, it is not necessary to transfer the display data to the time required for switching the column driver, and high-speed transfer of display data can be realized.

Next, a second embodiment of the present invention will be described with reference to FIG. 10 and FIG.

In this embodiment, an RGB vertical stripe type color liquid crystal panel 1 is used.
2 is a display device using a color liquid crystal display controller 21, a common driver 23, and a column driver.
24 and a display signal conversion circuit 30.

The color liquid crystal display controller 21 transmits a color display synchronization signal and color display data to a common driver 23 that drives a common electrode of the RGB vertical stripe type color liquid crystal panel 12 and a column driver 24 that drives a column electrode. They are output via signal lines 13 and display data lines 14, respectively. The display signal conversion circuit 30 converts these into a converted color display synchronization signal and converted color display data, and
The data is output to the common driver 23 and the column driver 24 via the display data line 17.

The common driver 23, which is a component of the present embodiment,
The column driver 24 and the display conversion circuit 30 are similar to those of the corresponding components shown in FIG. 1 described above, except that they handle three types of display data of R, G, and B for color display. Be composed. For example, although not specifically shown, the display signal conversion circuit 30 includes a counter circuit, a clock mask circuit, and a shift circuit corresponding to each component of the display signal conversion circuit 10 shown in FIG. 6A. Therefore, the description of these components will not be repeated.

 Next, the operation of the present embodiment will be described.

FIG. 11 shows a color display data shift clock (hereinafter CCL2) in the color display synchronization signal, a color display data (hereinafter CD0-7), and a converted color display data shift clock (hereinafter CCL2 ') in the converted color display synchronization signal. ), Converted color display data (hereinafter, CD0-7 '), and the timing of the carrier signal (hereinafter, ▼) output from the column driver 4. In FIG. 11, reference numerals for the signal lines and the display data lines are added to clarify the relationship with the signal lines.

In FIG. 11, the data is output via the display data line 14.
CD0-7 is input to the display signal conversion circuit 30 in synchronization with CCL2. The color display data CD0-7 is transferred in the order of red, green, and blue display data R, G, and B, and one pixel is displayed on the color liquid crystal panel 12 by the R, G, and B data. A counter circuit (corresponding to the counter circuit 100 in FIG. 6A) in the display signal conversion circuit 30 detects an output point a of the column driver 4 output to the carrier signal line 9 and outputs a
CD0-7 data up to point +1), R (a + 1), G (a
+1) and B (a + 1) are shifted by a shift circuit (the shift circuit of FIG. 6A).
(Corresponding to 300) and synchronize with CCL2 '.
Output as -7 '. In addition, the clock mask circuit (the
The clock mask circuit 200 shown in Fig. 6A)
Mask the clock from point a to point (a + 1) in 2
Output as CL2 '.

As a result, one pixel of color display data (comprising one dot each of R, G, and B) is transferred in the cycle Tclock3, but the shortest time Tclock1 for transferring one dot display data is shorter than the output delay time Tdelay of ▲ ▼. However, CCL2 'is Tc
A pulse having a cycle delayed by the lock2 time is output, so that the color display data of CD0-7 'can be reliably shifted and latched continuously by the next-stage column driver 4 after the previous-stage column driver 4. I have.

The point a in the present embodiment is the color display data B for CD0-7.
, The color display data is continuously output to CD0-7 'and the CCL2' synchronized with this is output even if the color display data is located at the other color display data position R or G.

The relationship between the periods of the above-described signals is as follows.

Tclock1 <Tdelay <Tclock3 <Tclock2 In this embodiment, as shown in FIG. 11, 4Tclock1 ≦ Tclock3. In addition, the above-described display signal conversion circuit 10
The other color display synchronizing signals are also shifted and converted by the shift circuit to timings at which the color liquid crystal panel can be driven and displayed, and output.

Next, the twelfth embodiment of the third and fourth embodiments of the present invention will be described.
This will be described with reference to FIG. 13 and FIG.

The embodiment shown in FIG. 12 is an example in which the liquid crystal controller 19 incorporating the display signal conversion circuit shown in the first embodiment is used. Other components are the same as in the first embodiment.

As shown in FIG. 12B, the liquid crystal controller 19 of the present embodiment includes the same liquid crystal display controller 1, the counter circuit 100, and the clock mask circuit 200 as those shown in FIG.
And a shift circuit group 300.

The embodiment shown in FIG. 13 is an example in which the color liquid crystal display controller 18 incorporating the display signal conversion circuit shown in the second embodiment is used. Other components are the same as those of the second embodiment.

As shown in FIG. 13B, the liquid crystal controller 18 of this embodiment includes a color liquid crystal display controller 21, a counter circuit 100, a clock mask circuit 200, and a shift circuit group 300 similar to those shown in FIG. And is provided.

According to the embodiments shown in FIGS. 12 and 13, high-speed display driving of liquid crystal can be performed using the conventional liquid crystal display panel, common driver and column driver, respectively.

As described above, according to each embodiment of the present invention, the display data transfer rate in the conventional liquid crystal device is one dot and one cycle Tclock3 as shown in FIG. Even if it is used, by providing the display signal conversion circuit, the display data transfer speed can be transferred as short as one dot transfer in one cycle (Tclock1) as shown in FIG. That is, since there is a relationship of Tclock1 <Tdelay <Tclock3, Tdelay <Tclock2, and moreover, only the number of Tclock2 column drivers, the display data transfer rate can be made higher than before.

Further, in the color liquid crystal device as shown in the second embodiment, the display signal conversion circuit is provided even when the column driver used in the conventional monochrome liquid crystal panel driven at the timing shown in FIG. 9 is used. As shown in the timing chart of FIG. 11, the transfer time of one-dot display data is one cycle Tclock2 (T
delay <Tclock2) and the other one cycle Tclock1 (3Tc
lock ≦ Tclock3, 4Tclock1 = Tclock3 in the second embodiment)
Thus, the speed can be increased, and the display of the color liquid crystal panel can be driven using the conventional column driver.

Although the display device of each of the above embodiments includes a liquid crystal controller, this can be connected to a host device instead of the display device. Also, the display signal conversion circuit may be provided on the host device side. In this case,
A display controller and a display signal conversion circuit are provided on a main body side of an information processing device including a host device, for example, a central processing unit, a memory, and the like, and a display unit of the information processing device is configured including these components.

Next, a fifth embodiment of the present invention will be described with reference to FIG.

The embodiment shown in FIG. 14 is for a color liquid crystal panel.
The converted color display data and the converted color display synchronization signal having the same periodic relationship as shown in FIG.
This is an example of outputting to.

The CRT display controller 31 converts the display information sent from the MPU 40 via the address bus 42 and the data bus 41, and converts the display information into display data 34 for CRT display and a synchronization signal 35 using the frame display memory 32. And output.

The display signal conversion circuit 33 has a data module 36 and a clock module 37, as shown in FIG.
The display signal conversion circuit 33 is provided with a synchronizing signal 3 for the CRT display.
5, vertical sync signal (VSYNC), horizontal sync signal (HSYNC),
The display start position signal (BLANK) and the display data shift dot clock (DOTCLOCK) are sent to the internal clock module 37.
Is converted into a color display conversion signal 16 for color liquid crystal, and the color display data 34 for CRT display is also synchronized with the clock module 37 by the data module 36 to convert the color display data 17 for color liquid crystal. Is converted and output.

Next, a sixth embodiment of the present invention will be described with reference to FIG.

The color liquid crystal display controller 43 includes an address bus 42,
The display information sent from the MPU 40 is converted via the data bus 41, and the converted color display data and converted color display synchronization for the color liquid crystal panel display having the same periodic relationship as shown in FIG. The signal is generated or converted and output to the common driver 23 and the column driver 24 via the signal line 16 and the display data line 17.

FIG. 17 shows the internal configuration of the color liquid crystal display controller 43.

In FIG. 17, the MPU interface module 46
Performs synchronous capture of the display signal from the MPU. The clock module 47 generates a synchronization clock signal inside the color liquid crystal display controller 43. The memory interface 48 mainly performs control of storing and reading out display data of the color liquid crystal panel in the display memory 44. The LCD interface module 49 outputs display data and a synchronization signal for synchronizing the color liquid crystal panel display.

In each of the above embodiments, an example in which the present invention is applied to a column driver is described. However, the present invention can also be applied to a common driver.

In each of the above embodiments, the control for suppressing the output of CL2 is
The display signal conversion is performed at a preset timing in the display signal conversion circuit, but may be performed based on information from the column driver. For example, it is possible to detect the output of the carrier signal of each column driver and control the suppression of the output of CL2.

Further, the present invention includes not only an independent display device but also a device having such a display device as a part. Workstations, personal computers, laptop computers, notebook computers, electronic organizers, etc., to name one example of this type,
A word processor having the same form as these may be used. Further, the present invention is not limited to the information processing device, and can be applied to a display pulse of a television monitor, a measuring device, a control device, and the like.

[Effects of the Invention] According to the present invention, there is an effect that display data can be transferred at high speed regardless of the state of the column driver of the display panel.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of a first embodiment in which the present invention is applied to a display device using a liquid crystal panel. FIG. 2 is a block diagram showing an outline of an embodiment of a conventional liquid crystal display device.
FIG. 4 is a block diagram showing the detailed configuration thereof, FIG. 4 is a timing chart showing the operation of the column driver in the conventional liquid crystal display device, and FIG. 5 shows the detailed configuration of the display device of the first embodiment of the present invention. FIG. 6A is a block diagram showing a configuration of a display signal conversion circuit used in the first embodiment of the present invention, and FIG. 6B is a configuration of one embodiment of a display signal conversion circuit that can be used in the present invention. FIG. 6C is a block diagram showing an example of a 5-bit synchronous counter used in the display signal conversion circuit, FIG. 6D and FIG. 6E are timing charts showing the operation of the display signal conversion circuit, and FIG.
7 is a block diagram showing another configuration example of the shifter circuit, FIGS. 7 and 8 are timing charts showing the operation of the first embodiment, FIG. 9 is a timing chart showing the operation of the conventional column driver, FIG. 10 is a block diagram showing the outline of a second embodiment in which the present invention is applied to a display device using a color liquid crystal panel, FIG. 11 is a timing chart showing the operation of the second embodiment, and FIG. FIG. 12B is a block diagram showing the internal configuration of a third embodiment of the present invention, FIG. 13A is a block diagram showing the outline of a fourth embodiment of the present invention, and FIG. FIG. 14 is a block diagram showing an outline of a fifth embodiment of the present invention, FIG. 15 is a block diagram showing the internal configuration, FIG.
FIG. 13 is a block diagram showing an outline of a sixth embodiment of the present invention.
FIG. 17 is a block diagram showing the internal configuration. 1 ... liquid crystal display controller, 2 ... liquid crystal panel, 3 ...
... common driver, 4 ... column driver, 5 ... display synchronization signal, 6 ... display data, 7 ... conversion display synchronization signal, 8 ... conversion display data.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masaaki Kitajima 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Research Laboratory, Ltd. (72) Inventor Koji Takahashi 3300 Hayano, Mobara City, Chiba Prefecture Inside the Mobara Plant, Hitachi Co., Ltd. (72) Inventor Tsutomu Furuhashi 292 Yoshidacho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. (56) References JP-A-2-217895 (JP, A) JP-A-3-233492 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/36 G02F 1 / 133 505 G09G 3/20 623

Claims (8)

(57) [Claims] 1. A driver for driving a display panel, which is connected in a plurality of stages, sets an amount corresponding to a shift amount in an internal shift register to a display data shift clock supplied to each driver for each driver. Based on an amount corresponding to the calculated shift amount, a time point at which a driver that is currently taking in the display data outputs a shift enable signal to the next driver is detected, and from this detected time point A method for driving the display panel shift clock, wherein the supply of the display data shift clock is delayed for a predetermined time longer than the output delay time of the shift enable signal output from the driver to the next driver. When transferring display data from a higher-level device to each driver connected to a plurality of stages and driving a display panel, after the display data has been fetched by the driver that is currently fetching the display data, the driver receives the display data from the driver. For a predetermined period of time longer than the output delay time of the shift enable signal output to the next-stage driver, the output of the clock signal for the driver to take in the display data is suppressed, and the display data sent from the host device during that time is suppressed. To delay the transmission to the driver,
A display data transfer method for a display device, wherein the transfer of the display data is resumed when the suppression of the clock signal is released. 3. A display panel, comprising: a plurality of stages of connected drivers for driving the display panel; a display controller for transferring display data from a host device to the driver together with a synchronization signal; and fetching current display data. After the display data capture by the driver is completed, the output of the synchronization signal for the driver to capture the display data is suppressed for a predetermined period of time longer than the output delay time of the shift enable signal output from the driver to the next driver. And the display data sent from the higher-level device in the meantime is delayed in accordance with the synchronization signal transfer control means to suppress transfer to the driver. When the suppression of the synchronization signal is released, the display data A display device comprising: display data transfer control means for restarting transfer. 4. A display device comprising a display panel and a driver connected to a plurality of stages and driving the display panel by receiving display data from a host device together with a synchronization signal and driving the display panel. After the driver completes the capture of the display data, when a predetermined time longer than the output delay time of the shift enable signal output from the driver to the next driver is set, the synchronization for suppressing the output of the synchronization signal for the driver to capture the display data is performed. The signal transfer control means and the display data sent from the higher-level device side are delayed in accordance with the signal transfer control means to suppress the transfer to the driver. When the suppression of the synchronization signal is released, the transfer of the display data is stopped. A display data transfer control unit for restarting the display data transfer. 5. A display signal conversion circuit for transferring display data from a host device to a driver together with a synchronization signal for a display device having a display panel and a driver connected to a plurality of stages and driving the display panel. After the display data capturing by the driver that is currently capturing display data is completed, the driver takes in the display data for a predetermined time longer than the output delay time of the shift enable signal output from the driver to the next driver. Synchronous signal transfer control means for suppressing the output of the synchronous signal, and display data sent from the host device in the meantime are delayed in accordance with the synchronous signal transfer control means, transfer to the driver is suppressed, and the suppression of the synchronous signal is released. And display data transfer control means for restarting the transfer of the display data. . 6. A synchronizing signal including a clock signal synchronized with display data transfer from a higher-level device to a display device having a display panel and a driver connected to a plurality of stages and driving the display panel. And a display signal conversion circuit which transfers the clock signal to the driver in synchronization with the start of display data capture of each driver. The count value corresponds to the time required for each driver to capture display data. A counter circuit for detecting a first time point at which a fixed value is reached and a second time point at which the value corresponds to a time period during which a driver of the next stage set in advance can capture display data; A clock mask circuit for suppressing transfer of the clock signal to each driver from a first time to a second time by a signal; A shifter configured by cascading shifters for shifting the display data by the number of pulses of the clock signal from the first time to the second time by the number of stages less than the number of stages of the driver; A shift circuit having a selector section for sequentially selecting display data which is not shifted each time, and sequentially selecting outputs of the shifters in the column order of the shifters, and transferring and outputting the data. 7. An information processing apparatus comprising the display device according to claim 3. 8. A display device having a display panel and a driver connected to a plurality of stages and driving the display panel,
A display controller for transferring display data from a higher-level device together with a synchronization signal to a driver, and outputting a shift enable signal output from the driver to a next-stage driver after completion of display data capture by a driver that is currently capturing display data. A synchronization signal transfer control means for suppressing output of a synchronization signal for the driver to take in display data for a predetermined time longer than the delay time, and delaying display data sent from the host device in accordance with the synchronization signal transfer control means. A display data transfer control means for suppressing transfer to the driver and restarting transfer of the display data when the suppression of the synchronization signal is released.