CN109243392B - Line driving circuit structure and display device - Google Patents
Line driving circuit structure and display device Download PDFInfo
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- CN109243392B CN109243392B CN201811231804.7A CN201811231804A CN109243392B CN 109243392 B CN109243392 B CN 109243392B CN 201811231804 A CN201811231804 A CN 201811231804A CN 109243392 B CN109243392 B CN 109243392B
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- 238000004804 winding Methods 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 abstract description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 101001077376 Oryza sativa subsp. japonica UMP-CMP kinase 4 Proteins 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000013021 overheating Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- 238000002834 transmittance Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
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Abstract
The invention provides a row driving circuit structure and a display device. The connecting line for connecting the clock signal line and the GOA circuit in the line driving circuit structure comprises a first straight line part, a winding part and a second straight line part, wherein one end of the first straight line part is connected with the corresponding clock signal line, the other end of the first straight line part is connected with one end of the winding part, one end of the second straight line part is connected with the GOA circuit, the other end of the second straight line part is connected with the other end of the winding part, and the resistances of a plurality of connecting lines are the same, so that the transverse striations in the display process can be eliminated when the connecting lines are.
Description
Technical Field
The invention relates to the technical field of display, in particular to a row driving circuit structure and a display device.
Background
Liquid Crystal Displays (LCDs) have many advantages such as thin body, power saving, no radiation, and the like, and are widely used. Such as: liquid crystal televisions, mobile phones, Personal Digital Assistants (PDAs), digital cameras, computer screens, notebook computer screens, or the like, are dominant in the field of flat panel displays.
Most of the existing liquid crystal displays in the market are backlight liquid crystal displays (lcds), which include a liquid crystal display panel and a backlight module (backlight module). The liquid crystal display panel operates on the principle that liquid crystal molecules are filled between a thin film Transistor Array Substrate (TFT Array Substrate) and a color filter Substrate (color filter, CF), and driving voltages are applied to the two substrates to control the rotation direction of the liquid crystal molecules, so that light of the backlight module is refracted out to generate a picture.
In the active liquid crystal display, each pixel is electrically connected with a Thin Film Transistor (TFT), a Gate (Gate) of the TFT is connected to a horizontal scanning line, a Source (Source) is connected to a data line in a vertical direction, and a Drain (Drain) is connected to a pixel electrode. Applying sufficient voltage to the horizontal scanning lines can turn on all TFTs electrically connected to the horizontal scanning lines, so that signal voltage on the data lines can be written into the pixels, and the transmittance of different liquid crystals can be controlled, thereby achieving the effect of controlling color and brightness. Currently, the driving of the horizontal scanning lines of the active liquid crystal display panel is mainly performed by an external Integrated Circuit (IC), and the external IC can control the charging and discharging of each level of horizontal scanning lines step by step.
The GOA (Gate Driver on Array) technology is a driving method that can use the Array process of the liquid crystal display panel to fabricate the Gate driving circuit on the TFT Array substrate to scan the Gate line by line. The GOA technology can reduce the welding (bonding) process of an external IC, has the opportunity of improving the productivity and reducing the product cost, and can ensure that the liquid crystal display panel is more suitable for manufacturing narrow-frame or frameless display products.
Referring to fig. 1, a schematic diagram of a conventional line driving circuit structure includes a GOA circuit 100, a plurality of clock signal lines 200, and a plurality of connection lines 300. Many clock signal lines 200 all are located one side of GOA circuit 100, many clock signal lines 200 are arranged along the direction of keeping away from GOA circuit 100 in proper order, many clock signal lines 200 are parallel to each other, many connecting wires 300 all are located one side that GOA circuit 100 is equipped with clock signal line 200, many connecting wires 300 and many clock signal line 200 vertical cross, one end of each connecting wire 300 corresponds and a clock signal line 200 electric connection, other end electric connection GOA circuit 100. Because the distance between each clock signal line 200 and the GOA circuit 100 is different, the lengths of the connection lines 300 connecting different clock signal lines 200 are different, so that the resistances of the connection lines 300 are different, and the lateral capacitances between adjacent clock signal lines 200 are also different, which may cause unequal capacitance-resistance loads (RCloading) on different scan lines when the GOA circuit 100 outputs scan signals to a plurality of scan lines, thereby causing a horizontal streak when the display device displays, and may also cause inconsistent capacitive coupling between adjacent clock signals, resulting in unequal current peaks of adjacent clock signals, which may cause excessive local current of the display device in severe cases, thereby causing overheating of the display device.
Disclosure of Invention
The invention aims to provide a line driving circuit structure which can eliminate horizontal stripes of a display device during display.
Another object of the present invention is to provide a display device capable of eliminating horizontal stripes in display.
In order to achieve the above object, the present invention first provides a row driving circuit structure, which includes a GOA circuit, a plurality of clock signal lines, and a plurality of connecting lines;
the plurality of clock signal lines are sequentially arranged at intervals at one side of the GOA circuit along the direction far away from the GOA circuit and are mutually parallel; one end of each connecting line is correspondingly connected with one clock signal line, and the other end of each connecting line is connected with the GOA circuit;
each connecting line comprises a first straight line part, a winding part and a second straight line part, one end of the first straight line part is connected with the corresponding clock signal line, the other end of the first straight line part is connected with one end of the winding part, one end of the second straight line part is connected with the GOA circuit, and the other end of the second straight line part is connected with the other end of the winding part; the resistances of the connecting wires are the same.
The winding part of each connecting wire comprises a first sub-straight line part, a second sub-straight line part and a third sub-straight line part;
in each connecting line, the second sub-linear portion is located on one side of the second linear portion, two ends of the first sub-linear portion are respectively connected with the other end of the first linear portion and one end of the second sub-linear portion, and two ends of the third sub-linear portion are respectively connected with the other end of the second linear portion and the other end of the second sub-linear portion.
The sum of the lengths of the first straight line part, the second straight line part, the first sub straight line part, the second sub straight line part and the third sub straight line part of the connecting lines is equal, the resistivity of the connecting lines is equal, and the cross-sectional areas of the first straight line part, the second straight line part, the first sub straight line part, the second sub straight line part and the third sub straight line part of each connecting line are equal.
The winding part of each connecting wire except the connecting wire which is connected with the clock signal wire closest to the GOA circuit is positioned between the corresponding clock signal wire and the adjacent other clock signal wire at one side of the corresponding clock signal wire close to the GOA circuit; the winding portion of the connection line connecting the clock signal line closest to the GOA circuit is located between the clock signal line closest to the GOA circuit and the GOA circuit.
In each connecting line, the first straight line part and the second straight line part are collinear, and the first sub straight line part and the third sub straight line part are perpendicular to the first straight line part; the second sub-linear portion is parallel to the first linear portion.
The winding part of each connecting line except for the connecting line which is closest to the clock signal line of the GOA circuit also comprises a fourth sub-straight line part; in each of the connection lines other than the connection line connecting the clock signal line closest to the GOA circuit, the fourth sub-straight line portion is perpendicular to the second sub-straight line portion, one end of the fourth sub-straight line portion is connected to one of the two ends of the second sub-straight line portion, and the other end extends in a direction away from the first straight line portion.
The winding part of each connecting line except the connecting line which is closest to the clock signal line of the GOA circuit also comprises a fifth sub straight line part and a sixth sub straight line part; in each connecting line except for the connecting line which is connected with the clock signal line closest to the GOA circuit, the fifth sub straight line part is perpendicular to the second sub straight line part, one end of the fifth sub straight line part is connected with the other end of the second sub straight line part, and the other end of the fifth sub straight line part extends in the direction away from the first straight line part; the sixth sub straight line part is parallel to the second sub straight line part, and two ends of the sixth sub straight line part are respectively connected with the other end of the fourth sub straight line part and the other end of the fifth sub straight line part.
The sum of the lengths of the fourth sub straight line portion and the third sub straight line portion of each connection line other than the connection line connecting the clock signal line closest to the GOA circuit is equal to the length of the third sub straight line portion of the connection line connecting the clock signal line closest to the GOA circuit.
The widths of the plurality of clock signal lines are the same; the intervals between any two adjacent clock signal lines are the same.
The invention also provides a display device comprising the line driving circuit structure.
The invention has the beneficial effects that: the connecting line for connecting the clock signal line and the GOA circuit in the line driving circuit structure comprises a first straight line part, a winding part and a second straight line part, wherein one end of the first straight line part is connected with the corresponding clock signal line, the other end of the first straight line part is connected with one end of the winding part, one end of the second straight line part is connected with the GOA circuit, the other end of the second straight line part is connected with the other end of the winding part, and the resistances of a plurality of connecting lines are the same, so that the transverse striations in the display process can be eliminated when the connecting line. The display device of the invention comprises the line driving circuit structure, and can eliminate the horizontal stripes during display.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
FIG. 1 is a schematic diagram of a conventional row driver circuit configuration;
FIG. 2 is a diagram of a row driver circuit structure according to a first embodiment of the present invention;
fig. 3 is a schematic diagram of a row driving circuit structure according to a second embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 2, a first embodiment of a column driving circuit structure of the present invention includes a GOA circuit 10, a plurality of clock signal lines 20, and a plurality of connection lines 30.
The plurality of clock signal lines 20 are sequentially arranged at intervals and parallel to each other on one side of the GOA circuit 10 along a direction away from the GOA circuit 10. One end of each connection line 30 is connected to one corresponding clock signal line 20, and the other end is connected to the GOA circuit 10.
Each connecting line 30 includes a first straight portion 31, a winding portion 32, and a second straight portion 33, wherein one end of the first straight portion 31 is connected to the corresponding clock signal line 20, the other end is connected to one end of the winding portion 32, one end of the second straight portion 33 is connected to the GOA circuit 10, and the other end is connected to the other end of the winding portion 32. The plurality of connection lines 30 have the same resistance.
Specifically, referring to fig. 1, in the first embodiment of the present invention, the winding portion 32 of each connecting wire 30 includes a first sub-straight portion 321, a second sub-straight portion 322, and a third sub-straight portion 323. In each connection line 30, the second sub-straight portion 322 is located at one side of the second straight portion 33, two ends of the first sub-straight portion 321 are respectively connected to the other end of the first straight portion 31 and one end of the second sub-straight portion 322, and two ends of the third sub-straight portion 323 are respectively connected to the other end of the second straight portion 33 and the other end of the second sub-straight portion 322.
Specifically, the sum of the lengths of the first straight portion 31, the second straight portion 33, the first sub-straight portion 321, the second sub-straight portion 322, and the third sub-straight portion 323 of the plurality of connection lines 30 is equal, the resistivity of the plurality of connection lines 30 is equal, and the cross-sectional areas of the first straight portion 31, the second straight portion 33, the first sub-straight portion 321, the second sub-straight portion 322, and the third sub-straight portion 323 of each connection line 30 are equal.
Specifically, in the first embodiment shown in fig. 1, the number of the clock signal lines 20 is 4, and the clock signal lines are the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, and the fourth clock signal line CK4, but in other embodiments of the present invention, the number of the clock signal lines 20 may be 2, 3, or more than 4, which does not affect the implementation of the present invention.
Specifically, referring to fig. 1, the winding portion 32 of each connection line 30 except the connection line 30 connecting the clock signal line 20 closest to the GOA circuit 10 is located between the corresponding clock signal line 20 and another adjacent clock signal line 20 on the side of the corresponding clock signal line 20 close to the GOA circuit 10. The winding portion 32 of the connection line 30 connecting the clock signal line 20 closest to the GOA circuit 10 is located between the clock signal line 20 closest to the GOA circuit 10 and the GOA circuit 10.
Specifically, referring to fig. 1, in the first embodiment of the present invention, in each connecting line 30, the first straight line portion 31 and the second straight line portion 33 are collinear, and the first sub-straight line portion 321 and the third sub-straight line portion 323 are perpendicular to the first straight line portion 31. The second sub straight line portion 322 is parallel to the first straight line portion 31. So that the first sub straight line portion 321 and the third sub straight line portion 323 have the same length.
Specifically, referring to fig. 1, in the first embodiment of the present invention, the winding portion 32 of each connection line 30, except for the connection line 30 connected to the clock signal line 20 closest to the GOA circuit 10, further includes a fourth sub-straight portion 324, a fifth sub-straight portion 325 and a sixth sub-straight portion 326. In each connection line 30 except the connection line 30 connecting the clock signal line 20 closest to the GOA circuit 10, the fourth sub-straight line portion 324 is perpendicular to the second sub-straight line portion 322, one end of the fourth sub-straight line portion 324 is connected to one of the two ends of the second sub-straight line portion 322, the other end extends in a direction away from the first straight line portion 31, the fifth sub-straight line portion 325 is perpendicular to the second sub-straight line portion 322, one end of the fifth sub-straight line portion 325 is connected to the other of the two ends of the second sub-straight line portion 322, the other end extends in a direction away from the first straight line portion 31, the sixth sub-straight line portion 326 is parallel to the second sub-straight line portion 322, and the two ends of the sixth sub-straight line portion 326 are respectively connected to the other end of the fourth sub-straight line portion 324 and the other end of the fifth sub-straight line. Accordingly, the fourth sub straight line portion 324 and the fifth sub straight line portion 325 have the same length.
Further, referring to fig. 1, the sum of the lengths of the fourth sub straight portion 324 and the third sub straight portion 323 of each connection line 30 except the connection line 30 connecting the clock signal line 20 closest to the GOA circuit 10 is equal to the length of the third sub straight portion 323 of the connection line 30 connecting the clock signal line 20 closest to the GOA circuit 10.
Specifically, in the first embodiment of the present invention, the lengths of the second sub straight portions 322 of the plurality of connection lines 30 are all equal.
Specifically, in the first embodiment of the present invention, the widths of the plurality of clock signal lines 20 are the same, and the intervals between any two adjacent clock signal lines 20 are the same.
Specifically, in the first embodiment of the present invention, the equivalent lengths of the plurality of connection lines 30 satisfy the following formula:
Lck1＝A0A1+A1A2+A2A3+A3A4+A4A7；
Lck2＝B0B1+B1B2+B2B5+B5B6+B6B7；
Lck3＝C0C1+C1C2+C2C5+C5C6+C6C7；
Lck4＝D0D1+D1D2+D2D5+D5D6+D6D7；
where Lck1 is the equivalent length of the connection line 30 connected to the first clock signal line CK1, A0A1 is the length of the first straight line portion 31 of the connection line 30 connected to the first clock signal line CK1, A1A2 is the length of the first sub straight line portion 321 of the connection line 30 connected to the first clock signal line CK1, A2A3 is the length of the second sub straight line portion 322 of the connection line 30 connected to the first clock signal line CK1, A3A4 is the length of the third sub straight line portion 323 of the connection line 30 connected to the first clock signal line CK1, A4A7 is the length of the second straight line portion 33 of the connection line 30 connected to the first clock signal line CK1, Lck2 is the equivalent length of the connection line 30 connected to the second clock signal line CK2, B0B1 is the length of the first straight line portion 31 of the connection line 30 connected to the second clock signal line CK2, B1B2 is the length of the first sub straight line portion of the connection line CK 321 connected to the second clock signal line CK2, B2B5 is the length of the second sub straight portion 322 of the connection line 30 connected to the second clock signal line CK2, B5B6 is the length of the third sub straight portion 323 of the connection line 30 connected to the second clock signal line CK2, B6B7 is the length of the second straight portion 33 of the connection line 30 connected to the second clock signal line CK2, Lck3 is the equivalent length of the connection line 30 connected to the third clock signal line CK3, C0C1 is the length of the first straight portion 31 of the connection line 30 connected to the third clock signal line CK3, C1C2 is the length of the first sub straight portion 321 of the connection line 30 connected to the third clock signal line CK 6334, C2C5 is the length of the second sub straight portion 322 of the connection line 30 connected to the third clock signal line CK3, C5C6 is the length of the third sub straight portion 323 of the connection line 30 connected to the third clock signal line CK3, and C5C6 is the length of the third sub straight portion 323 of the connection line CK 5966C 3 connected to the third clock signal line CK 4633, lck4 is the equivalent length of the connection line 30 connected to the fourth clock signal line CK4, D0B1 is the length of the first straight portion 31 of the connection line 30 connected to the fourth clock signal line CK4, D1B2 is the length of the first sub-straight portion 321 of the connection line 30 connected to the fourth clock signal line CK4, D2B5 is the length of the second sub-straight portion 322 of the connection line 30 connected to the fourth clock signal line CK4, D5B6 is the length of the third sub-straight portion 323 of the connection line 30 connected to the fourth clock signal line CK4, and D6B7 is the length of the second straight portion 33 of the connection line 30 connected to the fourth clock signal line CK 4.
In the first embodiment of the present invention, the sum of the lengths of the first straight line portion 31, the first sub straight line portion 321, the second sub straight line portion 322, the third sub straight line portion 323, and the second straight line portion 33 of the plurality of connecting lines 30 is equal, so that the equivalent lengths of the plurality of connecting lines 30 are equal, that is, Lck1 ═ Lck2 ═ Lck3 ═ Lck4, and the lengths of the first sub straight line portion 321 and the third sub straight line portion 323 of each connecting line 30 are equal, and in the first embodiment, the widths of the plurality of clock signal lines 20 are equal, and the intervals between any two adjacent clock signal lines 20 are equal, therefore, the above formula is calculated:
X1+X2＝2B2B3；
2(X1+X2)＝2C2C3；
3(X1+X2)＝2D2D3；
where X1 is the width of the clock signal line 20, X2 is the interval between any two adjacent clock signal lines 20, B2B3 is the length of the first sub-straight portion 321 of the connection line 30 connected to the first clock signal line CK1 minus the length of the first sub-straight portion 321 of the connection line 30 connected to the second clock signal line CK2, C2C3 is the length of the first sub-straight portion 321 of the connection line 30 connected to the first clock signal line CK1 minus the length of the first sub-straight portion 321 of the connection line 30 connected to the third clock signal line CK3, and D2D3 is the length of the first sub-straight portion 321 of the connection line 30 connected to the first clock signal line CK1 minus the length of the first sub-straight portion 321 of the connection line 30 connected to the fourth clock signal line CK 4.
Please refer to fig. 3, which is a schematic diagram of a column driving circuit structure according to a second embodiment of the present invention, the difference between the second embodiment and the first embodiment is that the winding portion 32 of each connection line 30 except the connection line 30 connecting the clock signal line 20 closest to the GOA circuit 10 only includes the first sub-straight portion 321, the second sub-straight portion 322, the third sub-straight portion 323, and the fourth sub-straight portion 324, but does not include the fifth sub-straight portion 325 and the sixth sub-straight portion 326, and the rest is the same as the first embodiment, and will not be described herein again.
In the present invention, the winding portions 32 are disposed on the plurality of connection lines 30, and the difference between the sum of the lengths of the first straight portion 31 and the second straight portion 32 of the different connection lines 30, which is caused by the different distances from the plurality of clock signal lines 20 to the GOA circuit 10, is compensated by the winding portions 32, so that the plurality of connection lines 30 have the same resistance, specifically, according to the calculation formula R of the trace resistance, where R is a resistance value, ρ is a resistivity of the trace, L is an equivalent length of the trace, and S is a cross-sectional area of the trace, in the present invention, since the resistivity and the cross-sectional area of the first straight portion 31, the first sub-straight portion 321, the second sub-straight portion 322, the third sub-straight portion 323, and the second straight portion 33 of the plurality of connection lines 30 are the same, the resistance of the plurality of connection lines 30 is determined by the equivalent length thereof, by providing the plurality of connection lines 30 with the same equivalent length, that is, by providing the plurality of connection lines 30 with the same sum of the lengths of the first straight line portion 31, the first sub straight line portion 321, the second sub straight line portion 322, the third sub straight line portion 323, and the second straight line portion 33, the resistances of the plurality of connection lines 30 can be made to be the same, and the present invention also provides the fourth sub straight line portion 324 in the winding portion 32 of each connection line 30 except for the connection line 30 connecting the clock signal line 20 closest to the GOA circuit 10, and the sum of the lengths of the fourth sub straight line portion 324 and the third sub straight line portion 323 of each connection line 30 except for the connection line 30 connecting the clock signal line 20 closest to the GOA circuit 10 is made to be equal to the length of the third sub straight line portion 323 connecting the connection line 30 connecting the clock signal line 20 closest to the GOA circuit 10, so that the side areas of the adjacent clock signal lines 20 and connection lines 30 are made to be the, the invention can eliminate the display horizontal stripes caused by different capacitance-resistance loads on different scanning lines when the line driving circuit is applied to a display device, and can make the capacitance coupling quantities of the adjacent clock signals consistent, so that the current peak values of the adjacent clock signals are equal, and the display device is prevented from overheating caused by overlarge local current of the display device.
Based on the same inventive concept, the invention further provides a display device, which comprises the row driving circuit structure, and repeated description of the row driving circuit structure is omitted here.
In the display device of the present invention, the winding portions 32 are provided on the plurality of connection lines 30, and the difference between the sum of the lengths of the first straight portion 31 and the second straight portion 32 of the different connection lines 30, which is caused by the different distances between the plurality of clock signal lines 20 and the GOA circuit 10, is compensated by the winding portions 32, so that the plurality of connection lines 30 have the same resistance, specifically, the calculation formula R of the trace resistance is ρ L/S, where R is a resistance value, ρ is a resistivity of the trace, L is an equivalent length of the trace, and S is a cross-sectional area of the trace, and therefore, in the present invention, since the resistivities and the cross-sectional areas of the first straight portion 31, the first sub-straight portion 321, the second sub-straight portion 322, the third sub-straight portion 323, and the second straight portion 33 of the plurality of connection lines 30 are the same, the magnitude of the resistance of the plurality of connection lines 30 is determined by the equivalent length thereof, and the equivalent length of the plurality of connection lines 30 is set to be the same, that is, the sum of the lengths of the first straight line part 31, the first sub straight line part 321, the second sub straight line part 322, the third sub straight line part 323, and the second straight line part 33 of the plurality of connection lines 30 is set to be the same, so that the resistances of the plurality of connection lines 30 can be the same, and the fourth sub straight line part 324 is provided in the winding part 32 of each connection line 30 except for the connection line 30 connected to the clock signal line 20 closest to the GOA circuit 10, and the sum of the lengths of the fourth sub straight line part 324 and the third sub straight line part 323 of each connection line 30 except for the connection line 30 connected to the clock signal line 20 closest to the GOA circuit 10 is equal to the length of the third sub straight line part 323 connected to the connection line 30 closest to the clock signal line 20 of the GOA circuit 10, whereby the display device of the present invention can eliminate the display device caused by the The horizontal stripes can enable the capacitance coupling amount of the adjacent clock signals to be consistent, so that the current peak values of the adjacent clock signals are equal, and the display device is prevented from being overheated due to overlarge local current.
In summary, the connection lines for connecting the clock signal lines and the GOA circuits in the row driving circuit structure of the present invention include a first straight line portion, a winding portion, and a second straight line portion, one end of the first straight line portion is connected to the corresponding clock signal line, the other end of the first straight line portion is connected to one end of the winding portion, one end of the second straight line portion is connected to the GOA circuit, the other end of the second straight line portion is connected to the other end of the winding portion, and the resistances of the plurality of connection lines are the same, so that the horizontal stripes in the display can be eliminated when the. The display device of the invention comprises the line driving circuit structure, and can eliminate the horizontal stripes during display.
As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications are intended to fall within the scope of the appended claims.
Claims (5)
1. A row driving circuit structure is characterized by comprising a GOA circuit (10), a plurality of clock signal lines (20) and a plurality of connecting lines (30);
the clock signal lines (20) are sequentially arranged at intervals at one side of the GOA circuit (10) along the direction far away from the GOA circuit (10) and are mutually parallel; one end of each connecting wire (30) is correspondingly connected with one clock signal wire (20), and the other end is connected with the GOA circuit (10);
each connecting line (30) comprises a first straight line part (31), a winding part (32) and a second straight line part (33), one end of each first straight line part (31) is connected with the corresponding clock signal line (20), the other end of each first straight line part is connected with one end of each winding part (32), one end of each second straight line part (33) is connected with the GOA circuit (10), and the other end of each second straight line part is connected with the other end of each winding part (32); the resistances of the connecting lines (30) are the same;
the winding part (32) of each connecting wire (30) comprises a first sub-straight line part (321), a second sub-straight line part (322) and a third sub-straight line part (323);
in each connecting line (30), the second sub-straight line part (322) is positioned at one side of the second straight line part (33), two ends of the first sub-straight line part (321) are respectively connected with the other end of the first straight line part (31) and one end of the second sub-straight line part (322), and two ends of the third sub-straight line part (323) are respectively connected with the other end of the second straight line part (33) and the other end of the second sub-straight line part (322);
the winding part (32) of each connecting line (30) except the connecting line (30) which is connected with the clock signal line (20) closest to the GOA circuit (10) is positioned between the corresponding clock signal line (20) and the adjacent other clock signal line (20) at the side of the corresponding clock signal line (20) close to the GOA circuit (10); a winding part (32) of a connecting line (30) for connecting the clock signal line (20) closest to the GOA circuit (10) is positioned between the clock signal line (20) closest to the GOA circuit (10) and the GOA circuit (10);
in each connecting line (30), the first straight line part (31) and the second straight line part (33) are collinear, and the first sub-straight line part (321) and the third sub-straight line part (323) are perpendicular to the first straight line part (31); the second sub-straight line portion (322) is parallel to the first straight line portion (31);
the winding part (32) of each connection line (30) except the connection line (30) connecting the clock signal line (20) closest to the GOA circuit (10) further comprises a fourth sub-straight line part (324); in each connecting line (30) except the connecting line (30) which is connected with the clock signal line (20) closest to the GOA circuit (10), the fourth sub straight line part (324) is perpendicular to the second sub straight line part (322), one end of the fourth sub straight line part (324) is connected with one of two ends of the second sub straight line part (322), and the other end extends in the direction away from the first straight line part (31);
the sum of the lengths of the fourth sub straight line portion (324) and the third sub straight line portion (323) of each connection line (30) other than the connection line (30) connecting the clock signal lines (20) closest to the GOA circuit (10) is equal to the length of the third sub straight line portion (323) of the connection line (30) connecting the clock signal lines (20) closest to the GOA circuit (10).
2. The line driving circuit arrangement of claim 1, wherein the sum of the lengths of the first straight portion (31), the second straight portion (33), the first sub-straight portion (321), the second sub-straight portion (322) and the third sub-straight portion (323) of the plurality of connection lines (30) is equal, the resistivity of the plurality of connection lines (30) is equal, and the cross-sectional areas of the first straight portion (31), the second straight portion (33), the first sub-straight portion (321), the second sub-straight portion (322) and the third sub-straight portion (323) of each connection line (30) are equal.
3. The row driver circuit arrangement of claim 1, wherein the winding portion (32) of each connection line (30) other than the connection line (30) connecting the clock signal line (20) closest to the GOA circuit (10) further comprises a fifth sub-straight portion (325) and a sixth sub-straight portion (326); in each connection line (30) except for the connection line (30) which is connected with the clock signal line (20) closest to the GOA circuit (10), the fifth sub-straight line part (325) is perpendicular to the second sub-straight line part (322), one end of the fifth sub-straight line part (325) is connected with the other of the two ends of the second sub-straight line part (322), and the other end extends in the direction away from the first straight line part (31); the sixth sub straight line part (326) is parallel to the second sub straight line part (322), and two ends of the sixth sub straight line part (326) are respectively connected with the other end of the fourth sub straight line part (324) and the other end of the fifth sub straight line part (325).
4. A row driver circuit arrangement as claimed in claim 1, characterized in that the width of the plurality of clock signal lines (20) is the same; the intervals between any two adjacent clock signal lines (20) are the same.
5. A display device comprising a row driver circuit arrangement as claimed in any one of claims 1 to 4.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811231804.7A CN109243392B (en) | 2018-10-22 | 2018-10-22 | Line driving circuit structure and display device |
| PCT/CN2018/120982 WO2020082541A1 (en) | 2018-10-22 | 2018-12-13 | Row driving circuit structure and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811231804.7A CN109243392B (en) | 2018-10-22 | 2018-10-22 | Line driving circuit structure and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109243392A CN109243392A (en) | 2019-01-18 |
| CN109243392B true CN109243392B (en) | 2020-09-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811231804.7A Active CN109243392B (en) | 2018-10-22 | 2018-10-22 | Line driving circuit structure and display device |
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| Country | Link |
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| CN (1) | CN109243392B (en) |
| WO (1) | WO2020082541A1 (en) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109637424A (en) * | 2019-01-24 | 2019-04-16 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN110675819A (en) * | 2019-09-02 | 2020-01-10 | 深圳市华星光电半导体显示技术有限公司 | Connecting circuit of display panel light-emitting device |
| CN110689836A (en) * | 2019-10-22 | 2020-01-14 | 深圳市华星光电技术有限公司 | GOA circuit and display panel |
| CN110854138B (en) * | 2019-11-25 | 2022-03-08 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN111292696B (en) * | 2020-02-27 | 2021-07-06 | 深圳市华星光电半导体显示技术有限公司 | GOA driving circuit, GOA array substrate, display panel and display device |
| CN111240114B (en) * | 2020-03-16 | 2021-06-01 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| CN111091776B (en) * | 2020-03-22 | 2020-06-16 | 深圳市华星光电半导体显示技术有限公司 | Drive circuit and display panel |
| CN111091775B (en) * | 2020-03-22 | 2020-09-01 | 深圳市华星光电半导体显示技术有限公司 | Display panel and electronic equipment |
| CN111312189A (en) * | 2020-03-31 | 2020-06-19 | 深圳市华星光电半导体显示技术有限公司 | GOA (Gate driver on array) driving circuit and array substrate |
| CN111679520A (en) * | 2020-06-01 | 2020-09-18 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN111653229B (en) * | 2020-06-22 | 2022-07-15 | 武汉京东方光电科技有限公司 | Gate drive circuit and display device |
| CN113971940B (en) | 2020-07-24 | 2023-03-10 | 京东方科技集团股份有限公司 | Gate drive circuit and display panel |
| CN113964136B (en) * | 2021-10-13 | 2022-12-06 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN113990270B (en) * | 2021-11-08 | 2023-03-17 | 深圳市华星光电半导体显示技术有限公司 | Display device |
| CN114167652B (en) * | 2021-11-09 | 2024-03-29 | Tcl华星光电技术有限公司 | Display panel and mobile terminal |
| CN114093298B (en) * | 2021-11-24 | 2024-04-05 | 武汉京东方光电科技有限公司 | Configuration method and device of display device, storage medium and electronic device |
| CN114141198B (en) * | 2021-12-07 | 2023-04-21 | 合肥京东方卓印科技有限公司 | Scanning driving circuit, maintenance method thereof and display device |
| CN114360432A (en) * | 2022-02-18 | 2022-04-15 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| CN114695389A (en) * | 2022-03-18 | 2022-07-01 | Tcl华星光电技术有限公司 | Display panel and display device |
| CN114898721A (en) * | 2022-06-22 | 2022-08-12 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| WO2024087034A1 (en) * | 2022-10-25 | 2024-05-02 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN117496886A (en) * | 2023-12-29 | 2024-02-02 | 元旭半导体科技股份有限公司 | Method and system for improving display performance of LED display screen |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106991949A (en) * | 2015-12-30 | 2017-07-28 | 三星显示有限公司 | Display device |
| CN107305306A (en) * | 2016-04-20 | 2017-10-31 | 三星显示有限公司 | Display device |
| CN207038050U (en) * | 2017-08-23 | 2018-02-23 | 京东方科技集团股份有限公司 | Array base palte and display device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101427584B1 (en) * | 2008-01-22 | 2014-08-08 | 삼성디스플레이 주식회사 | Display device |
| TWI546598B (en) * | 2010-08-27 | 2016-08-21 | 友達光電股份有限公司 | Lcd panel and method of manufacturing the same |
| CN104952888A (en) * | 2015-07-20 | 2015-09-30 | 合肥鑫晟光电科技有限公司 | Peripheral circuit for display baseplate, display baseplate and display device |
| CN105761662B (en) * | 2016-05-19 | 2018-11-23 | 京东方科技集团股份有限公司 | Gate driving circuit, the driving method of gate driving circuit and display device |
| CN106371255A (en) * | 2016-11-08 | 2017-02-01 | 厦门天马微电子有限公司 | Array substrate and display panel comprising same and display device |
| CN206573830U (en) * | 2017-03-13 | 2017-10-20 | 惠科股份有限公司 | Array substrate and display device |
| CN206848661U (en) * | 2017-07-03 | 2018-01-05 | 京东方科技集团股份有限公司 | Array base palte and display device |
-
2018
- 2018-10-22 CN CN201811231804.7A patent/CN109243392B/en active Active
- 2018-12-13 WO PCT/CN2018/120982 patent/WO2020082541A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106991949A (en) * | 2015-12-30 | 2017-07-28 | 三星显示有限公司 | Display device |
| CN107305306A (en) * | 2016-04-20 | 2017-10-31 | 三星显示有限公司 | Display device |
| CN207038050U (en) * | 2017-08-23 | 2018-02-23 | 京东方科技集团股份有限公司 | Array base palte and display device |
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| Publication number | Publication date |
|---|---|
| CN109243392A (en) | 2019-01-18 |
| WO2020082541A1 (en) | 2020-04-30 |
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