CN104952888A - Peripheral circuit for display baseplate, display baseplate and display device - Google Patents
Peripheral circuit for display baseplate, display baseplate and display device Download PDFInfo
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- CN104952888A CN104952888A CN201510431178.6A CN201510431178A CN104952888A CN 104952888 A CN104952888 A CN 104952888A CN 201510431178 A CN201510431178 A CN 201510431178A CN 104952888 A CN104952888 A CN 104952888A
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- 230000002093 peripheral effect Effects 0.000 title claims abstract description 54
- 239000000463 material Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 22
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 239000007772 electrode material Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000007323 disproportionation reaction Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a peripheral circuit for a display baseplate, the display baseplate and a display device. The peripheral circuit comprises a circuit used for connecting a display area, and a plurality of leading wires, made of the same material, of an integrated circuit of a peripheral area, wherein the lengths of the leading wires are not completely the same; the widths of the leading wires are not completely the same; the widths of the leading wires are gradually increased along with the increase of the lengths of the leading wires. The resistance difference of the leading wires in the peripheral circuit can be reduced, picture unevenness caused by overlarge resistance difference of the leading wires can be improved, and the narrow frame design of a high PPI product can be realized.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of peripheral circuit of substrate for display, substrate for display and display unit.
Background technology
Along with the development of Display Technique, high-resolution, narrow frame, driving chip quantity reduce the notable feature becoming big-and-middle size display screen.Resolution raising makes grid line and holding wire quantity increase, and narrow frame design makes peripheral circuit space be compressed, and the minimizing of driving chip quantity can reduce costs but can further increase wiring difficulty.
In the prior art, the lead-in wire (e.g., grid line or holding wire) of peripheral circuit region adopts identical material, thickness usually, and with etc. the mode of live width arrange.For each lead-in wire being connected to same chip, because the length of each lead-in wire is inconsistent, when each lead material and consistency of thickness, the resistance of lead-in wire is directly proportional to the length of lead-in wire.Again due to, general, the length of submarginal lead-in wire is greater than the length by paracentral lead-in wire.Therefore, the resistance of submarginal lead-in wire is greater than the resistance by paracentral lead-in wire.But when the resistance between each lead-in wire differs greatly, display screen may be caused when showing image, under there is grey menu, bright dark inequality, transverse direction and vertical striped etc. show bad problem.
In addition, if solve the problem compared with the length of short leg by increasing, the area of outer peripheral areas can be taken again, thus frame can be caused wider or reduce the problem of PPI.So just be unfavorable for the product realizing narrow frame, high PPI.
Summary of the invention
The object of the present invention is to provide a kind of peripheral circuit of substrate for display, substrate for display and display unit, to reduce or to eliminate the resistance difference of each lead-in wire in peripheral circuit, and realize high PPI, narrow frame design.
For solving the problems of the technologies described above, as first aspect of the present invention, a kind of peripheral circuit of substrate for display is provided, comprise: for the many lead-in wires with material of the integrated circuit of the circuit and outer peripheral areas that connect viewing area, the length of described a plurality of leads is incomplete same, and the width of described a plurality of leads is incomplete same; Wherein, the width of described a plurality of leads increases gradually with the increasing lengths of lead-in wire.
Preferably, described a plurality of leads is arranged in order from the centre of lead-in wire region to both sides, is less than the wire length near both sides near middle wire length; Wherein, the wire widths near both sides is less than near middle wire widths.
Preferably, the width of each lead-in wire arranged to the direction of the either side both sides from centre, increases gradually with identical increment.
Preferably, the scope of described increment is 0.1um ~ 20um.
Preferably, as the length L of each lead-in wire
ndetermine, and the length L of certain setting lead-in wire
1and width W
1when determining, the width of all the other lead-in wires in a plurality of leads meets following formula:
W
n＝L
nW
1/L
1；
W
nbe the width of n-th lead-in wire, 1≤n≤N, N is pincounts.
Preferably, the line of one end of each lead-in wire is as the first line, and the line of the other end of each lead-in wire is as the second line, and described first line is parallel with described second line;
Described a plurality of leads is arranged in order from the centre of lead-in wire region to both sides, and each lead-in wire is straight line; Angle between arbitrary neighborhood two lead-in wire is γ; Setting is the 1st article with the perpendicular lead-in wire of described first line and go between, then n-th bar of lead-in wire is (n-1) γ with the described 1st article of angle gone between, and so, n-th width gone between meets following formula:
W
n＝W
1/sin[90-(n-1)γ]；
Wherein, n is positive integer; W
1for the width of the lead-in wire perpendicular with the first line.
Preferably, the lead-in wire near centre is curve; Lead-in wire near both sides is straight line or curve;
Wherein, described curve is wave, arcuate line, jaggies or curved line.
Preferably, described a plurality of leads is arranged with layer; Or described a plurality of leads bilayer is arranged, and adjacent lead-in wire different layers is arranged.
As second aspect of the present invention, also provide a kind of substrate for display, described substrate for display comprises above-mentioned peripheral circuit provided by the present invention.
As the 3rd aspect of the present invention, also provide a kind of display unit, described display unit comprises above-mentioned substrate for display provided by the present invention.
The present invention reduces the resistance difference in peripheral circuit between lead-in wire with the live width such as non-and the design of gradual change live width, can realize waiting resistance wiring, thus it is bad to improve because distance end lead resistance difference is excessive the displays such as picture that is that cause is uneven, horizontal and vertical striped.In addition, for the high PPI product that number of leads in peripheral circuit increases, the present invention by wiring space to extending transversely, can reduce the vertical range shared by peripheral circuit, thus is conducive to realizing narrow frame design.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for specification, is used from explanation the present invention, but is not construed as limiting the invention with embodiment one below.
Fig. 1 is the schematic diagram of substrate for display in the embodiment of the present invention;
Fig. 2 is one of lead-in wire arrangement schematic diagram of peripheral circuit in the embodiment of the present invention;
Fig. 3 is the design diagram realizing the distribution of resistance such as lead-in wire in the embodiment of the present invention;
Fig. 4 is the lead-in wire arrangement schematic diagram two of peripheral circuit in the embodiment of the present invention;
Fig. 5 is the enlarged diagram of bend unit I in Fig. 4;
Fig. 6 is the lead-in wire arrangement schematic diagram three of peripheral circuit in the embodiment of the present invention;
Fig. 7 is the lead-in wire arrangement schematic diagram four of peripheral circuit in the embodiment of the present invention;
Fig. 8 is the lead-in wire arrangement schematic diagram five of peripheral circuit in the embodiment of the present invention;
Fig. 9 is the schematic diagram of a lead-in wire in Fig. 8.
In the accompanying drawings, 1-viewing area; 3-peripheral circuit; 31-goes between; 311-is near middle lead-in wire; 312-is near the lead-in wire of both sides; 4-integrated circuit; 51-first line; 52-second line; I-bend unit; 601-first vertical portion; 602-first horizontal part; 603-second vertical portion; 604-second horizontal part; 605-the 3rd vertical portion; 7-first conductive layer; 8-second conductive layer; 91-vertical line region; 92-hatched example areas; The narrow curved region of 93-; The wide curved region of 94-.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Should be understood that, embodiment described herein, only for instruction and explanation of the present invention, is not limited to the present invention.
The present invention provide firstly a kind of peripheral circuit of substrate for display, as shown in Figure 1, mainly provides a kind of peripheral circuit 3 comprising some lead-in wires 31.Concrete, peripheral circuit 3 comprises the many lead-in wires 31 with material of the integrated circuit 4 (as drive IC) for connecting circuit (as image element circuit) in the viewing area 1 (i.e. AA region) of described substrate for display and outer peripheral areas.That is, one end of some lead-in wires 31 is for connecting the grid line/data wire in AA region, and the other end is for connecting the golden finger in drive IC binding region.
General, each lead-in wire 31 in peripheral circuit 3 is being formed with in a patterning processes, therefore, the parameter such as material, thickness of each lead-in wire 31 is consistent, but, because the grid line being arranged in viewing area 1 diverse location is different with the distance of data wire distance drive IC, therefore, the length of each lead-in wire 31 is generally incomplete same.
As mentioned above, in the prior art, the width of each lead-in wire 31 is consistent, length so due to each lead-in wire 31 is incomplete same, the length of usual submarginal lead-in wire 31 is greater than the length by paracentral lead-in wire 31, therefore submarginally draws, and the resistance of 31 is greater than the resistance by paracentral lead-in wire, when resistance between each lead-in wire 31 differs greatly, brightness disproportionation, striped Mura etc. will be caused to show bad phenomenon and to occur.
In peripheral circuit 3 provided by the present invention, the length of a plurality of leads 31 is incomplete same, and the width of a plurality of leads 31 is incomplete same; Wherein, the width of a plurality of leads 31 increases gradually with the increasing lengths of lead-in wire 31.That is, the length of lead-in wire 31 is longer, and its width is also wider.
It should be noted that, " length is incomplete same " here comprises all not identical situation of length of every bar lead-in wire 31, also comprises part 31 length that go between identical, and another part goes between the different situation of 31 length; Here " width is incomplete same " comprises all not identical situation of width of every bar lead-in wire 31, also comprises part 31 width that go between identical, and another part goes between the different situation of 31 width.
The peripheral circuit that the invention described above embodiment provides, at same material, under the prerequisite of stack pile lead-in wire, resistance is directly proportional to the length of lead-in wire, is inversely proportional to the width of lead-in wire.The present invention due to lead-in wire width with lead-in wire increasing lengths and increase gradually, the lead-in wire wire laying mode of width such as to compare, reduce compared with long lead and compared with the resistance difference between short leg, effectively can to reduce in peripheral circuit the resistance difference caused because length is different between each lead-in wire like this, thus effectively can avoid that the resistance difference because of each lead-in wire is excessive and picture that is that cause is uneven, laterally and the bad problem of the display such as vertical striped.
In practical application scene, the lead-in wire that the grid line in the viewing area that distance drive IC is far away or data wire are drawn is longer, and the lead-in wire that the grid line in the viewing area that distance drive IC is nearer or data wire are drawn is shorter, and arranges regularly between lead-in wire.
See Fig. 2 and Fig. 3, a plurality of leads 31 is arranged in order from the centre (the 1st article of lead-in wire region as shown in Figure 3) of lead-in wire region to both sides (N article of lead-in wire region as shown in Figure 3 and region symmetrical with it), and the length near middle lead-in wire 31 is less than the length of the lead-in wire 31 near both sides; Wherein, the width of close middle lead-in wire 31 is less than the width of the lead-in wire 31 near both sides.
Preferably, as shown in Figure 2, from lead-in wire region centre to both sides, lead-in wire 31 width increase gradually.Due to go between 31 from centre to arranged on both sides time, length increases gradually, therefore, in order to the resistance reducing the lead-in wire 31 caused because length increases increases gradually, by increasing lead-in wire 31 width gradually, the resistance difference between lead-in wire 31 can be reduced, effectively improving the uniformity coefficient of display frame.
As the first situation of the present invention, the width of each lead-in wire arranged to the direction of the either side both sides from the centre of peripheral circuit, increases gradually with identical increment.
That is, compared with each lead-in wire goes between with adjacent last bar, the amplitude that width increases is identical.Or, as the second situation of the present invention, from the centre of peripheral circuit to the direction of the either side both sides, the width of adjacent legs increases gradually with different increments, further, to go between the closer to the lead-in wire of the both sides of peripheral circuit with last bar compared with the increment of width larger.Here the change of " increment " can be linear, also can be nonlinear.
Such as, N bar lead-in wire is placed with altogether from the middle part of peripheral circuit to a lateral edges of peripheral circuit, increment wherein between (n+1)th width gone between and n-th width gone between is greater than the increment between n-th width gone between and (n-1)th width gone between, and n is integer here, and 2≤n≤N-1.
Visible, this wire laying mode is more flexible compared with waiting wire laying mode of increment, and the increment of physical length to its width that can go between according to every bar regulates, to obtain better display effect.
In embodiments of the present invention, according to the experience of actual production, the difference of the width of adjacent legs can between 0.1um-20um.Preferably, the width of the narrowest lead-in wire can be set to the accessible minimum widith of technique, such as, can be 0.1um, 1um, 1.5um etc.
In order to reduce the difference of resistance between each lead-in wire further, this just requires the width accurately controlling each lead-in wire, ensures there is not resistance difference between each lead-in wire.
Consider that lead resistance is directly proportional to wire length, be inversely proportional to wire widths, therefore, as the length L of each lead-in wire
ndetermine, and the length L of certain setting lead-in wire (the 1st bar of lead-in wire as shown in Figure 3)
1and width W
1when determining, the width of all the other lead-in wires in a plurality of leads meets following formula (1-1):
W
n＝L
nW
1/L
1(1-1)
W
nbe the width of n-th lead-in wire, 1≤n≤N, N is pincounts.
From formula (1-1), as long as determine the 1st article of length gone between and width, just can determine the ratio of other length gone between and width, when determining the length that other go between, width just can be determined.Like this, the resistance difference value between each lead-in wire determined is almost nil.
Can be metal or transparent electrode material etc. for making the material of lead-in wire in the present invention.When utilizing transparent electrode material to make lead-in wire, because the resistivity of transparent electrode material is higher than the resistivity of metal material, in order to reduce the resistance of lead-in wire, the width of increasing lead-in wire that can be suitable.
Described lead-in wire can be made by the metal materials such as aluminium, silver, copper, molybdenum or the alloy of at least two kinds comprised in these metals, or can be made by indium tin oxide (ITO) transparent electrode material.
When determining above by formula (1-1) width gone between, need under the prerequisite determining the length gone between, then determine the width of lead-in wire, when practical operation, the mode of layout lead-in wire is more, causes the width gone between to be inconvenient to grasp.
Therefore, the invention provides one preferably wiring layout's mode, see Fig. 3, the line of one end of each lead-in wire 31 is as the first line 51, and the line of the other end of each lead-in wire 31 is parallel with the second line 52 as the second line 52, first line 51;
A plurality of leads 31 is arranged in order from the centre of lead-in wire region to both sides, and each lead-in wire 31 is straight line; Angle between arbitrary neighborhood two lead-in wire 31 is γ; Setting is the 1st article with the perpendicular lead-in wire of the first line 51 and go between, then n-th bar of lead-in wire is (n-1) γ with the described 1st article of angle gone between, and so, n-th width gone between meets following formula (1-2):
W
n＝W
1/sin[90-(n-1)γ] (1-2)
Wherein, n is positive integer; W
1for the width (i.e. the 1st article of width gone between in Fig. 3) of the lead-in wire perpendicular with the first line 51.
The origin of formula (1-2) below will be described.
Under same substrate manufacture process conditions, the thickness of each lead-in wire is consistent, and material is identical, now square resistance R
sidentical.Further, R
s=ρ/a, ρ is the resistivity of the material making lead-in wire, and a is the thickness of lead-in wire.
When needs realization every bar as shown in Figure 3 goes between 31 impartial resistance wires design, first calculate the resistance R of the 1st bar of lead-in wire
1, due to the length L of the 1st bar of lead-in wire
1equal the distance c between viewing area and integrated circuit (as drive IC), therefore R
1meet following formula (1-3):
R
1＝R
sc/W
1(1-3)
Here W
1adopt the minimum widith that can realize in existing manufacture craft.
Then calculate the angle γ of adjacent legs, because a plurality of leads 31 is normally spacedly distributed, therefore the angle γ of adjacent legs can think identical, and γ=(90-β)/X;
Wherein, β is the angle between N bar of lead-in wire and the second line 52, as can be seen from Figure 3 sin β=c/L
n, L
nbe the length of N bar of lead-in wire, X=N
dATA/ 2N
cOF, N
dATAfor go between 31 total number, N
cOFfor the number of integrated circuit.
Such as, when described substrate for display comprises two integrated circuits, X is the total number N of lead-in wire 31
dATA1/4th.
For the 2nd bar of lead-in wire, due to etc. resistive arrangement, its resistance R
2with R
1equal, that is: R
2=R
1=R
sl
2/ W
2, in addition, according to the graphics relationship in Fig. 3, sin β
2=c/L
2; β
2=90-γ; The 2nd article of width gone between: W can be drawn
2=R
sc/ [sin (90-γ) R
1].
Afterwards, by iterative computation, the width W of n-th lead-in wire can be obtained
n, see formula (1-4):
W
n＝R
sc/{sin[90-(n-1)γ]R} (1-4)
Bring formula (1-3) into formula (1-4) and formula (1-2) can be obtained.
Can find out according to above-mentioned formula, from the middle part of peripheral circuit to both sides, due to go between 31 length L
nincrease gradually, when waiting distribution of resistance, the width W of lead-in wire 31
nalso should be broadening gradually.
Further, the shape of the lead-in wire in the present invention can be straight line, and also can be curve, curve here comprises the shapes such as wave, arcuate line, jaggies or curved line.Be understandable that, when apart from identical, the physical length of curve is greater than the physical length of straight line, therefore, according to the distance length at the two ends that will connect that go between, can decide lead-in wire selection straight line or curve.
Preferably, in the region at lead-in wire place, be curve near middle lead-in wire; Lead-in wire near both sides is straight line or curve; Wherein, described curve is wave, arcuate line, jaggies or curved line.
This is because, the lead-in wire usually near middle is shorter, if be designed to curve, its physical length can be extended, thus reduce middle lead-in wire and the resistance difference between the lead-in wire of both sides, and then improve the bad problem of display because resistance difference causes.
As shown in Figure 4, a plurality of leads 31 comprises near middle lead-in wire 311 and the lead-in wire 312 near both sides, wherein, is the shape of similar arcuate line near middle lead-in wire 311; 312, the lead-in wire near both sides is made up of multiple straightway.This wire laying mode effectively reduces near middle lead-in wire 311 and the resistance difference between the lead-in wire 312 of both sides, is conducive to improving display effect.
In addition, lead-in wire 312 near both sides does not have employing straight line, but adopt the mode of many straightway splicings, for the high PPI product that number of leads increases, this execution mode is by near extending transversely to wiring space of the lead-in wire 312 of both sides, the vertical range shared by peripheral circuit can be reduced, thus be conducive to realizing narrow frame design.
Be described in detail to the arcuate line shown in Fig. 4 below.
Comprise multiple bend unit I near middle lead-in wire 311, as shown in Figure 5, each bend unit I comprises the first vertical portion 601, first horizontal part 602, second vertical portion 603, second horizontal part 604 and the 3rd vertical portion 605 connected successively.In adjacent two bend unit I, the 3rd vertical portion 605 of last bend unit I is connected with first vertical portion 601 of a rear bend unit I.That is, the bend unit in the present invention can adopt the structure of similar " bow " font.
It should be noted that, the bend unit in the present invention also can replace with wave unit, jaggies unit, camber line unit etc., repeats no more herein.
The present invention is by design bend unit, effectively extend and be arranged in the length of peripheral circuit near middle lead-in wire 311, compensate for the resistance near middle lead-in wire 311, reduce the difference between the resistance near middle lead-in wire 311 and the resistance of the lead-in wire 312 near both sides, thus improve and that cause picture non-uniform phenomenon excessive due to distance end lead resistance difference, improve display effect.
In the present invention, a plurality of leads all can be made within the same layer, as shown in Figure 6.Or, a plurality of leads bilayer can be arranged, and adjacent lead-in wire different layers is arranged, as shown in Figure 7, a plurality of leads is divided into two-layer making, be produced in the first conductive layer 7 and the second conductive layer 8, and the lead-in wire being arranged in the first conductive layer 7 is intervally arranged with the lead-in wire being arranged in the second conductive layer 8.
Lead-in wire described in the present invention can be gate signal line or data signal line.Adjacent legs adopts to be intervally arranged and is arranged on the design of different layers, can make less by the spacing of adjacent legs, thus be conducive to packed wiring space, realize narrow frame design.
In the present invention, can combine above-mentioned various execution mode use.Such as in the wire laying mode shown in Fig. 8, combine vertical line region 91, hatched example areas 92, narrow curved region 93 and wide curved region 94 arrangement.Here " narrow curved " and " wide curved " refers to " narrow " and " wide " of the distance in the bend unit I shown in Fig. 5 between the first vertical portion 601 and the second vertical portion 603.
For a lead-in wire, this lead-in wire can pass vertical line region 91, hatched example areas 92, narrow curved region 93 and wide curved region 94, and the part being arranged in vertical line region 91 is vertical curve, be arranged in that the part of hatched example areas 92 is oblique line, to be arranged in the part bending degree in narrow curved region 93 part bending degree that is less, that be arranged in wide curved region 94 comparatively large, as shown in Figure 9.This wire laying mode can realize the effect of peripheral circuit region resistance equiblibrium mass distribution on the whole, thus improves display image quality.
Present invention also offers a kind of substrate for display, described substrate for display comprises above-mentioned peripheral circuit provided by the present invention.
The present invention reduces the resistance difference in peripheral circuit between lead-in wire with the live width such as non-and the design of gradual change live width, can realize waiting resistance wiring, thus it is bad to improve because distance end lead resistance difference is excessive the displays such as picture that is that cause is uneven, horizontal and vertical striped.In addition, for the high PPI product that number of leads in peripheral circuit increases, the present invention, by extending transversely to wiring space of lead-in wire, reduce the vertical range shared by peripheral circuit, thus is conducive to realizing narrow frame design.
It should be noted that, above-mentioned cabling scenario provided by the present invention is not only applicable to substrate for display, is also applicable in the product that chip (IC), COF (Chip On Film) etc. need multilead to connect.
Present invention also offers a kind of display unit, described display unit comprises above-mentioned substrate for display provided by the present invention.As mentioned above, it is bad that display unit provided by the present invention effectively can improve the displays such as picture display is uneven, horizontal and vertical striped, thus have good display effect.
Be understandable that, the illustrative embodiments that above execution mode is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (10)
1. the peripheral circuit of a substrate for display, comprise: for the many lead-in wires with material of the integrated circuit of the circuit and outer peripheral areas that connect viewing area, it is characterized in that, the length of described a plurality of leads is incomplete same, and the width of described a plurality of leads is incomplete same; Wherein, the width of described a plurality of leads increases with the increasing lengths of lead-in wire.
2. peripheral circuit according to claim 1, is characterized in that, described a plurality of leads is arranged in order from the centre of lead-in wire region to both sides, is less than the wire length near both sides near middle wire length; Wherein, the wire widths near both sides is less than near middle wire widths.
3. peripheral circuit according to claim 2, is characterized in that, the width of each lead-in wire arranged to the direction of the either side both sides from centre, increases gradually with identical increment.
4. peripheral circuit according to claim 3, is characterized in that, the scope of described increment is 0.1um ~ 20um.
5. peripheral circuit according to claim 1 and 2, is characterized in that, as the length L of each lead-in wire
ndetermine, and the length L of certain setting lead-in wire
1and width W
1when determining, the width of all the other lead-in wires in a plurality of leads meets following formula:
W
n＝L
nW
1/L
1；
W
nbe the width of n-th lead-in wire, 1≤n≤N, N is pincounts.
6. peripheral circuit according to claim 1 and 2, is characterized in that, the line of one end of each lead-in wire is as the first line, and the line of the other end of each lead-in wire is as the second line, and described first line is parallel with described second line;
Described a plurality of leads is arranged in order from the centre of lead-in wire region to both sides, and each lead-in wire is straight line; Angle between arbitrary neighborhood two lead-in wire is γ; Setting is the 1st article with the perpendicular lead-in wire of described first line and go between, then n-th bar of lead-in wire is (n-1) γ with the described 1st article of angle gone between, and so, n-th width gone between meets following formula:
W
n＝W
1/sin[90-(n-1)γ]；
Wherein, n is positive integer; W
1for the width of the lead-in wire perpendicular with the first line.
7. peripheral circuit according to claim 2, is characterized in that, is curve near middle lead-in wire; Lead-in wire near both sides is straight line or curve;
Wherein, described curve is wave, arcuate line, jaggies or curved line.
8. peripheral circuit as claimed in any of claims 1 to 4, is characterized in that, described a plurality of leads is arranged with layer; Or described a plurality of leads bilayer is arranged, and adjacent lead-in wire different layers is arranged.
9. a substrate for display, is characterized in that, comprises the peripheral circuit in claim 1 to 8 described in any one.
10. a display unit, is characterized in that, comprises substrate for display according to claim 9.
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| CN201510431178.6A CN104952888A (en) | 2015-07-20 | 2015-07-20 | Peripheral circuit for display baseplate, display baseplate and display device |
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| CN201510431178.6A CN104952888A (en) | 2015-07-20 | 2015-07-20 | Peripheral circuit for display baseplate, display baseplate and display device |
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| CN104952888A true CN104952888A (en) | 2015-09-30 |
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