CN111292696B - GOA driving circuit, GOA array substrate, display panel and display device - Google Patents
GOA driving circuit, GOA array substrate, display panel and display device Download PDFInfo
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- CN111292696B CN111292696B CN202010124475.7A CN202010124475A CN111292696B CN 111292696 B CN111292696 B CN 111292696B CN 202010124475 A CN202010124475 A CN 202010124475A CN 111292696 B CN111292696 B CN 111292696B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The application discloses a GOA driving circuit, a GOA array substrate, a display panel and a display device, wherein the circuit comprises a GOA circuit module and a bus module; the GOA circuit module comprises a plurality of cascaded GOA circuit units; the bus module comprises a plurality of clock signal wiring units; the clock signal wiring unit comprises a first CK wiring subunit, a second CK wiring subunit and a CK corner connecting unit; the first end of the first CK wiring subunit is connected with the GOA circuit unit, and the second end of the first CK wiring subunit is connected with the first end of the CK corner connecting line unit; the second end of the CK corner connecting line unit is connected with the first end of the second CK routing subunit; the second end of the second CK routing subunit is used for connecting a clock signal module; CK turning wiring unit is solid metal line this application through setting up CK turning wiring unit into solid metal construction, has increased the effective metal line width of CK turning wiring unit (district of turning round), and then has reduced current density to reduce the temperature that produces taking place abnormal current.
Description
Technical Field
The application relates to the technical field of display, in particular to a GOA driving circuit, a GOA array substrate, a display panel and a display device thereof.
Background
With the improvement of the performance of the TFT, the GOA technology is currently and generally applied to the display panel, and has many advantages, so that Gate ICs (Gate IC chips) can be saved, the yield of customers can be improved, and a frameless design can be realized. For example, the majority of LCD TV products currently use the GOA technology, and as the image quality is improved, the Gate-On-array (GOA) circuit uses a plurality of TFT thin Film transistors, the channel length, source and drain of each TFT thin Film transistor are etched completely, and the final finish value is about the normal and stable operation function of the whole circuit, while the Tri-Gate architecture has the advantage of saving the number of COF (Chip On Film) and reducing the cost, taking the liquid crystal panel of 55UD model as an example, the number of COF (Chip On Film) adopted by normal-Gate can be reduced to 4 COF (Chip On Film) adopted by Tri-Gate. However, the GOA current of the Tri-gate is high, and the panel has a high temperature and a risk of screen burn-in when short-circuiting.
In the implementation process, the inventor finds that at least the following problems exist in the conventional technology: the traditional GOA circuit has high current density, and easily causes high panel temperature when abnormal current is generated.
Disclosure of Invention
Accordingly, it is desirable to provide a GOA driving circuit, a GOA array substrate, a display panel, and a display device thereof, which are directed to the problem that the conventional GOA circuit has a high current density and is likely to cause a high panel temperature when an abnormal current is generated.
In order to achieve the above object, an embodiment of the present invention provides a GOA driving circuit, including:
the GOA circuit module comprises a plurality of cascaded GOA circuit units;
the bus module comprises a plurality of clock signal wiring units; each clock signal wiring unit is connected with each GOA circuit unit in a one-to-one corresponding way;
the clock signal wiring unit comprises a first CK wiring subunit, a second CK wiring subunit and a CK corner connecting unit; the first end of the first CK wiring subunit is connected with the GOA circuit unit, and the second end of the first CK wiring subunit is connected with the first end of the CK corner connecting line unit; the second end of the CK corner connecting line unit is connected with the first end of the second CK routing subunit; the second end of the second CK routing subunit is used for connecting a clock signal module; the CK corner connecting line unit is a solid metal line.
In one embodiment, the first CK trace subunit is arranged along a horizontal direction; the second CK routing subunit is arranged along the vertical direction; the included angle of the CK corner connecting line unit is 90 degrees.
In one embodiment, the first CK trace subunit is a solid metal line; the second CK routing subunit is a solid metal wire.
In one embodiment, the line width of the first CK trace subunit is greater than the line width of the second CK trace subunit.
In one embodiment, the second CK trace subunit includes at least one CK signal lead; one end of the CK signal lead is connected with the second end of the CK corner connecting line unit, and the other end of the CK signal lead is connected with the clock signal module.
In one embodiment, the bus module further includes a low-frequency signal routing unit;
the low-frequency signal wiring unit comprises a first LC wiring subunit, a second LC wiring subunit and an LC corner connecting unit; the first end of the first LC routing subunit is connected with the GOA circuit unit, and the second end of the first LC routing subunit is connected with the first end of the LC corner connecting line unit; the second end of the LC corner connecting line unit is connected with the first end of the second LC routing subunit; the second end of the second LC routing subunit is used for connecting a low-frequency signal module; the LC corner connecting line unit is a solid metal line.
In one embodiment, the bus module further includes a power signal routing unit and a start signal routing unit;
the power signal wiring unit comprises a first VSS wiring subunit, a second VSS wiring subunit and a VSS corner connecting unit; the first end of the first VSS wiring subunit is connected with the GOA circuit unit, and the second end of the first VSS wiring subunit is connected with the first end of the VSS corner wiring unit; the second end of the VSS corner connecting line unit is connected with the first end of the second VSS wiring subunit; the second end of the second VSS wiring subunit is used for connecting the power signal module; the VSS corner connecting line unit is a solid metal line;
the opening signal wiring unit comprises a first STV wiring subunit, a second STV wiring subunit and an STV corner connecting unit; the first end of the first STV wiring subunit is connected with the GOA circuit unit, and the second end of the first STV wiring subunit is connected with the first end of the STV corner wiring unit; the second end of the STV corner connecting line unit is connected with the first end of the second STV wiring subunit; the second end of the second STV wiring subunit is used for connecting the starting signal module; the STV corner connecting line unit is a solid metal line.
On the other hand, the embodiment of the invention further provides a GOA array substrate, which comprises a substrate and the GOA driving circuit arranged on the substrate.
On the other hand, an embodiment of the present invention further provides a display panel, including the GOA array substrate according to any one of the above embodiments.
On the other hand, the embodiment of the invention also provides a display device, which comprises the display panel.
One of the above technical solutions has the following advantages and beneficial effects:
in each embodiment of the foregoing GOA driving circuit, the GOA circuit module includes a plurality of cascaded GOA circuit units; the bus module comprises a plurality of clock signal wiring units; each clock signal wiring unit is connected with each GOA circuit unit in a one-to-one corresponding way; the clock signal wiring unit comprises a first CK wiring subunit, a second CK wiring subunit and a CK corner connecting unit; the first end of the first CK wiring subunit is connected with the GOA circuit unit, and the second end of the first CK wiring subunit is connected with the first end of the CK corner connecting line unit; the second end of the CK corner connecting line unit is connected with the first end of the second CK routing subunit; the second end of the second CK routing subunit is used for connecting a clock signal module; the CK corner connecting line unit is a solid metal line, so that the current density of the clock signal wiring unit can be reduced, and the circuit is prevented from being damaged due to overhigh temperature when the clock signal current is abnormal. This application has increased the effective metal line width of first CK wiring subunit to CK turning wiring unit (district of turning round) through setting up CK turning wiring unit into solid metal construction, and then has reduced current density (can reduce about 50% current density) to reduce the temperature that takes place the abnormal current and produce.
Drawings
The present application will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a schematic diagram of a first structure of a GOA driving circuit according to an embodiment;
FIG. 2 is a schematic diagram of a second structure of a GOA driving circuit according to an embodiment;
FIG. 3 is a schematic diagram of a third structure of a GOA driving circuit according to an embodiment;
FIG. 4 is a schematic diagram illustrating a clock signal trace unit according to an embodiment;
fig. 5 is a schematic wiring diagram of a low-frequency signal routing unit in an embodiment.
Detailed Description
For a more clear understanding of the technical features, objects, and effects of the present application, specific embodiments of the present application will now be described in detail with reference to the accompanying drawings.
The technical solutions of the present application will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
The following detailed description of embodiments of the present application will be made with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present application, are given by way of illustration and explanation only, and are not intended to limit the present application.
Referring to fig. 1, fig. 2, fig. 3, fig. 4 and fig. 5, the following describes in detail a GOA driving circuit, a GOA array substrate thereof, a display panel and a display device according to an embodiment of the present disclosure with reference to the drawings.
The problem that the panel temperature is high when abnormal current is generated due to the fact that the current density of a traditional GOA circuit is high is solved. In one embodiment, as shown in fig. 1, there is provided a GOA driving circuit, including:
the GOA circuit module 11, the GOA circuit module 11 includes a plurality of cascaded GOA circuit units 110;
the bus module 13, the bus module 13 includes a plurality of clock signal routing units 130; each clock signal routing unit 130 is connected with each GOA circuit unit 102 in a one-to-one correspondence manner;
the clock signal routing unit 130 includes a first CK routing subunit 132, a second CK routing subunit 134, and a CK corner connection unit 136; a first end of the first CK routing subunit 132 is connected to the GOA circuit unit 110, and a second end is connected to a first end of the CK corner connecting unit 136; the second end of the CK corner connecting line unit 136 is connected to the first end of the second CK routing sub-unit 134; the second end of the second CK routing subunit 134 is used for connecting a clock signal module; the CK corner connecting unit 136 is a solid metal line.
Specifically, the GOA (Gate Driver On Array or Gate On Array) circuit module 11 may include a plurality of GOA circuit units 110. The GOA circuit unit 110 can be used to drive sub-pixels (e.g., red, green, or blue sub-pixels). The bus module 13 is used for transmitting signals required by the GOA circuit units. The bus module 13 may include a plurality of clock signal routing units 130, and the clock signal routing units 130 may be used for transmitting clock signals. The first CK trace subunit 132 refers to a section of CK signal trace; the second CK trace subunit 134 refers to a section of CK signal trace; the CK corner connecting line unit 136 refers to a connecting line for connecting between the first CK routing sub-unit 132 and the second CK routing sub-unit 134. A clock signal block refers to a device or block that generates a clock signal (CK signal). The CK corner connecting unit 136 is a solid metal line. The line width of the solid metal line can be determined according to the practical application condition.
It should be noted that the clock signal can be represented by high and low voltage levels.
Further, the GOA-based circuit module 11 includes a plurality of cascaded GOA circuit units 110; the bus module 13 includes a plurality of clock signal routing units 130; each clock signal routing unit 130 is connected to each GOA circuit unit 110 in a one-to-one correspondence manner, and then the clock signal routing unit 130 can transmit a clock signal (CK signal) to the GOA circuit units 110; the clock signal routing unit 130 includes a first CK routing subunit 132, a second CK routing subunit 134 and a CK corner connecting unit 136; a first end of the first CK routing subunit 132 is connected to the GOA circuit unit 110, and a second end is connected to a first end of the CK corner connecting unit 136; the second end of the CK corner connecting line unit 136 is connected to the first end of the second CK routing sub-unit 134; the second end of the second CK routing subunit 134 is used for connecting a clock signal module; the CK corner connecting unit 136 is a solid metal wire, so as to reduce the current density of the clock signal routing unit, and prevent the circuit from being damaged due to over-high temperature when the clock signal current is abnormal.
In the foregoing embodiment of the GOA driving circuit, the CK corner connecting unit is configured as a solid metal structure, so that the effective metal line width from the first CK routing subunit to the CK corner connecting unit (turning region) is increased, and further, the current density is reduced (by about 50% of the current density can be reduced), and the temperature generated when abnormal current occurs is reduced.
In one specific embodiment, as shown in fig. 1, the first CK trace subunit 132 is disposed along the horizontal direction; the second CK routing sub-unit 134 is disposed along the vertical direction; the included angle of the CK corner connecting unit 136 is 90 degrees.
Specifically, the first CK wiring subunit 132 is disposed along the horizontal direction, the second CK wiring subunit 134 is disposed along the vertical direction, the second end of the first CK wiring subunit 132 is connected to the first end of the CK corner wiring unit 136, the first end of the second CK wiring subunit 134 is connected to the second end of the CK corner wiring unit 136, and further an included angle between the first CK wiring subunit 132 and the second CK wiring subunit 134 is 90 degrees, that is, the included angle of the CK corner wiring unit 136 is 90 degrees.
In a specific embodiment, the first CK trace subunit is a solid metal wire; the second CK routing subunit is a solid metal wire.
In particular, the solid metal lines may be used to transmit clock signals (i.e., high and low potential level signals). The first CK routing subunit is set to be a solid metal wire; the second CK wiring subunit is set to be a solid metal wire, so that the effective metal wire width of the first CK wiring subunit and the effective metal wire width of the second CK wiring subunit are respectively increased, and the current density is effectively reduced.
In a specific embodiment, the line width of the first CK trace subunit is greater than the line width of the second CK trace subunit.
Specifically, the line width of the first CK routing subunit can be determined according to the actual application condition; the line width larger than the second CK wiring subunit can be determined according to the practical application condition. The line width of the first CK routing subunit is larger than that of the second CK routing subunit; the line width of the first CK routing subunit is equal to the line width of the first end side of the CK corner connecting unit; the line width of the second CK routing subunit is equal to the line width of the second end side of the CK corner connecting unit.
In a specific embodiment, the second CK trace subunit includes at least one CK signal lead; one end of the CK signal lead is connected with the second end of the CK corner connecting line unit, and the other end of the CK signal lead is connected with the clock signal module.
In one example, the second CK trace subunit includes eight CK signal leads; one end of each CK signal lead is connected with the second end of each CK corner connecting unit, and the other end of each CK signal lead is connected with the clock signal module.
Specifically, the CK signal leads are arranged in parallel at intervals.
In one embodiment, as shown in fig. 2, a GOA driving circuit is provided, which includes a GOA circuit module 21 and a bus module 23: the GOA circuit module 21 includes a plurality of cascaded GOA circuit units 210; the bus module 23 includes a plurality of clock signal routing units 230; each clock signal routing unit 230 is connected to each GOA circuit unit 210 in a one-to-one correspondence. The bus module 23 further includes a low frequency signal routing unit 240; the low frequency signal routing units 240 are respectively connected to the GOA circuit units 210.
The clock signal routing unit 230 includes a first CK routing subunit 232, a second CK routing subunit 234 and a CK corner connecting unit 236; a first end of the first CK routing subunit 232 is connected to the GOA circuit unit 210, and a second end is connected to a first end of the CK corner connecting unit 236; a second end of the CK corner connecting unit 236 is connected to a first end of the second CK routing sub-unit 234; a second end of the second CK routing subunit 234 is used for connecting a clock signal module; CK corner link unit 236 is a solid metal line.
The low frequency signal routing unit 240 includes a first LC routing subunit 242, a second LC routing subunit 244 and an LC corner connection unit 246; a first end of the first LC routing sub-unit 242 is connected to the GOA circuit unit 210, and a second end is connected to a first end of the LC corner connecting unit 246; a second end of the LC corner link unit 246 is connected to a first end of the second LC routing sub-unit 244; a second end of the second LC routing subunit 244 is used for connecting a low-frequency signal module; the LC corner link elements 246 are solid metal lines.
Specifically, the low frequency signal routing unit 240 may be used to transmit a low frequency signal (i.e., LC signal). The first LC trace subunit 242 refers to a segment of LC signal trace; the second LC trace subunit 244 refers to a segment of LC signal trace; the LC corner connection unit 246 refers to a connection line for connecting between the first LC routing sub-unit 242 and the second LC routing sub-unit 244. A low frequency signal module refers to a device or module that generates a low frequency signal (LC signal). The LC corner link elements 246 are solid metal lines. The line width of the solid metal line can be determined according to the practical application condition.
Further, a first end of the first LC routing sub-unit 242 is connected to the GOA circuit unit 210, and a second end is connected to a first end of the LC corner connecting unit 246; a second end of the LC corner link unit 246 is connected to a first end of the second LC routing sub-unit 244; a second end of the second LC routing subunit 244 is used for connecting a low-frequency signal module; and the LC corner link elements 246 are provided as solid metal line structures. And then can reduce the current density of low frequency signal line unit, prevent that the low frequency signal current from unusual, causing the high temperature and damaging the circuit.
In the above embodiment, the LC corner connecting unit is configured as a solid metal structure, so that the effective metal line width from the first LC routing sub-unit to the LC corner connecting unit (the turning region) is increased, the current density is reduced (the current density can be reduced by about 50%), and the temperature generated when abnormal current occurs is reduced.
In one example, the low frequency signal trace units may include LC1 signal trace units and LC2 signal trace units. The LC1 signal routing units are respectively connected with the GOA circuit units; the LC2 signal routing units are respectively connected to the GOA circuit units.
In one embodiment, as shown in fig. 3, a GOA driving circuit is provided, which includes a GOA circuit module 31 and a bus module 33: the GOA circuit module 31 includes a plurality of cascaded GOA circuit units 310; the bus module 33 includes a plurality of clock signal routing units 330; each clock signal routing unit 330 is connected to each GOA circuit unit 310 in a one-to-one correspondence. The bus module 33 further includes a low frequency signal routing unit 340; the low frequency signal routing unit 340 is connected to each of the GOA circuit units 310. The bus module 33 further includes a power signal routing unit 350 and a start signal routing unit 360; the power signal routing unit 350 is connected to each of the GOA circuit units 310; the start signal routing unit 360 is connected to each of the GOA circuit units 310.
The clock signal routing unit 330 includes a first CK routing subunit 332, a second CK routing subunit 334, and a CK corner connection unit 336; a first end of the first CK routing sub-unit 332 is connected to the GOA circuit unit 310, and a second end is connected to a first end of the CK corner connecting unit 336; the second end of the CK corner connecting unit 336 is connected to the first end of the second CK routing sub-unit 334; the second end of the second CK routing subunit 334 is used for connecting a clock signal module; CK corner wiring unit 336 is a solid metal line.
The low frequency signal routing unit 340 includes a first LC routing sub-unit 342, a second LC routing sub-unit 344 and an LC corner connection unit 346; a first end of the first LC routing subunit 342 is connected to the GOA circuit unit 310, and a second end is connected to a first end of the LC corner connecting unit 346; a second end of the LC corner wiring unit 346 is connected to a first end of the second LC routing sub-unit 344; a second end of the second LC routing sub-unit 344 is used for connecting a low frequency signal module; the LC corner link cells 346 are solid metal lines.
The power signal routing unit 350 includes a first VSS routing subunit 352, a second VSS routing subunit 354 and a VSS corner connecting unit 356; a first terminal of the first VSS routing subunit 352 is connected to the GOA circuit unit 310, and a second terminal is connected to a first terminal of the VSS corner connecting unit 356; a second end of the VSS corner connecting line unit 356 is connected to a first end of the second VSS routing subunit 354; the second end of the second VSS routing subunit 354 is used for connecting the power signal module; the VSS corner link cells 356 are solid metal lines.
The opening signal routing unit 360 includes a first STV routing subunit 362, a second STV routing subunit 364 and an STV corner connection unit 366; a first end of the first STV routing subunit 362 is connected to the GOA circuit unit 310, and a second end is connected to a first end of the STV corner connection unit 366; a second end of the STV corner connection unit 366 is connected to a first end of the second STV routing subunit 364; the second end of the second STV routing subunit 364 is used for connecting the start signal module; the STV corner wiring unit 366 is a solid metal wire.
Specifically, the power signal routing unit 350 may be used to transmit a power signal (i.e., a VSS signal). The first VSS routing subunit 352 refers to a section of VSS signal routing; the second VSS routing subunit 354 refers to a section of VSS signal routing; the VSS corner wiring unit 356 refers to a wiring for connecting between the first VSS wiring subunit 352 and the second VSS wiring subunit 354. The power signal module refers to a device or a module that generates a power signal (VSS signal). The VSS corner connection unit 356 is a solid metal line; the line width of the solid metal line can be determined according to the practical application condition.
The start signal routing unit 360 can be used to transmit a start signal (i.e., an STV signal). The first STV trace subunit 362 refers to a segment of STV signal trace; the second STV trace subunit 364 refers to a segment of STV signal trace; the STV corner connection unit 366 refers to a connection line for connecting between the first STV trace subunit 362 and the second STV trace subunit 364. The turn-on signal block refers to a device or block that generates a turn-on signal (STV signal). The STV corner connection unit 366 is a solid metal wire; the line width of the solid metal line can be determined according to the practical application condition.
In the above embodiment, the VSS corner connection unit is configured as a solid metal structure, so that the effective metal line width from the first VSS wiring subunit to the VSS corner connection unit (turning region) is increased; the effective metal wire width from the first STV wiring subunit to the STV corner wiring unit (turning area) is increased by setting the STV corner wiring unit to be a solid metal structure; thereby reducing the current density (which can be reduced by about 50%) and reducing the temperature at which abnormal current generation occurs.
In one example, as shown in fig. 4, a wiring diagram of the clock signal routing unit is shown. By arranging the CK corner connecting unit of the solid metal structure between the first CK routing unit and the second CK routing unit, the current density can be reduced (about 50% of the current density can be reduced), and the temperature generated when abnormal current occurs can be reduced. Compared with the traditional hollow connecting line design of digging Slit and the like, the CK corner connecting line units are filled by solid filling, so that the current density of the clock signal wiring unit can be reduced (the current density of the traditional hollow connecting line design of digging Slit and the like is 1.664 to 10)-4(ii) a The current density after the solid filling is 8.588 x 10-5) The temperature generated when the current is abnormal is reduced.
In one example, as shown in fig. 5, a wiring diagram of the low frequency signal routing unit is shown. By arranging the LC corner connecting unit of the solid metal structure between the first LC wiring unit and the second LC wiring unit, the current density can be reduced (about 50% of the current density can be reduced), and the temperature generated when abnormal current occurs can be reduced. Compare traditional hollow wiring designs such as dig Slit, fill up through solid and set up LC corner wiring unit, increase effective line width, and then can reduce the current density that low frequency signal walked the line unit to reduce the temperature that produces when the electric current is unusual.
In one embodiment, a GOA array substrate is further provided, which includes a substrate, and the GOA driving circuit provided on the substrate.
The substrate may be, but not limited to, an amorphous silicon array substrate or an indium gallium zinc oxide array substrate.
Specifically, by arranging the GOA circuit module and the bus module on the substrate and arranging the CK corner connecting line unit of the solid metal structure between the first CK wiring unit and the second CK wiring unit, the effective metal line width from the first CK wiring subunit to the CK corner connecting line unit (turning region) and the effective metal line width from the second CK wiring subunit to the CK corner connecting line unit (turning region) are increased, so that the current density is reduced (about 50% of the current density can be reduced), and the temperature generated when abnormal current occurs is reduced.
For the specific definition of the GOA array substrate, reference may be made to the above definition of the GOA driving circuit, which is not described herein again.
In one embodiment, a display panel is also provided, and the display panel includes the GOA array substrate according to any one of the above embodiments.
For specific limitations of the display panel, reference may be made to the limitations of the GOA array substrate and the GOA driving circuit, which are not described herein again.
It should be noted that the present application is particularly applicable to display panels with Tri-gate GOA architecture and higher GOA current consumption, but is not limited thereto, and can be applied to various current-driven display panels, such as display panels with normal-gate GOA architecture.
In one embodiment, a display device is also provided, which includes the display panel as described above.
In one embodiment, the display panel may be, but is not limited to, an OLED display panel, a Micro LED display panel, a Mini LED display panel, or a μ LED display panel.
For specific limitations of the display device, reference may be made to the limitations of the display panel, the GOA array substrate and the GOA driving circuit, which are not described herein again.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A GOA driving circuit, comprising:
the GOA circuit module comprises a plurality of cascaded GOA circuit units;
the bus module comprises a plurality of clock signal wiring units; each clock signal routing unit is connected with each GOA circuit unit in a one-to-one corresponding mode;
the clock signal routing unit comprises a first CK routing subunit, a second CK routing subunit and a CK corner connecting unit; the first end of the first CK routing subunit is connected with the GOA circuit unit, and the second end of the first CK routing subunit is connected with the first end of the CK corner connecting line unit; the second end of the CK corner connecting line unit is connected with the first end of the second CK routing subunit; the second end of the second CK routing subunit is used for connecting a clock signal module; and the CK corner connecting line unit is a solid metal line.
2. The GOA driving circuit according to claim 1, wherein the first CK trace sub-unit is arranged along a horizontal direction; the second CK routing subunit is arranged along the vertical direction; the included angle of the CK corner connecting line unit is 90 degrees.
3. The GOA driving circuit according to claim 2, wherein the first CK routing sub-unit is a solid metal wire; the second CK routing subunit is a solid metal wire.
4. The GOA driving circuit according to claim 3, wherein the line width of the first CK trace subunit is greater than the line width of the second CK trace subunit.
5. The GOA driving circuit according to claim 4, wherein the second CK routing sub-unit comprises at least one CK signal lead; one end of the CK signal lead is connected with the second end of the CK corner connecting line unit, and the other end of the CK signal lead is connected with the clock signal module.
6. The GOA driving circuit according to any one of claims 1 to 5, wherein the bus module further comprises a low frequency signal routing unit;
the low-frequency signal wiring unit comprises a first LC wiring subunit, a second LC wiring subunit and an LC corner connecting unit; the first end of the first LC routing subunit is connected with the GOA circuit unit, and the second end of the first LC routing subunit is connected with the first end of the LC corner connecting line unit; the second end of the LC corner connecting line unit is connected with the first end of the second LC routing sub-unit; the second end of the second LC routing subunit is used for connecting a low-frequency signal module; the LC corner connecting line unit is a solid metal line.
7. The GOA driving circuit according to claim 6, wherein the bus module further comprises a power signal routing unit and a start signal routing unit;
the power signal wiring unit comprises a first VSS wiring subunit, a second VSS wiring subunit and a VSS corner connecting unit; the first end of the first VSS wiring subunit is connected with the GOA circuit unit, and the second end of the first VSS wiring subunit is connected with the first end of the VSS corner connecting line unit; the second end of the VSS corner connecting line unit is connected with the first end of the second VSS wiring subunit; the second end of the second VSS wiring subunit is used for connecting a power signal module; the VSS corner connecting line unit is a solid metal line;
the starting signal wiring unit comprises a first STV wiring subunit, a second STV wiring subunit and an STV corner connecting unit; the first end of the first STV wiring subunit is connected with the GOA circuit unit, and the second end of the first STV wiring subunit is connected with the first end of the STV corner wiring unit; the second end of the STV corner connecting line unit is connected with the first end of the second STV wiring subunit; the second end of the second STV wiring subunit is used for connecting an opening signal module; the STV corner connecting line unit is a solid metal line.
8. A GOA array substrate, comprising a substrate and the GOA driving circuit of any one of claims 1 to 7 disposed on the substrate.
9. A display panel comprising the GOA array substrate of claim 8.
10. A display device characterized by comprising the display panel according to claim 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010124475.7A CN111292696B (en) | 2020-02-27 | 2020-02-27 | GOA driving circuit, GOA array substrate, display panel and display device |
| PCT/CN2020/084619 WO2021169005A1 (en) | 2020-02-27 | 2020-04-14 | Goa drive circuit and goa array substrate having same, display panel, and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010124475.7A CN111292696B (en) | 2020-02-27 | 2020-02-27 | GOA driving circuit, GOA array substrate, display panel and display device |
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| Publication Number | Publication Date |
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| CN111292696A CN111292696A (en) | 2020-06-16 |
| CN111292696B true CN111292696B (en) | 2021-07-06 |
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| CN202010124475.7A Active CN111292696B (en) | 2020-02-27 | 2020-02-27 | GOA driving circuit, GOA array substrate, display panel and display device |
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| Country | Link |
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| CN (1) | CN111292696B (en) |
| WO (1) | WO2021169005A1 (en) |
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| CN113589609B (en) * | 2021-07-16 | 2023-04-04 | Tcl华星光电技术有限公司 | GOA circuit, display panel and display device |
| CN114242018B (en) * | 2021-12-28 | 2023-05-23 | 深圳创维－Rgb电子有限公司 | GOA driving circuit, GOA driving method and display panel |
| CN114974164B (en) * | 2022-08-02 | 2022-12-09 | 惠科股份有限公司 | Array substrate and display panel |
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| WO2021169005A1 (en) | 2021-09-02 |
| CN111292696A (en) | 2020-06-16 |
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