JP2000174595A - Clock generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a clock generating circuit that corrects deterioration in a clock signal characteristic caused by signals propagated through wiring so as to prevent clock skew. SOLUTION: Internal clock generating circuits 70-1, 70-2,..., 70-n respectively compare clock signals extracted from terminals t1, t2,..., tn of a clock signal wire 30 with reference voltages v1, v2,... vn set to different levels depending on the delay of the clock signals, and generate internal clock signals ck1, ck2,..., ckn according to the comparison result. Then the internal clock signals ck1, ck2,..., ckn can be synchronized with each other so as to correct deterioration in the clock caused by resistance and capacitance of the clock signal wire 30. A distributed constant of the clock signal wire 30 can easily be estimated by wiring a ground wire or a power wire over the clock signal wire 30, interference between clock signals and other signals can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal whose characteristics have deteriorated due to propagation on a signal line.
The present invention relates to a clock generation circuit that supplies a corrected clock signal whose deterioration has been corrected.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, a system clock signal is used to unify operation timings of different partial circuits on a substrate. By controlling the operation timing of each partial circuit based on the rising edge or the falling edge of the system clock signal, it is possible to synchronize the operations of different partial circuits.

As the speed of semiconductor devices has increased, the frequency of clock signals has been increasing. Due to the capacitance and resistance of the signal wiring for transmitting the high-frequency clock signal on the semiconductor chip, the characteristics of the rising edge or the falling edge of the clock signal deteriorate. When a clock signal whose characteristics have deteriorated is input to a logic circuit having a predetermined logic threshold, a clock signal delay called clock skew occurs. When the clock skew occurs, the operation timing between different partial circuits is disturbed, causing a malfunction.

Until now, various measures have been taken to prevent the occurrence of clock skew. For example,
Develop a manufacturing process with small wiring capacitance and wiring resistance, find a wiring pattern that minimizes wiring capacitance, optimize wiring routing on the board, equalize signal delays, and further devise circuits. Prevent clock skew. For example, a buffer may be provided in the middle of the wiring to minimize the amount of signal delay, or a new clock may be generated by detecting an intermediate timing between two different paths with different clock delays. The method of has been taken.

FIG. 4 shows a configuration example of a conventional clock generation circuit for correcting clock skew caused by wiring resistance and parasitic capacitance. As shown, this clock generation circuit includes a reference clock generation circuit 100, a detection circuit 110, a delay circuit 120, and a clock supply circuit 130.
It consists of. The clock supply circuit 130 includes a clock signal CL for controlling the operation timing of the circuit.
Generate K. The delay circuit 120 delays the clock signal CLK according to the control signal S _C from the detection circuit 110, and supplies the delayed clock signal to the input / output circuit 140 and the like as the internal clock signal CK. Note that the signal wiring from the clock supply circuit 130 to the delay circuit 120 causes a delay of the clock signal, that is, a clock skew. The clock skew is caused by the clock supply circuit 130
Since it varies depending on the wiring distance from the circuit to the destination circuit, the clock skew varies depending on the location of the destination circuit on the substrate. Therefore, when controlling the operation timing with this clock, a sufficient margin is usually taken. Need, which limits the operating speed of the destination circuit.

[0006] The detection circuit 110 receives the reference clock signal RC.
Input node signal wiring distance to the supply node ND _C of ND _A and the internal clock signal CK of K are arranged in a similar location. That is, the reference clock signal RCK is location on the substrate of the detection circuit 110 as the propagation time and the internal clock signal CK from the input node ND _A until the detection circuit 110 is equal propagation time until the detection circuit 110 from the node ND _C Is determined. Detection circuit 110 detects the phase shift between the reference clock and the internal clock signal to be input, and outputs a control signal S _C corresponding to the phase shift of the clock signal to the delay circuit 120.

FIG. 5 shows a signal waveform of each part when the clock generation circuit shown in FIG. 4 operates. FIG. 5 (a)
Reference clock RCK, FIG. 4B shows a reference clock signal RCK ′ input to the detection circuit 110, FIG. 4C shows an internal clock signal CK ′ input to the detection circuit 110, and FIG. Each waveform of the internal clock signal supplied from the circuit 120 is shown.

[0008] As described above, the reference clock RCK input node detection circuit from the input node ND _C of the wiring distance and the internal clock signal CK from ND _A to the detection circuit 110 1
10 so that the wiring distances up to 10 are equal.
Is set, it is considered that the wiring resistance and the parasitic capacitance of the signal wiring are equal. Therefore, the delay of the reference clock RCK on the signal line up to the detection circuit and the delay of the internal clock signal CK on the signal line up to the detection circuit 110 are substantially the same. By the detection circuit 110,
Detecting a phase shift between the input reference clock signal and the internal clock signal, in accordance with the detection result, generates a control signal S _C that controls the delay time of the delay circuit 120 t _d, and sends to the delay circuit 120. This feedback control, the internal clock signal CK the phase of the output node ND _C is
It is controlled so that it substantially matches the reference clock RCK.
Therefore, the clock supply circuit 130 supplies the delay circuit 120
The clock delay generated in the signal lines up to the above is corrected, and the operation margin in the partial circuits arranged at different places on the substrate, for example, the input / output circuit 140 shown in FIG. 4 can be reduced, and the operation speed can be improved. realizable.

[0009]

By the way, in the above-mentioned conventional method, the detection circuit 110 always operates with the reference clock RC.
It must be placed in the middle point between the input node ND _C input node ND _A and the internal clock signal CK of K. In a complicated logic circuit such as a microprocessor, a clock signal is supplied to a large number of destinations, and wiring is increased. The input nodes of the internal clock signal CK from the wire length and detection circuit 110 of the delay time of the signal from the input node ND _A reference clock signal RCK to the detection circuit 110 ND
Since it is determined by the wiring length up to _C , if another wiring overlaps with these wirings and the capacitance or the like changes, the delay time of the signal generated on the wiring changes, making it impossible to obtain the desired timing . Furthermore, the routing of the clock signal wiring leads to a complicated layout, resulting in an increase in chip size. Further, even if the prevention of clock skew can be realized by simulation, the actual I
The C chip has a disadvantage that a deviation from the simulation occurs, and the occurrence of clock skew cannot be prevented as designed.

The present invention has been made in view of the above circumstances, and has as its object to correct deterioration of clock characteristics due to wiring resistance and parasitic capacitance of a clock signal, and to prevent malfunction of a semiconductor device due to clock skew. A clock generation circuit is provided.

[0011]

In order to achieve the above object, a clock generation circuit according to the present invention comprises at least one reference signal generation circuit for generating a reference signal corresponding to the deterioration of the characteristic, And a comparison circuit that compares the level of the clock signal with the reference signal and the corrected clock signal is output from the comparison circuit.

Further, the present invention is a clock generation circuit for generating a corrected clock signal in which the rising / falling characteristics have been degraded by propagating through a signal line and correcting the degradation, wherein the clock generation circuit responds to the control signal. At least one reference signal generating circuit for generating a reference signal, a comparing circuit for comparing the level of the clock signal having a deterioration in signal propagation with the level of the reference signal, and generating a reference clock signal having a predetermined phase. A reference clock generation circuit, compares the phase of the output signal of the comparison circuit with the reference clock signal, and controls the control signal so that the phase error between the output signal of the comparison circuit and the reference clock signal becomes a predetermined value. And a control circuit for controlling the reference signal output from the reference signal generation circuit, and the control circuit Positive clock signal is output.

In the present invention, preferably, the reference signal generating circuit includes a reference voltage source for supplying a reference voltage whose level is set in accordance with the deterioration of the characteristic, a reference voltage source and a ground potential. And a reference current source for supplying a reference current having a level set in accordance with the deterioration of the characteristic to the resistance element.

Further, in the present invention, preferably, a ground line or a power supply line is provided so as to cover the signal line for transmitting the clock signal.

According to the present invention, a clock signal, whose rising or falling characteristics have deteriorated by propagating through a signal line, is compared with a predetermined reference signal, for example, a reference voltage, and at a timing according to the comparison result. Since the correction clock is generated, the clock skew generated by the signal line is corrected, and a correction clock having a desired phase is generated. Further, by detecting a phase difference between the generated correction clock signal and a predetermined reference clock signal, and adjusting the reference signal according to the phase difference, the reference signal is adjusted according to the variation of the semiconductor circuit generated in a manufacturing process or the like. The signal is automatically controlled, the influence of the variation can be suppressed, and the phase accuracy of the correction clock signal can be improved.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a clock generation circuit according to the present invention. As shown in the figure, the clock generation circuit of this embodiment includes n clock supply circuits 10, buffer circuits 20, clock signal wirings 30, ground wirings 40, a reference voltage source 50, a reference current source 60, and n (n is a positive integer). , 70-n
It consists of.

The clock supply circuit 10 generates a clock signal having a desired frequency and inputs the clock signal to the buffer circuit 20. The buffer circuit 20 supplies the clock signal CLK in which the waveform of the input clock signal is adjusted to the clock signal wiring 30.
To enter. In the present embodiment, the buffer circuit 20
A buffer amplifier having a predetermined slew rate.
As a result, the rising or falling characteristics of the clock signal input to the clock signal extension 30 are substantially determined by the slew rate of the buffer circuit 20, and the effects of circuit variations are reduced. The clock signal CLK output from the buffer circuit 20 is propagated through the clock signal wiring 30, and the terminals t1, t2,.
The correction clock generation circuits 70-1 and 70-
2, ..., 70-n.

A reference signal generating circuit is formed by the reference voltage source 50, the reference current source 60, and the n resistance elements R1, R2,..., Rn connected in series between the reference voltage source 50 and the reference current source 60. Be composed. The reference signal generation circuit,
, vn are generated and supplied to the correction clock generation circuits 70-1, 70-2, ..., 70-n, respectively. Here, by adjusting the supply voltage of the reference voltage source 50 and the supply current of the reference current source 60,
The offsets and gradients of the generated reference voltages v1, v2,... Vn can be adjusted.

Correction clock generation circuits 70-1 and 70-
, 70-n are terminals t1, t2,.
n and a reference voltage v1, v2,
, Vn, and outputs n corrected clock signals ck1, ck2,..., Ckn, respectively, according to the comparison result. The correction clock signals ck1, ck2,.
Symbols n are synchronizing signals having the same phase and are supplied to different internal circuits. The operation timings of these internal circuits are controlled to synchronize the operations of the internal circuits.

As shown in FIG. 1, ground wiring 40 is provided so as to cover clock signal wiring 30 on the semiconductor substrate. Thereby, the clock signal wiring 30 and the ground wiring 40
And a parasitic capacitance between them. By adjusting the wiring pattern of the clock signal wiring 30, the wiring resistance generated on the wiring and the parasitic capacitance between the clock signal wiring 30 and the ground wiring 40 can be made constant. Further, by making the pattern of the clock signal wiring 30 uniform, the wiring resistance and the parasitic capacitance per unit wiring length can be made constant, and the wiring resistance and the parasitic capacitance can be estimated with high accuracy. Note that the power supply voltage V
Almost the same effect can be obtained by wiring a power supply line for supplying _CC so as to cover the clock signal wiring 30.
By performing such wiring, mutual interference between the clock signal and other signals can be reduced.

Due to the wiring resistance of the clock signal line 30 and the parasitic capacitance generated between the clock signal line 30 and the ground line, the clock signal line 30 can be equivalently regarded as the distributed constant circuit shown in FIG. That is, when the clock signal CLK is propagated through the clock signal wiring 30, a certain delay occurs per unit length of the signal wiring. Therefore, the plurality of terminals t1, t2,.
The delay amount of the clock signal output from n can be estimated.
Correction clock generation circuits 70-1, 70-2, ..., 70-
n, the clock signals extracted from the terminals t1, t2,..., tn are compared with reference signals set according to the delay amounts of the respective clocks, and the corrected clock signals ck1, ck2,. , Ckn. Thereby, the corrected clock signal c having the same phase is obtained.
k1, ck2,..., ckn are generated, and circuits that operate in accordance with these correction clock signals can be operated at the same timing.

FIG. 2 shows a correction clock generation circuit 70-1,
It is a waveform diagram which shows operation | movement of 70-2, ..., 70-n. FIG. 2A shows clock signals extracted from terminals t1, t2,..., Tn and reference signals set according to the respective clock signals. FIG. 7B shows the correction clock signals ck1, ck2,..., C generated by the correction clock generation circuits 70-1, 70-2,.
kn is shown.

As shown in FIG. 2A, the clock signal C
When LK is input, the terminal t of the clock signal wiring 30
Clock signals having different delay amounts are output from 1, t2,..., Tn. Further, the reference voltages v1, v2 having different levels according to the delay amount of each clock.
, vn are generated. These reference voltages are used as correction clock generation circuits 70-1, 70-2,.
Respectively. That is, the correction clock generation circuit 7
, 70-n are equivalently logic circuits using the reference voltages v1, v2,..., Vn as logic thresholds, respectively.

As the simplest example, when all of the correction clock generation circuits 70-1, 70-2,..., 70-n are constituted by comparison circuits, the correction clock signal ck1 output by each correction clock generation circuit is provided. , Ck
The waveforms of 2,..., Ckn are as shown in FIG.
As shown, in each correction clock generation circuit, the level of the input clock signal is compared with the level of the reference voltage. Here, assuming that a low-level signal is output when the level of the clock signal is lower than the reference voltage, and a high-level signal is output when the level of the clock signal is higher than the reference voltage, FIG. .., Ckn are obtained. As described above, since the level of the reference voltage input to each comparison circuit is set according to the delay amount of each clock signal, the corrected clock signals ck1, ck2,. Is done.

As shown in FIG. 2A, the reference voltages v1,
Since v2,..., vn are respectively set in accordance with the rising edge of the clock signal, the generated correction clock signals ck1, ck2,
..., the falling edges of ckn do not match. When synchronizing with the rising edges of the corrected clock signals ck1, ck2,..., Ckn, only the rising edge affects the operation timing of each partial circuit, so that even if the falling edge is shifted, it does not affect the circuit operation. When the synchronization of the falling edge is also required, the correction clock generation circuits 70-1, 70-2,..., 70-n shown in FIG. In this case, each flip-flop is configured by, for example, a monostable circuit that raises an output signal in response to a rising edge of an input signal, and then lowers the output signal after a certain time has elapsed from the rising edge of the input signal. can do. In addition, it is also possible to generate a corrected clock signal with the same falling edge by generating the inverted clock signal by the buffer circuit 20 and using the inverted clock signal as a reference clock signal through different paths.

As described above, according to the present embodiment, the correction clock generating circuits 70-1, 70-2,.
0-n are terminals t1 and t of the clock signal wiring 30, respectively.
, Tn and the reference voltages v1, v2,..., Vn set at different levels, and the corrected clock signals ck1, ck2,. , The correction clock signals ck1, ck2,..., Ckn can be synchronized, and the clock skew caused by the wiring resistance and the parasitic capacitance of the clock signal wiring 30 can be corrected. Furthermore, by arranging a ground line or a power supply line so as to cover the clock signal line 30, the distribution constant of the clock signal line 30 can be easily estimated, the accuracy of the reference voltage can be improved, and the clock signal and other signals can be separated. Interference can be reduced.

Second Embodiment FIG. 3 is a circuit diagram showing a second embodiment of the clock generation circuit according to the present invention. As shown, the basic configuration of the clock generation circuit of this embodiment is almost the same as that of the first embodiment shown in FIG. However, in this embodiment, a detection circuit for detecting a phase difference between the generated correction clock signal and a predetermined reference clock is provided, and a reference voltage source and a reference voltage for generating a reference voltage are provided in accordance with the detected phase difference. By controlling the current source, each correction clock generation circuit 70-
1, 70-2,..., 70-n
Since 1, v2,..., Vn are automatically controlled, it is possible to suppress circuit variations. Hereinafter, the configuration and operation of the clock generation circuit of the present embodiment will be described in more detail with reference to the circuit diagram of FIG.

As shown in FIG. 3, the clock generation circuit of the present embodiment comprises a clock supply circuit 10, a buffer circuit 2
0, the clock signal wiring 30, the ground wiring 40, the correction clock generating circuits 70-1, 70-2,.
The reference clock generation circuit 100 and the detection circuit 80-1,
80-2 are provided. Further, in the present embodiment,
The reference voltage source 50a and the reference current source 60a
The supply voltage and the supply current are controlled according to the output signals of -1 and 80-2, respectively. The reference voltage source 50a,
The components other than the reference current source 60a, the detection circuits 80-1 and 80-2, and the reference clock generation circuit 100 have substantially the same configuration as the first embodiment shown in FIG.
In FIG. 3, the same components are denoted by the same reference numerals. Hereinafter, the reference voltage source 50a, the reference current source 60a,
The description will focus on the detection circuits 80-1 and 80-2 and the reference clock generation circuit 100.

The reference clock generation circuit 100 generates a reference clock RCK and supplies it to the detection circuits 80-1 and 80-2. The detection circuit 80-1 outputs the reference clock R
CK is compared with the correction clock signal ck1 generated by the correction clock generation circuit 70-1 to detect a timing error between these clock signals. Detection circuit 80-2
Is the reference clock RCK and the correction clock generation circuit 70-
n with the corrected clock signal ckn generated by
An error in the timing of these clock signals is detected.
Therefore, the detection circuits 80-1 and 80-2 can be configured by, for example, a phase comparison circuit.

The detection circuits 80-1 and 80-2 control the control signal S in accordance with the phase error of each input clock signal.
_C1 and S _C2 are output. Since the supply voltage _Vref of the reference voltage source 50a is adjusted according to the control signal S _C1 , the reference voltages v1, generated by the resistance elements R1, R2,.
The offset voltages of v2,..., vn are controlled. on the other hand,
The supply current I of the reference current source 60a according to the control signal S _{C2
Since ref} is adjusted, the resistance elements R1, R2,.
, The gradient of the reference voltages v1, v2,. When variations occur in the semiconductor elements on the substrate in the manufacturing process, for example, the resistance value of the resistance element deviates from the design value. In this case, in the clock generation circuit of the first embodiment, the phases of the generated correction clock signals ck1, ck2,..., Ckn may be shifted from each other. On the other hand, in the clock generation circuit according to the present embodiment, the reference voltage V _ref and the reference current I _ref supplied by the reference voltage source 50a and the reference current source 60a are synchronized with the reference clock RCK generated by the reference clock generation circuit 100. By controlling _ref , the correction clock signals ck1, ck2,.
Are automatically adjusted, and the influence of the variation can be suppressed.

In the present embodiment, similarly to the first embodiment, by arranging a ground line or a power supply line so as to cover the clock signal wiring 30, the distribution constant of the clock signal wiring 30 can be easily reduced. Can be estimated to
The reference voltage can be generated with high accuracy. Further, such wiring can reduce interference between the clock signal and other signals. By controlling the level of the reference voltage, the correction clock generation circuits 70-1 and 70-1
−2,..., 70-n
Either the rising edge or the falling edge of 1, ck2,..., Ckn can be matched. Further, the monostable circuit is connected to each correction clock generation circuit 70-
, 70-n, it is possible to generate corrected clock signals ck1, ck2,..., Ckn in which both the rising edge and the falling edge match. In addition, it is also possible to generate a corrected clock signal with the same falling edge by generating the inverted clock signal by the buffer circuit 20 and using the inverted clock signal as a reference clock signal through different paths.

[0032]

As described above, according to the clock signal generating circuit of the present invention, while the increase in the circuit layout is minimized, the clock signal generating circuit is generated by the wiring resistance and the parasitic capacitance of the signal line in the semiconductor circuit. Clock skew can be eliminated, and signal interference can be prevented. Further, there is an advantage that the clock skew can be automatically corrected according to the variation generated in the manufacturing process and the like, and the phase of the corrected clock generated without being affected by the variation of the process can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a clock generation circuit according to the present invention.

FIG. 2 is a waveform chart showing an operation of the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the clock generation circuit according to the present invention.

FIG. 4 is a circuit diagram illustrating an example of a conventional clock generation circuit.

FIG. 5 is a waveform chart showing an operation of the conventional clock generation circuit.

[Explanation of symbols]

10 clock supply circuit, 20 buffer circuit, 30
Clock signal wiring, 40 ground wiring, 50 reference voltage source, 60 reference current source, 70-1, 70-2,.
−n: correction clock generation circuit, 100: reference clock generation circuit, 110: detection circuit, 120: delay circuit, 130
... Clock supply circuit, 140 ... I / O circuit, V _CC ... Power supply voltage, GND ... Ground potential.

Claims (12)

[Claims] 1. A rising / lowering signal is propagated through a signal line.
A clock generation circuit that generates a corrected clock signal that corrects the deterioration for a clock signal whose fall characteristic has deteriorated, wherein at least one reference signal generation circuit generates a reference signal according to the deterioration of the characteristic. A clock generation circuit, comprising: a comparison circuit for comparing a level of a clock signal deteriorated due to signal propagation with a level of the reference signal, wherein the correction clock signal is output from the comparison circuit. 2. The reference signal generating circuit is connected in series between a reference voltage source for supplying a reference voltage whose level is set according to the deterioration of the characteristic and a ground potential. 2. The clock generation circuit according to claim 1, comprising at least two resistance elements. 3. The clock generation circuit according to claim 2, wherein said reference signal generation circuit further includes a reference current source for supplying a reference current having a level set according to the deterioration of said characteristic to said resistance element. 4. An amplifier circuit for amplifying an input clock signal and inputting the amplified clock signal to the signal line, wherein the amplifier circuit has a predetermined slew rate.
A clock generation circuit as described. 5. The clock generation circuit according to claim 1, wherein a ground line is provided so as to cover the signal line for transmitting the clock signal. 6. The clock generation circuit according to claim 1, wherein a power supply line is provided so as to cover the signal line for transmitting the clock signal. 7. Propagation of a signal by propagation through a signal line
A clock generation circuit that generates a corrected clock signal in which the deterioration is corrected for a clock signal whose fall characteristic has deteriorated, wherein at least one reference signal generation circuit generates a reference signal according to a control signal; A comparison circuit that compares the level of the clock signal with the deterioration with the reference signal; a reference clock generation circuit that generates a reference clock signal having a predetermined phase; and an output signal of the comparison circuit and the reference clock signal. And outputs the control signal so that the phase error between the output signal of the comparison circuit and the reference clock signal becomes a predetermined value, and outputs the reference signal output from the reference signal generation circuit. And a control circuit for controlling the control circuit, wherein the correction circuit outputs the correction clock signal from the comparison circuit. 8. The reference signal generation circuit is connected in series between a reference voltage source for supplying a reference voltage whose level is set according to the deterioration of the characteristic and the reference voltage source and a ground potential. The clock generation circuit according to claim 7, comprising at least two resistance elements. 9. The clock generation circuit according to claim 8, wherein said reference signal generation circuit further includes a reference current source for supplying a reference current whose level is set according to the deterioration of said characteristic to said resistance element. 10. An amplifier circuit for amplifying an input clock signal and inputting the amplified clock signal to the signal line, wherein the amplifier circuit has a predetermined slew rate.
A clock generation circuit as described. 11. A clock generation circuit according to claim 7, wherein a ground line is provided so as to cover said signal line for transmitting said clock signal. 12. The clock generation circuit according to claim 7, wherein a power supply line is provided so as to cover said signal line for transmitting said clock signal.