CN113986799A - Digital pin dynamic multiplexing method and device based on FPGA - Google Patents
Digital pin dynamic multiplexing method and device based on FPGA Download PDFInfo
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Abstract
The application relates to a dynamic multiplexing method and a device of digital pins based on FPGA, wherein a chip needing dynamic multiplexing of the digital pins sends dynamic mapping information of an input/output port to a dynamic multiplexing controller through a configuration port, and then the dynamic multiplexing controller stores the dynamic mapping information to a lookup table circuit, wherein the dynamic mapping information comprises mapping information of S input/output pins; and then, the dynamic multiplexing controller controls the mapping relation between the M input ports and the N output ports of the switch network to be sequentially matched with the mapping information of the S input/output pins, so that the complete dynamic multiplexing of the input/output pins interconnected by a plurality of chips is realized, the cost is low, and the automation degree is high.
Description
Technical Field
The application relates to the technical field of computers, in particular to a digital pin dynamic multiplexing method and device based on an FPGA.
Background
With the continuous expansion of the application range of the microcontroller chip, the number of external circuit modules connected with the microcontroller chip is increased, and the number of the input/output ports of the microcontroller chip is often insufficient to connect all the external circuit modules. In addition, external circuit modules such as sensors often need to transmit data to a plurality of microcontroller chips, but one input/output port of one microcontroller chip can only be connected with one input/output port of one external circuit, i.e. one-to-one mutual transmission, and many-to-many mutual transmission cannot be supported.
For the pin multiplexing technology, for example, the invention patent with application number CN201310562546.1 discloses a method for multiplexing I/O pins in a sequential FPGA based on D latches. The method is characterized in that an output port of the FPGA is simultaneously connected with an input interface of a first external circuit and an input interface of a D latch, and an output port of the D latch is connected with an input interface of a second external circuit. When the FPGA needs to communicate with a first external circuit, the FPGA controls the D latch to be in a latch state, and the D latch keeps output data of the FPGA and does not receive subsequent output data of the FPGA; when the FPGA needs to communicate with the second external circuit, the FPGA controls the D latch to be in a through state, and output data of the FPGA passes through the D latch and is sent to the second external circuit. The method can multiplex chip output pins and realize the expansion of the bit width of the FPGA output data. The typical application is to expand the width of an address line when the FPGA is connected with an external SRAM chip.
However, in the method of the invention, when the D latch is in the pass-through state and outputs data to the second external circuit, the first external circuit can still receive the output data of the FPGA, which is likely to cause leakage of transmission data and cause misoperation of the external circuit.
Also for example, chinese patent application No. CN201910916629.3 discloses a digital pin conversion device and method based on FPGA. The method can realize the correct butt joint of the chip pins and the peripheral circuit pins after replacing another peripheral circuit with different pin definitions by the FPGA through the configurable one-to-one corresponding connection of the chip pins and the peripheral circuit pins without redesigning and manufacturing a hardware circuit board. However, this method requires the chip pins and the peripheral circuit pins to be in one-to-one correspondence, and cannot multiplex the limited chip pins and the plurality of peripheral circuit pins for data exchange during the chip operation.
Obviously, the existing chip pin multiplexing and converting method has the problem that the dynamic multiplexing of the input and output pins of the chip cannot be completely realized.
Disclosure of Invention
Therefore, in order to solve the above technical problems, it is necessary to provide a method and an apparatus for dynamically multiplexing digital pins based on FPGA, which can implement complete dynamic multiplexing of input/output pins interconnected by multiple chips.
The technical scheme of the invention is as follows:
a digital pin dynamic multiplexing device based on FPGA comprises:
the dynamic multiplexing controller is provided with a configuration port, the configuration port is used for being connected with a chip needing digital pin dynamic multiplexing, and the chip needing digital pin dynamic multiplexing sends dynamic mapping information of an input/output port to the dynamic multiplexing controller through the configuration port;
the lookup table circuit is connected with the dynamic multiplexing controller, and the dynamic multiplexing controller is used for writing the dynamic mapping information of the input/output port acquired from the chip requiring digital pin dynamic multiplexing into the lookup table circuit;
the switch network is connected with the dynamic multiplexing controller, the switch network is provided with M input ports and N output ports, and the M input ports are connected with the N output ports;
one end of the input circuit is connected with the M input ports of the switch network, the other end of the input circuit is used for being connected with an output digital pin of a chip needing digital pin dynamic multiplexing,
and one end of the output circuit is connected with the N output ports of the switch network, and the other end of the output circuit is used for being connected with input digital pins of a chip which needs digital pin dynamic multiplexing.
Specifically, the lookup table circuit includes S lookup tables, each of the S lookup tables is connected to the dynamic multiplexing controller, and each lookup table stores a mapping relationship between an input pin and an output pin of a chip requiring dynamic multiplexing of digital pins, a retention time T of the mapping relationship, and a next lookup table number to be switched.
Specifically, the mapping relationship between the input pins and the output pins of the S chips requiring dynamic multiplexing of the digital pins is stored in the S lookup tables.
Specifically, the input circuit comprises M input pins, inputs of the M input pins are used for connecting output digital pins of a chip requiring digital pin dynamic multiplexing, and outputs of the M input pins are connected with M input ports of the switch network.
Specifically, the output circuit comprises N output pins, the input ends of the N output pins are connected to N output ports of the switch network, and the output ends of the N output pins are used for connecting input digital pins of a chip requiring digital pin dynamic multiplexing.
Specifically, a digital pin dynamic multiplexing method based on an FPGA is based on the digital pin dynamic multiplexing device based on the FPGA, and the method includes the following steps:
the method comprises the following steps: the chip which needs digital pin dynamic multiplexing sends the dynamic mapping information of the input and output ports to the dynamic multiplexing controller through the configuration port;
step two: the dynamic multiplexing controller stores the dynamic mapping information to the lookup table circuit, wherein the dynamic mapping information comprises mapping information of S input/output pins;
step three: and the dynamic multiplexing controller controls the mapping relation between the M input ports and the N output ports of the switch network to sequentially match the mapping information of the S input/output pins.
Specifically, one of the input/output pin mapping information includes a mapping relationship between an input pin and an output pin of a chip requiring dynamic multiplexing of digital pins, a retention time T of the mapping relationship, and a next switching lookup table number;
step two: the dynamic multiplexing controller stores the dynamic mapping information to the lookup table circuit, where the dynamic mapping information includes mapping information of S input/output pins, and specifically includes:
and the dynamic multiplexing controller stores the dynamic mapping information into S lookup table circuits in the lookup table circuits, wherein one lookup table stores the mapping relation between the input pin and the output pin of a chip requiring digital pin dynamic multiplexing, the maintenance time T of the mapping relation and the number of the next switched lookup table.
Specifically, mapping information of S input/output pins in the dynamic mapping information is arranged according to a specific sequence;
step three: the dynamic multiplexing controller controls mapping relationships between the M input ports and the N output ports of the switch network to sequentially match mapping information of the S input/output pins, and specifically includes:
and the dynamic multiplexing controller controls the mapping relation between the M input ports and the N output ports of the switch network to sequentially match the mapping information of the S input/output pins according to the specific sequence.
The invention has the following technical effects:
according to the FPGA-based digital pin dynamic multiplexing method and device, firstly, a chip needing digital pin dynamic multiplexing sends dynamic mapping information of an input/output port to the dynamic multiplexing controller through the configuration port, and then the dynamic multiplexing controller stores the dynamic mapping information to the lookup table circuit, wherein the dynamic mapping information comprises mapping information of S input/output pins; and then, the dynamic multiplexing controller controls the mapping relation between the M input ports and the N output ports of the switch network to be sequentially matched with the mapping information of the S input/output pins, so that the complete dynamic multiplexing of the input/output pins interconnected by a plurality of chips is realized, the cost is low, and the automation degree is high.
Drawings
Fig. 1 is a block diagram of an embodiment of an FPGA-based digital pin dynamic multiplexing apparatus.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In one embodiment, as shown in fig. 1, there is provided an FPGA-based digital pin dynamic multiplexing apparatus, including a dynamic multiplexing controller, a lookup table circuit, a switch network, an input circuit, and an output circuit.
Further, the dynamic multiplexing controller has a configuration port, the configuration port is used for connecting with a chip requiring digital pin dynamic multiplexing, and the chip requiring digital pin dynamic multiplexing sends dynamic mapping information of the input/output port to the dynamic multiplexing controller through the configuration port. Specifically, the number of chips requiring dynamic multiplexing of digital pins is one or more.
The lookup table circuit is connected with the dynamic multiplexing controller, and the dynamic multiplexing controller is used for writing dynamic mapping information of the input/output port acquired from a chip requiring digital pin dynamic multiplexing into the lookup table circuit; the switch network is connected with the dynamic multiplexing controller, the switch network is provided with M input ports and N output ports, and the M input ports are connected with the N output ports; one end of the input circuit is connected with M input ports of the switch network, the other end of the input circuit is used for being connected with output digital pins of a chip needing digital pin dynamic multiplexing, one end of the output circuit is connected with N output ports of the switch network, and the other end of the output circuit is used for being connected with input digital pins of the chip needing digital pin dynamic multiplexing.
The invention relates to a digital pin dynamic multiplexing method and a device based on FPGA, firstly, a chip needing digital pin dynamic multiplexing sends dynamic mapping information of an input/output port to a dynamic multiplexing controller through a configuration port, and then the dynamic multiplexing controller stores the dynamic mapping information to a lookup table circuit, wherein the dynamic mapping information comprises mapping information of S input/output pins; and then, the dynamic multiplexing controller controls the mapping relation between the M input ports and the N output ports of the switch network to be sequentially matched with the mapping information of the S input/output pins, so that the complete dynamic multiplexing of the input/output pins interconnected by a plurality of chips is realized, the cost is low, and the automation degree is high.
In one embodiment, the lookup table circuit includes S lookup tables, each of the S lookup tables is connected to the dynamic multiplexing controller, and each of the lookup tables stores a mapping relationship between an input pin and an output pin of a chip requiring dynamic multiplexing of digital pins, a maintaining time T of the mapping relationship, and a next lookup table number for switching, and the mapping relationship between the input pin and the output pin of the chip requiring dynamic multiplexing of digital pins, the maintaining time T of the mapping relationship, and the next lookup table number for switching are in one-to-one correspondence.
In one embodiment, the S lookup tables store mapping relationships between input pins and output pins of S chips requiring dynamic multiplexing of digital pins, and similarly, the S lookup tables also store the holding time T of the S mapping relationships and the number of the next lookup table to be switched.
In one embodiment, the input circuit includes M input pins, inputs of the M input pins are used for connecting output digital pins of a chip requiring digital pin dynamic multiplexing, and outputs of the M input pins are connected with M input ports of the switch network.
In one embodiment, the output circuit includes N output pins, inputs of the N output pins are connected to N output ports of the switch network, and outputs of the N output pins are used for connecting input digital pins of a chip requiring dynamic multiplexing of digital pins.
Furthermore, the dynamic multiplexing controller is connected to the S lookup tables and the switch network, and can read the mapping relationship between the M input pins and the N output pins stored in any one lookup table k, and control the switch network to change the configuration in real time, so that the M input pins are connected to the N output pins through the switch network, and the mapping relationship between the M input pins and the N output pins stored in the lookup tables k is satisfied, and dynamic real-time switching of the S mapping relationships can be realized, thereby realizing dynamic multiplexing of all digital pins of all chips requiring dynamic multiplexing of the digital pins, wherein k is an integer between 1 and S.
The connection relation between M input ports and N output ports of the switch network enables any input port h to be connected with any output port j. h is an integer from 1 to M, and j is an integer from 1 to N.
In one embodiment, a method for dynamically multiplexing digital pins based on an FPGA is based on the apparatus for dynamically multiplexing digital pins based on the FPGA, and the method includes the following steps:
the method comprises the following steps: the chip which needs digital pin dynamic multiplexing sends the dynamic mapping information of the input and output ports to the dynamic multiplexing controller through the configuration port;
step two: the dynamic multiplexing controller stores the dynamic mapping information to the lookup table circuit, wherein the dynamic mapping information comprises mapping information of S input/output pins;
step three: and the dynamic multiplexing controller controls the mapping relation between the M input ports and the N output ports of the switch network to sequentially match the mapping information of the S input/output pins.
Further, the chip requiring digital pin dynamic multiplexing sends the dynamic mapping information of the input/output port to the dynamic multiplexing controller through the configuration port, and then the dynamic multiplexing controller stores the dynamic mapping information to the lookup table circuit, wherein the dynamic mapping information comprises mapping information of S input/output pins; and then, the dynamic multiplexing controller controls the mapping relation between the M input ports and the N output ports of the switch network to be sequentially matched with the mapping information of the S input/output pins, so that the complete dynamic multiplexing of the input/output pins interconnected by a plurality of chips is realized, the cost is low, and the automation degree is high.
In one embodiment, one of the input/output pin mapping information includes a mapping relationship between an input pin and an output pin of a chip requiring dynamic multiplexing of digital pins, a maintaining time T of the mapping relationship, and a next switching look-up table number;
step two: the dynamic multiplexing controller stores the dynamic mapping information to the lookup table circuit, where the dynamic mapping information includes mapping information of S input/output pins, and specifically includes:
and the dynamic multiplexing controller stores the dynamic mapping information into S lookup table circuits in the lookup table circuits, wherein one lookup table stores the mapping relation between the input pin and the output pin of a chip requiring digital pin dynamic multiplexing, the maintenance time T of the mapping relation and the number of the next switched lookup table.
In one embodiment, the mapping information of the S input/output pins in the dynamic mapping information is arranged according to a specific sequence;
step three: the dynamic multiplexing controller controls mapping relationships between the M input ports and the N output ports of the switch network to sequentially match mapping information of the S input/output pins, and specifically includes:
and the dynamic multiplexing controller controls the mapping relation between the M input ports and the N output ports of the switch network to sequentially match the mapping information of the S input/output pins according to the specific sequence. In particular, the specific sequential arrangement is set by the person skilled in the art as desired.
Further, let the first lookup table number be a. Then, 1. ltoreq. a. ltoreq.S.
Next, b = a is initialized, where b represents the number of the current look-up table.
Furthermore, the dynamic multiplexing controller fetches the mapping information of the input/output pins stored in the lookup table b, then controls the switch network to configure the mapping relationship between the M input pins and the N output pins to conform to the mapping information of the input/output pins, and then waits for a time T, where T is a maintaining time T of the mapping relationship of the lookup table b. Then, the dynamic multiplexing controller searches for the next lookup table according to the specific sequence, takes out the mapping information of the input and output pins of the next lookup table, and then circulates the steps until all the matching is completed in sequence according to the specific sequence.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (8)
1. The utility model provides a digit pin developments multiplexing device based on FPGA which characterized in that includes:
the dynamic multiplexing controller is provided with a configuration port, the configuration port is used for being connected with a chip needing digital pin dynamic multiplexing, and the chip needing digital pin dynamic multiplexing sends dynamic mapping information of an input/output port to the dynamic multiplexing controller through the configuration port;
the lookup table circuit is connected with the dynamic multiplexing controller, and the dynamic multiplexing controller is used for writing the dynamic mapping information of the input/output port acquired from the chip requiring digital pin dynamic multiplexing into the lookup table circuit;
the switch network is connected with the dynamic multiplexing controller, the switch network is provided with M input ports and N output ports, and the M input ports are connected with the N output ports;
one end of the input circuit is connected with the M input ports of the switch network, the other end of the input circuit is used for being connected with an output digital pin of a chip needing digital pin dynamic multiplexing,
and one end of the output circuit is connected with the N output ports of the switch network, and the other end of the output circuit is used for being connected with input digital pins of a chip which needs digital pin dynamic multiplexing.
2. The dynamic multiplexing device for digital pins based on FPGA of claim 1, wherein said lookup table circuit comprises S lookup tables, each of which is connected to said dynamic multiplexing controller, and each of said lookup tables stores a mapping relationship between an input pin and an output pin of a chip requiring dynamic multiplexing of digital pins, a retention time T of the mapping relationship, and a next lookup table number for switching.
3. The FPGA-based dynamic digital pin multiplexing device of claim 2, wherein the S look-up tables store mapping relationships between input pins and output pins of S chips requiring dynamic digital pin multiplexing.
4. The FPGA-based digital pin dynamic multiplexing device of any one of claims 1 to 3, wherein the input circuit comprises M input pins, inputs of the M input pins are used for connecting output digital pins of a chip requiring digital pin dynamic multiplexing, and outputs of the M input pins are connected with M input ports of the switch network.
5. The dynamic multiplexing device for digital pins based on FPGA of any one of claims 1-3, wherein the output circuit comprises N output pins, the inputs of the N output pins are connected to N output ports of the switch network, and the outputs of the N output pins are used for connecting the input digital pins of the chip requiring dynamic multiplexing of digital pins.
6. An FPGA-based digital pin dynamic multiplexing method, which is based on the FPGA-based digital pin dynamic multiplexing device of any one of claims 1 to 5, and comprises the following steps:
the method comprises the following steps: the chip which needs digital pin dynamic multiplexing sends the dynamic mapping information of the input and output ports to the dynamic multiplexing controller through the configuration port;
step two: the dynamic multiplexing controller stores the dynamic mapping information to the lookup table circuit, wherein the dynamic mapping information comprises mapping information of S input/output pins;
step three: and the dynamic multiplexing controller controls the mapping relation between the M input ports and the N output ports of the switch network to sequentially match the mapping information of the S input/output pins.
7. The FPGA-based dynamic digital pin multiplexing method of claim 6, wherein one of the I/O pin mapping information comprises a mapping relationship between an I/O pin of a chip requiring dynamic digital pin multiplexing, a retention time T of the mapping relationship, and a next switching lookup table number;
step two: the dynamic multiplexing controller stores the dynamic mapping information to the lookup table circuit, where the dynamic mapping information includes mapping information of S input/output pins, and specifically includes:
and the dynamic multiplexing controller stores the dynamic mapping information into S lookup table circuits in the lookup table circuits, wherein one lookup table stores the mapping relation between the input pin and the output pin of a chip requiring digital pin dynamic multiplexing, the maintenance time T of the mapping relation and the number of the next switched lookup table.
8. The FPGA-based digital pin dynamic multiplexing device of claim 6 or 7, wherein the mapping information of S input/output pins in the dynamic mapping information is arranged according to a specific sequence;
step three: the dynamic multiplexing controller controls mapping relationships between the M input ports and the N output ports of the switch network to sequentially match mapping information of the S input/output pins, and specifically includes:
and the dynamic multiplexing controller controls the mapping relation between the M input ports and the N output ports of the switch network to sequentially match the mapping information of the S input/output pins according to the specific sequence.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116126366A (en) * | 2023-04-19 | 2023-05-16 | 深圳市锐深科技有限公司 | Chip input/output interface configuration method, device, medium and electronic equipment |
| CN116795755A (en) * | 2023-08-28 | 2023-09-22 | 上海移芯通信科技股份有限公司 | Equipment management method and device based on Internet of things chip |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200415501A (en) * | 2004-01-02 | 2004-08-16 | Via Tech Inc | Multi-functional I/O system |
| US20110260752A1 (en) * | 2010-04-27 | 2011-10-27 | Sebastien Jouin | General purpose input/output pin mapping |
| CN107329417A (en) * | 2016-04-28 | 2017-11-07 | 深圳市博巨兴实业发展有限公司 | A kind of microcontroller and its input and output pin mapping circuit |
| CN110674077A (en) * | 2019-09-26 | 2020-01-10 | 北京智芯微电子科技有限公司 | FPGA-based digital pin conversion device and method |
| CN110674069A (en) * | 2019-09-26 | 2020-01-10 | 北京智芯微电子科技有限公司 | Digital pin conversion circuit and method of chip and chip |
| CN111797583A (en) * | 2019-03-20 | 2020-10-20 | 瑞昱半导体股份有限公司 | Pin multiplexing device and method for controlling pin multiplexing device |
| CN113114220A (en) * | 2021-06-16 | 2021-07-13 | 杭州万高科技股份有限公司 | Chip system with remapping function and chip remapping configuration system |
| CN113272906A (en) * | 2021-03-30 | 2021-08-17 | 长江存储科技有限责任公司 | Pattern generation system with pin function mapping |
-
2021
- 2021-11-12 CN CN202111341816.7A patent/CN113986799B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200415501A (en) * | 2004-01-02 | 2004-08-16 | Via Tech Inc | Multi-functional I/O system |
| US20110260752A1 (en) * | 2010-04-27 | 2011-10-27 | Sebastien Jouin | General purpose input/output pin mapping |
| CN107329417A (en) * | 2016-04-28 | 2017-11-07 | 深圳市博巨兴实业发展有限公司 | A kind of microcontroller and its input and output pin mapping circuit |
| CN111797583A (en) * | 2019-03-20 | 2020-10-20 | 瑞昱半导体股份有限公司 | Pin multiplexing device and method for controlling pin multiplexing device |
| CN110674077A (en) * | 2019-09-26 | 2020-01-10 | 北京智芯微电子科技有限公司 | FPGA-based digital pin conversion device and method |
| CN110674069A (en) * | 2019-09-26 | 2020-01-10 | 北京智芯微电子科技有限公司 | Digital pin conversion circuit and method of chip and chip |
| CN113272906A (en) * | 2021-03-30 | 2021-08-17 | 长江存储科技有限责任公司 | Pattern generation system with pin function mapping |
| CN113114220A (en) * | 2021-06-16 | 2021-07-13 | 杭州万高科技股份有限公司 | Chip system with remapping function and chip remapping configuration system |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116126366A (en) * | 2023-04-19 | 2023-05-16 | 深圳市锐深科技有限公司 | Chip input/output interface configuration method, device, medium and electronic equipment |
| CN116126366B (en) * | 2023-04-19 | 2023-06-30 | 深圳市锐深科技有限公司 | Chip input/output interface configuration method, device, medium and electronic equipment |
| CN116795755A (en) * | 2023-08-28 | 2023-09-22 | 上海移芯通信科技股份有限公司 | Equipment management method and device based on Internet of things chip |
| CN116795755B (en) * | 2023-08-28 | 2023-12-08 | 上海移芯通信科技股份有限公司 | Equipment management method and device based on Internet of things chip |
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