CN1529458B - High-capacity hinder-free switching method in programme controlled switching network - Google Patents
High-capacity hinder-free switching method in programme controlled switching network Download PDFInfo
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- CN1529458B CN1529458B CN 03146947 CN03146947A CN1529458B CN 1529458 B CN1529458 B CN 1529458B CN 03146947 CN03146947 CN 03146947 CN 03146947 A CN03146947 A CN 03146947A CN 1529458 B CN1529458 B CN 1529458B
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Abstract
Three stage of switching network including three stage of chip set: input stage, intermediate stage and output stage is adopted in the invented method. An intermediate stage resources used table is setup in the intermediate stage. The table stores service condition of time slot resources in the intermediate stage. The method includes following steps: maintenance is carried out for the said table in switching in procedure and switching off procedure of program controlled exchange procedure. Before switching in, looking up the resources used table is carried out in advance. In switching in procedure, how to use switching in resources is determined based on the intermediate stage resources used table; in switching off procedure, corresponding id to time slot in the resources used table is released. The program controlled digital exchange network using the invented method is capable of carrying expedite exchange in large capacity with high exchanging efficiency and small delay.
Description
Technical field
The present invention relates to the Program Controling of Digital Exchange technology, specifically, relate to a kind of method that how to make digital time division switching network realize the clog-free exchange of big capacity, the inventive method will be widely used in the field of stored-program control exchange.
Background technology
The switching network that uses in the large capacity digital stored-program control exchange at present mainly adopts two kinds of methods, and a kind of is to adopt hardware component to carry out logic control to build circuit, satisfies the requirement of time gas exchange; Under the lower situation of the Capacity Ratio of former exchange chip, be all to be to adopt this method substantially, but the shortcoming of this method is, the hardware circuit complexity, poor reliability, and workload is bigger.In Chinese patent literature 95107865.8, just adopted string and conversion, dual port RAM, and the circuit of string conversion builds, but circuit is very complicated.Another kind of is exactly the switching network that the direct integrated chip that adopts chip manufacturer to provide constitutes.Just in time can remedy the shortcoming of first method for the advantage of second method, two kinds of methods of the same employing of hardware configuration in the second approach: a kind of is the matrix structure that adopts N * N, the advantage of this method is the problem that does not have obstruction basically, but to be it employed that chip-count increases and square being directly proportional of its exchange capacity growth and N for its shortcoming, needed exchange chip is many especially when exchange capacity is bigger, therefore product cost will be very high, produce, designs all very complicated.Another kind method is to adopt the method for three grades of switching networks, and the advantage of this method is the linear growth of the number and the exchange capacity of required chip, but its shortcoming is easy obstruction, and time delay is big.
Therefore, obviously there is defective in prior art, and awaits improving.
Summary of the invention
The objective of the invention is to defective, the method for the big without hindrance exchange of capacity in a kind of program-controlled switching network is provided at the method for three grades of switching networks of above-mentioned prior art.
Technical scheme of the present invention is as follows:
The method of the big without hindrance exchange of capacity in a kind of program-controlled switching network, it adopts three grades of switching networks, described three grades of switching networks comprise input stage, intergrade and three grades of chipsets of output stage, described intergrade is provided with intergrade resource use table, this intergrade resource is used to deposit the operating position of the time interval resource of described intergrade, the parameter that described time interval resource has comprises the input and output parameter of input stage, the input and output parameter of intergrade, the input and output parameter of output stage, said method comprising the steps of:
In the programme-controlled exchange process, continuing respectively and intermittent process in described intergrade resource use table is safeguarded, that is:
Before continuing, table look-up at first in advance, when continuing, judge the use continue resource according to this intergrade resource use table;
In interrupted, the time slot corresponding identification in this intergrade resource use table is discharged.
Described method, wherein, the step of tabling look-up in advance of being carried out before the described handshaking procedure is as follows:
A0) successively the element value of each group of described intergrade chip is searched,, determined that this yuan have available resources and be about to this inquiry pointer and move on to this element from the original position of inquiry pointer, and the initial position of the pointer next time searched of conduct.
Described method, wherein, described handshaking procedure has adopted following steps:
A1) determine the chip number of described input stage and the input combination of described intergrade respectively according to input parameter, and the output group number of the chip of described output stage number and described intergrade;
A2) chip of a selected at random described intergrade, according to pre-checking result by described intergrade resource use table is searched, obtain to continue can be successful judgment condition and this chip in input group and output group whether all have resource to use;
A3) as finding the intergrade chip that satisfies resources supplIes, described program controlled system is carried out the physics operation that continues to described input stage, intergrade and output stage; If whole network has not all had resource, return accordingly result and end;
A4) finish current continuing after, carry out described pre-table lookup operation intergrade resource use table handled the resource that next time continues to obtain, and preserve current inquiry pointer.
Described method, wherein, described intermittent process has adopted following steps:
The parameter of its time slot of output that continues that b1) basis has been set up;
B2) according to the parameter of the time slot of this output, the physics that reads output stage, intergrade and the input stage successively configuration that continues obtains the exchange configuration of intergrade and input stage;
B3) described program controlled system is carried out the physics intermittent operation;
B4) described intergrade resource use table is handled, discharged the sign of corresponding time interval resource in this intergrade resource use table.
Described method, wherein, described intergrade resource use table is subdivided into sublist again according to crosspoint physical connection situation, and the size of each sublist is the corresponding timeslot number that a physics continues.
The method of the big without hindrance exchange of capacity in a kind of program-controlled switching network provided by the invention, because it has adopted having adopted the use of intergrade resource to show to write down the time interval resource situation in existing three grades of switching networks, and before continuing, table look-up in advance and determine the time interval resource situation, and do not influence operating time of handshaking procedure, thereby can carry out the without hindrance exchange of big capacity in the Program Controling of Digital Exchange net of the inventive method, the exchange efficiency height is delayed little.
Description of drawings
Fig. 1 is the physical connection schematic diagram of three grades of switching networks in the method for the big without hindrance exchange of capacity in a kind of program-controlled switching network of the present invention;
Fig. 2 is the schematic flow sheet of the handshaking procedure in the inventive method;
Fig. 3 is the schematic flow sheet of the intermittent process in the inventive method;
Fig. 4 is the file layout schematic diagram that the intergrade resource in the inventive method is used table.
Embodiment
Below with reference to accompanying drawing,, make technical scheme of the present invention and beneficial effect thereof apparent by detailed description to preferred embodiment of the present invention.
Because the information that the inventive method has been managed each unit in the switching matrix ground (each exchange chip) perfectly, make that the relations that continue at different levels all are reliable, need only the spendable resources that have at different levels, just can guarantee to set up a path to final stage, and can not influence the relation of continuing that other paths have been set up from elementary.The inventive method has realized a kind of switching method of three grades of switching networks, the hardware schematic diagram of described three grades of switching networks as shown in Figure 1, connection by three grades of switching networks illustrates as can be seen, determine the annexation of entire switching network, need know the minislot parameter relation of six aspects: the input parameter of input stage, the output parameter of input stage, the input parameter of intergrade, the output parameter of intergrade, the input parameter of output stage, the output parameter of output stage.
But can know from the annexation of physics shown in Figure 1: the output parameter of described input stage is the same with the input parameter of described intergrade, and the output parameter of described intergrade and the input parameter of described output stage are one to one.Therefore the parameter that needs just is kept to 4: the input parameter of described input stage, the input parameter of described intergrade, the output parameter of described intergrade, the output parameter of described output stage.Because the input parameter of described input stage and the output parameter of described output stage just can be determined by the parameter that continues, so the inventive method uses table and intergrade output resource to use table as long as safeguard the input resource of described intergrade, promptly the intergrade resource uses table to get final product.
For the reliability that guarantees to continue, must safeguard the operating position of described intergrade, can not take without authorization before release for already used resource, to prevent to destroy other the relation of continuing.Described intergrade resource use table is mainly used to deposit the operating position of the time interval resource of described intergrade, to continue can be successful judgment condition mainly obtain by this table is inquired about.When continuing, need search this table; In interrupted, need the time slot corresponding identification in this table be discharged.Described intermediary resources use table is subdivided into sublist again according to crosspoint physical connection situation, and the size of each sublist is the corresponding timeslot number of a physical connection.
The inventive method provides a kind of switching network of single-plate grade high-capacity, can finish the big capacity exchange of 64K * 64K on a common veneer; And by expanding the exchange that the inventive method can realize 256Kx256K.
For 64K * 64K capacity, the monolithic exchange capacity be 16K * 16K chip.The hardware elementary diagram of the inventive method as shown in Figure 1.Adopt the exchange chip of 12 monolithics altogether, be divided into three grades: input stage switching stage, intergrade switching stage, output stage switching stage; Every grade has four row, and the capacity of entire switching network is equivalent to 4 times of single exchange chip.This monolithic chip can realize the clog-free circuit switching of 16K, and data channel interface is 32MHW (High Way, a kind of high-speed serial data line that carries data), and totally 32 to (input and output), and each 32MHW has 512Ts (Time Slot, time slot).Easy to operate for the inventive method, 32 HW that are defined in each chip are divided into one group that four group (Group): 0～7HW are, 8～15Hw is second group, and 16～23Hw is the 3rd group, and 24～31HW is the 4th group.
As seen from Figure 1: the HW of 4 row exchange chips is sorted, totally 128 HW.The annexation of the output HW of described input stage and the input HW of described intergrade is: first group of HW physical connection of the output of each chip of described input stage is to the chip of first row of described intergrade, second group of HW physical connection is to the chip of the secondary series of described intergrade, the 3rd group of HW physical connection is to the tertial chip of described intergrade, and the 4th group of HW physical connection is to the chip of the 4th row of described intergrade.It is emphasized that (annexation is linked in sequence in 8 HW of a group (Group)), the physical connection relation object of the output of same described intergrade and the input of described output stage seemingly.
Described intergrade resource is used table:
The exchange capacity of system is 64K among this embodiment of the inventive method, we define the array of a 32bit, each bit safeguards a time slot, each array element can be safeguarded 32 time slots, this intergrade input of safeguarding 64K needs 64 * 1024/32=2048 element, in like manner, the output of intergrade also needs 2048 elements.We are finished by 4 chips for the exchange capacity of 64K, and each chip has 4 groups (8HW) again, and this each group needs the 2048/4/4=128 element.
The file layout of the table of each group as shown in Figure 4, each table safeguards the time interval resource of 4k.The output of described intergrade is in like manner also in this way stored.The resource table of each intergrade input (output) will be safeguarded the initial address of a current pointer of tabling look-up, in the time of initially with the initial position of each table initial address as the pointer of tabling look-up; The initial address that other situations are tabled look-up is the address of the last time tabling look-up and being hit.The sublist of each group in the position of the resource table of whole intergrade is: initial position: ((4 * I)+J) * 128, termination locations ((4 * I)+J) * 128+127, wherein I: the chip of intergrade number, J: the group number of selected chip number.Each of each element in this table is represented the situation that takies of a time slot.If this time slot is occupied, then changes into and be marked as 1; During initialization, this table is initialized to 0.
Table look-up in advance:
The user just should determine present available time interval resource according to the relation of resource in the table before continuing, the algorithm of tabling look-up is: for the resource of each group maintenance, at first from inquiring about the original position of pointer, determine earlier whether certain element (double word) in this table has available resources, be whether this element value is 0xffffffff, if this value is not equal to 0Xffffffff, this yuan have available resources, just in this element, search, do not search in the next element if there are available resources to arrive, the rest may be inferred.All do not have available resources if travel through all 128 all spaces, this group of this chip has not just had available resource.If find available resources, so just should inquire about pointer and move on to this element, as the initial position of the pointer of searching next time.This process of tabling look-up in advance is actual to be the lookup method of a bivariate table, and the worst inquiry times in this group is 128+32=160 number, but this search procedure just finished before continuing, so do not influence the speed that continues.
The operation that continues:
As shown in Figure 2, at first determine the chip number of input stage, the chip of output stage number, and the output group number of the input group number of intergrade and intergrade according to input parameter.4 chips for intergrade all might exchange to the output of input stage in the corresponding input of output stage.So the chip of a selected at random intergrade in the inventive method is searched in selected chip and whether is satisfied corresponding input group and the output group all has resource to use.If do not satisfy just selected next chip of this condition and judge whether do not satisfy this condition, if 4 chips do not satisfy this condition, then these three grades of switching networks have not had continue resource and can use.
If find one the intergrade chip that satisfies resources supplIes is arranged, according to the output resource of present available intergrade, determine the relation of continuing of output stage, determine the relation of continuing of intergrade according to the output of the input of intergrade and intergrade; The relation of continuing of determining input stage according to the input and the customer parameter of intergrade.To input stage, intergrade, output stage are carried out physics and are continued then, and this relation of continuing has just been set up like this.
The bright for instance operating process that continues.The Ts 23 of input HW 4 outputs to the TS 4 of HW 124.The present invention can determine that the exchange chip of input stages be (4/32+1) first from input HW 4, intergrade be input as first group; HW 124 determines that the exchange chip of output stage is (124/32+1) the 4th from output, and intergrade is output as the 4th group.The chip that adds an intergrade of the inventive method picked at random, if selected second, then search first group and the 4th group available resources of output stage of this input stage of second of this intergrade, if available resource is arranged, if the HW30 of output stage, ts1 (note be for this HW number in the chip numbering 0～31), the 4th chip of corresponding output stage be input as 8+ (30-24)=14HW (numbering 0～31 of chip internal), ts1.If intergrade be input as HW 0 (numbering 0～31 of chip internal), TS3.Can determine the relation of continuing of intergrade.Be output as (1*8+0)=HW 8 (numbering 0～31 of chip internal), TS1 according to what the input of intergrade can be determined input stage.The relation of continuing of described like this input stage has also been decided.After finishing current continuing, tabling look-up in advance obtains the time interval resource that next time continues, and preserves current inquiry pointer.
Interrupted operation:
Interrupted operation is fairly simple with respect to handshaking procedure, begins to obtain step by step the information of continuing from output stage, and is interrupted to it then.By the flow chart of Fig. 3, at first determine the output parameter of output stage by interrupted parameter, read the information that continues of time slot then, the information of the input stage that can obtain exporting; Can draw the output parameter of intergrade by the input parameter of output stage, read the input parameter of the information acquisition intergrade that continues of intergrade then; Can obtain the output parameter of input stage by the input parameter of intergrade.Such three grades interrupted relation just can obtain fully, and it is interrupted respectively it to be carried out physics.Discharge the corresponding time interval resource of described intergrade simultaneously, and safeguard this intergrade resource use table.
Illustrate described interrupted process, the link that continues in the interrupted above-mentioned just now example.The input parameter that this is interrupted: output HW 124TS4.Read the 4th the information that continues of input stage, that knows output stage is input as 14HW (numbering 0～31 of chip internal), TS1; The exchange chip output of calculating intergrade is the HW30 of second output stage, ts1 (note this HW number be the numbering 0～31 in the chip); What the information of continuing that reads intergrade can obtain intergrade is input as HW 0 (numbering 0～31 of chip internal), and TS 3; The output that calculates input stage is first 8+0=HW8 (numbering 0～31 of chip internal), TS1.Such three grades interrupted target has all found, and carries out physics successively and intermittently gets final product.
The present invention adopts the method for tabling look-up in advance, do not have the problem of tabling look-up and postponing in the operation of reality, the operating time is that (connecting time is very short, for MOTORALA 8260CPU for 3 connecting time sums, for μ s level), so there is not the problem of delay in the operation of the three grades of nets that continue substantially; Because the resource that the method that the intergrade employing is tabled look-up in advance continues is directly used the last resource of searching, and is a choke free operation at every turn.Described method of tabling look-up in advance is the method that adopts two dimension to table look-up, and the search efficiency height is so whole three grades of net operations are choke free operations; For the exchange chip that uses, the corresponding address independently of the memory space of each time slot, the operation of different time slots is to walk abreast independently fully, so the different time-gap operation is independent of each other.
In sum, the present invention has realized realizing the method for clog-free undelayed exchange in the big capacity switching network that three grades of switching matrixs constitute.Continuing that the inventive method adopted is simple and reliable with interrupted method, only needs S=(C/8) * 2 (S: needed memory space, the exchange capacity of C switching network) for the table memory space; Than higher, the maintenance of his-and-hers watches is also relatively simple to the efficient of tabling look-up.So this invention has good application prospect in the large capacity digital exchange.
Should be pointed out that according to technical scheme of the present invention and design thereof, for those of ordinary skills, can make various possible being equal to and change or replacement, and all these changes or replacement all should belong to the protection range of claims of the present invention.
Claims (5)
1. the method for the big without hindrance exchange of capacity in the program-controlled switching network, it adopts three grades of switching networks, described three grades of switching networks comprise input stage, intergrade and three grades of chipsets of output stage, described intergrade is provided with intergrade resource use table, this intergrade resource use table is used to deposit the operating position of the time interval resource of described intergrade, the parameter that described time interval resource has comprises the input and output parameter of input stage, the input and output parameter of intergrade, the input and output parameter of output stage, said method comprising the steps of:
In the programme-controlled exchange process, continuing respectively and intermittent process in described intergrade resource use table is safeguarded, that is:
Before continuing, look into intergrade resource use table at first in advance, when having available time interval resource, finish input stage, intergrade and output stage according to available time interval resource and continue;
In interrupted, begin to obtain step by step the information of continuing from output stage, according to the information of continuing output stage, intergrade and input stage are carried out intermittently, and the time slot corresponding identification in this intergrade resource use table is discharged.
2. method according to claim 1 is characterized in that, the step of tabling look-up in advance of being carried out before the described handshaking procedure is as follows:
A0) successively the element value of each group of described intergrade chip is searched,, determined that this yuan have available resources and be about to this inquiry pointer and move on to this element from the original position of inquiry pointer, and the initial position of the pointer next time searched of conduct.
3. method according to claim 2 is characterized in that, described handshaking procedure has adopted following steps:
A1) determine the chip number of described input stage and the input combination of described intergrade respectively according to input parameter, and the output group number of the chip of described output stage number and described intergrade;
A2) chip of a selected at random described intergrade, according to pre-checking result by described intergrade resource use table is searched, obtain to continue can be successful judgment condition and this chip in input group and output group whether all have resource to use;
A3) as finding the intergrade chip that satisfies resources supplIes, described program controlled system is carried out the physics operation that continues to described input stage, intergrade and output stage; If whole network has not all had resource, return accordingly result and end;
A4) finish current continuing after, carry out described pre-table lookup operation intergrade resource use table handled the resource that next time continues to obtain, and preserve current inquiry pointer.
4. according to claim 2 or 3 described methods, it is characterized in that described intermittent process has adopted following steps:
The parameter of its time slot of output that continues that b1) basis has been set up;
B2) according to the parameter of the time slot of this output, the physics that reads output stage, intergrade and the input stage successively configuration that continues obtains the exchange configuration of intergrade and input stage;
B3) described program controlled system is carried out the physics intermittent operation;
B4) described intergrade resource use table is handled, discharged the sign of corresponding time interval resource in this intergrade resource use table.
5. method according to claim 4 is characterized in that, described intergrade resource use table is subdivided into sublist again according to crosspoint physical connection situation, and the size of each sublist is the corresponding timeslot number that a physics continues.
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| CN 03146947 CN1529458B (en) | 2003-09-26 | 2003-09-26 | High-capacity hinder-free switching method in programme controlled switching network |
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| CN 03146947 CN1529458B (en) | 2003-09-26 | 2003-09-26 | High-capacity hinder-free switching method in programme controlled switching network |
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| CN1529458B true CN1529458B (en) | 2010-04-14 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1870833B (en) * | 2005-05-26 | 2010-12-08 | 中兴通讯股份有限公司 | Method of implement large capacity unblock time-division exchange network and its single-board device |
| CN100417136C (en) * | 2005-07-27 | 2008-09-03 | 华为技术有限公司 | Down queue fast back pressure transmitting based on three-stage exchange network |
| CN1937784B (en) * | 2006-09-26 | 2010-05-12 | 华为技术有限公司 | Programme-coutrolled digital exchange method and exchange device for realizing data exchange |
| CN105262658A (en) * | 2015-10-30 | 2016-01-20 | 北京交控科技有限公司 | Switching device, field-bus topological structure, and data transmission method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1150515A (en) * | 1994-06-10 | 1997-05-21 | 艾利森电话股份有限公司 | Three stage switching unit |
| WO2003032554A2 (en) * | 2001-10-05 | 2003-04-17 | Bbnt Solutions Llc | Near-non-blocking switch scheduler for three-stage banyan switches |
| CN1431832A (en) * | 2003-01-16 | 2003-07-23 | 上海交通大学 | Three levels exchange structure with characters of high and low dual speeds, strict ranking and without blocking expansion |
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2003
- 2003-09-26 CN CN 03146947 patent/CN1529458B/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1150515A (en) * | 1994-06-10 | 1997-05-21 | 艾利森电话股份有限公司 | Three stage switching unit |
| WO2003032554A2 (en) * | 2001-10-05 | 2003-04-17 | Bbnt Solutions Llc | Near-non-blocking switch scheduler for three-stage banyan switches |
| CN1431832A (en) * | 2003-01-16 | 2003-07-23 | 上海交通大学 | Three levels exchange structure with characters of high and low dual speeds, strict ranking and without blocking expansion |
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