CN1870833B - Method of implement large capacity unblock time-division exchange network and its single-board device - Google Patents
Method of implement large capacity unblock time-division exchange network and its single-board device Download PDFInfo
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Abstract
The invention relates a sub-exchange network method and its single plate device when there is a large capacity without any block, in which, the single plate device includes a series & parallel processor for high-speed data input, which can receive high-speed signal with a sub-receiving method, an exchange part of input level of three level network receives high-speed data by a series & parallel input signal processor and chooses the middle level exchange entrance according to continuous request of exchanging, an exchange part of middle level of three level network receives output data of input level of exchanging network and chooses the exchange entrance of output level exchanging network according to continuous request of exchanging, the exchange part of output level of three level network receives output data of exchange parts in the middle level of exchanging network and chooses a link channel to output the high-speed data to series and parallel high-speed processor; high-speed data are output from series & parallel processor then put into series and parallel handling process to complete output data's re-reception and output. The invention realizes a sub-exchange network method on a single plate device when there is a large capacity without any block.
Description
Technical field
The present invention relates to communication field, relate in particular to a kind of method and single-board device thereof of realizing large capacity unblock time-division exchange network in the program controlled switch technology.
Background technology
Along with rolling up of telephone subscriber's quantity and continuing to optimize of telephone network, the user is also more and more higher to the capacity requirement of core switching device.In order to set up big capacity switching network, each communication apparatus manufacturer constitutes by a plurality of small-sized switching networks of stack.Such as finish the 256K exchange by the switching network that uses 32 16K, and for example use the 64K switching network of four big exchange capacities to set up, if constitute full switching network, then need more small-sized switching network, when using more small-sized switching network to set up the 256K exchange, can take a large amount of machine room spaces, the cost of equipment, maintenance difficulties, power consumption and time delay also can increase greatly, reliability also can reduce, if use the method for " copy T " to constitute the full switching network of 256K, the quantity of equipment will rise at double so, so development 256K time division switching network is most important.
Development along with large scale integrated circuit, larger capacity private exchange chip constantly comes out, so the switching network based on the private exchange chip also is on the increase, but the capacity of switching network is big more, the physical circuit that is connected with switching network is just many more so, also become another difficult problem in this area so solve big capacity switch network data physical interface problem, for meeting consumers' demand, this single-board device can realize on capacity that the 256K time division circuit exchanges entirely, and solved the problem of the data physics discrepancy circuit of 256K exchange use on a less veneer, this device also keeps certain advantage at aspects such as reliability and costs in addition.We adopt LVDS (the Low Voltage Differential Signaling) transceiver of National Semiconductor that the exchange physical circuit is carried out n in this single-board device: 1 (n gets the integer value more than or equal to 1) integrated, make the quantity of exchange physical circuit dwindle n doubly, the 16K time-division switching chip that uses the design of American I DT company to produce is simultaneously built the full switching network of 256K, if but use the method for " copying T ", then need 256 16K exchange chips, this can't realize on the less veneer of area, and cost and power consumption can be very high.So at this problem, we according to the characteristic Design of 16K exchange chip three grades of switching technologies, finally use 48 16K exchange chips promptly to finish the switching network design of 256K.Also can be on this basis by reducing the demand that corresponding device realizes that the time division switching network of 128K and the full exchange of 192K reduces the veneer cost and satisfies different occasions.
The CN99109931 Chinese patent has the following disadvantages: one, the present maximum of single-board device according to this patented method design can realize the 64K exchange capacity on PCB (the Printed Circuit Board printed circuit board (PCB)) veneer of same area size; Two, when realizing the 64K exchange, the exchange link of this single-board device of coming in and going out has just reached 256, can't arrange the physical link of 256K exchange capacity; Three, increase the PCB area in this way and design 256K when exchange, can roll up in order to the number of devices that realizes exchange so, reliability reduces, and power consumption also can roll up in addition.
The comparatively relevant method that the big without hindrance exchange of capacity in a kind of program-controlled switching network is provided of CN03146947 Chinese patent with the present invention, it adopts three grades of switching networks to carry out the without hindrance exchange of big capacity, and this method has only proposed can realize the clog-free exchange of big capacity of 64K * 64K on a less PCB veneer equally.And the single-board device that the present invention proposes not only utilizes three grades of switching technologies to realize 256K * 256K exchange, and has proposed to solve the data input and output way to solve the problem of big capacity exchange.
The EP1073309A2 European patent exists not enough, under present development situation, if when using the 16K crosspoint of same capacity to design the 256K switching network in this way, the quantity of exchange chip will reach 256, used 208 than this patent, this is impossible realize on a less PCB more.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of method and single-board device thereof of realizing large capacity unblock time-division exchange network, to realize large capacity unblock time-division exchange network on a less veneer.
To achieve these goals, the invention provides a kind of single-board device of realizing large capacity unblock time-division exchange network, wherein, comprising:
High-speed data input string and processor are used to receive the high speed signal of input, and high speed signal made string and handle, and tap is the input signal of veneer switching network circuit identification;
Three grades of switching network input stage switching parts are used to receive the signal by described high-speed data input string and processor input, and according to the switched connection requirement, select output link to export three grades of switching network intergrade switching parts to;
Three grades of switching network intergrade switching parts are used to receive the dateout of described switching network input stage switching part, and according to the switched connection requirement, select output link to export three grades of switching network output stage switching parts to;
Three grades of switching network output stage switching parts are used to receive the dateout of described switching network intergrade switching part, and according to the switched connection requirement, select output link to export high-speed data output and string manipulation device to;
High-speed data output and string manipulation device are used to receive the dateout of described switching network output stage switching part, and with the data work and the string manipulation that receive, finish the multiple connection of dateout, and data are exported.
Described single-board device, wherein, further comprise the slow processor of data input bullet, be used for requiring the signal time delay of adjustment from described high-speed data input string and processor input according to the sequential of data link, make described input signal satisfy the sequential requirement of switching network received signal, and the adjusted signal of described time delay is input to described three grades of switching network input stage switching parts.
Described single-board device wherein, further comprises:
The CPU control section is used for realizing the control action of exchange process;
The clock processing section is used to provide described single-board device work needed clock;
The host communication interface is used for communicating by letter with outside exchange main control computer, the order and/or to described main control computer uploaded state of continuing that receives that described main control computer sends;
The serial test interface is used for the single-board device of on-line operation is tested.
Described single-board device, wherein, described high-speed data input string and processor receive the high speed low voltage differential transfer signal of input, and it further comprises:
The multipath reception device is used to receive the high speed low voltage differential transfer signal of input;
One or more phase-locked loops, it is phase-locked to be used for clock that one or more incoming line is extracted, to produce required clock;
One or more deserializers are used for signal is gone here and there and changed;
Output register is used to export the low speed signal after going here and there and handling.
Described single-board device, wherein, described high-speed data output and string manipulation device output high speed low voltage differential transfer signal, it further comprises:
Phase-locked loop is used for outside input clock is carried out phase-locked, and produces internal clocking;
The input lock part is used to lock input signal;
Characteristic test sequence signal generator is used for sending test patterns under the chip testing pattern; And
One or more parallel-to-serial converters are used for signal is carried out and goes here and there conversion.
Described single-board device, wherein, the slow processor of described data input bullet further comprises: a dual port data memory, a dual port data memory are read an address generator and a dual port data memory write address generator; Described dual port data memory is read output signal according to the address storage input signal that described write address generator produces according to described address of reading the address generator generation.
Described single-board device, wherein, the read address, write address of described dual port data memory are generated by different clock controls; Described different clock comprises reference clock and the plate internal clock that is extracted by high speed low voltage differential transfer signaling interface.
Described single-board device, wherein, described three grades of switching network input stage switching parts, intergrade switching part and output stage switching parts further comprise a plurality of exchange chips; Wherein, per one or more in the output line of every chip is connected to the corresponding incoming line of every chip in the described intergrade switching part chipset respectively in the described input stage switching part chipset; In the described intergrade switching part chipset in the output line of every chip per one or more is connected to the corresponding incoming line of every chip in the described output stage switching part chipset respectively.
The present invention also provides a kind of method that realizes large capacity unblock time-division exchange network, wherein, comprising:
Step 3, three grades of switching network intergrade switching parts receive the dateout of described switching network input stage switching part, carry out second level exchange, and select the switching access of three grades of switching network output stage switching parts simultaneously;
Step 4, three grades of switching network output stage switching parts receive the dateout of described switching network intergrade switching part, carry out third level exchange, and export data to high-speed data output and string manipulation device;
Step 5, high-speed data output and string manipulation device receive the dateout of described switching network output stage switching part, and described dateout is done and string manipulation, data are exported after finishing the multiple connection of dateout.
Described method, wherein, after described step 1, further comprise a steps A, the slow processor of data inputs bullet receive through described step a string and handle after data, described data are carried out the time delay adjustment, so that the input of described three grades of switching networks can receive described data synchronously, and further the adjusted data of described time delay are input to described three grades of switching network input stage switching parts.
Described method wherein, comprises following subsequent steps:
The middle bridging chip with time interval resource that step a, poll are identified for exchanging does not all have time interval resource as whole network, then returns accordingly result and end;
Step b determines three grades of switching time slots that exchange is at different levels;
Step c, the physics of setting up described three grades of switching network input stages, intergrade and output stages continues;
Steps d is preserved subsequent data, continues and finishes.
Described method wherein, comprised further before described step a one judges the step whether output time solt has continued, in this way, then removed original continuing earlier.
Described method wherein, comprises following interrupted step:
Step a1 obtains the subsequent data of preserving;
Step b1 removes at different levels continuing;
Step c1, the time interval resource that bridging chip in the middle of described is discharged joins in the idle time slot formation;
Described method wherein, comprised further that before described step a1 one judges the step that output time solt is whether interrupted, in this way, then directly withdrawed from.
Compared with prior art, the present invention has adopted larger capacity exchange chip technology, three grades of switching networks and high speed LVDS technology such as (transmission of low voltage differential signaling low-voltage differential signal), make and reduced the device usage quantity in a large number when making up big capacity switching network such as 256K switching network, on a less veneer, realized large capacity unblock time-division exchange network.Very high because of interface signal speed simultaneously, the time-delay meeting of interface signal is different because of the difference of transmission medium, adopt high speed LVDS technology, make signal and clock synchronization, improved the stability of system, in addition, adopt high speed LVDS technology also to solve the physical circuit that enters big capacity switching network exchange and go out the lambda line problem.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is the structural representation of single-board device of the present invention;
Fig. 2 is the structural representation of the slow part of data bullet of the present invention;
Fig. 3 is the structural representation of three grades of switching networks of the present invention;
Fig. 4 is the flow chart that continues of the present invention;
Fig. 5 is the road flow chart of tearing open of the present invention;
Fig. 6 is the big capacity exchange chip technical pattern schematic diagram that the present invention adopts;
Fig. 7 is the LVDS export structure schematic diagram of output at a high speed and string manipulation device;
Fig. 8 is the LVDS input structure schematic diagram of high speed input string and processor.
Embodiment
Below in conjunction with accompanying drawing the present invention is realized that the enforcement of 256K unblock time-division exchange network technical scheme is described in further detail:
As shown in Figure 1, single-board device hardware module of the present invention comprises:
The work clock of veneer is provided by system clock, and the input of treatment system clocks is responsible in clock processing section 110, and provides work clock for the circuit such as switching network of veneer.
High-speed data input string and processor 101, this partial circuit is responsible for receiving high speed LVDS (transmission of the low voltage differential signaling low-voltage differential signal) signal of sending into from backboard (by the back board high-speed serial bus), extract LVDS signal reference clock, and high speed signal is carried out 1: n (n gets the integer value more than or equal to 1) string and tap are handled, signal after the processing is sent into the slow processor 102 of data input bullet, the slow processor 102 of data input bullet carries out the automatic time delay adjustment according to the clock that extracts to signal, make it satisfy the input timing of input stage switching network 103, data enter three grades of switching networks and carry out exchanges data under the controls of cpu system 107, directly export high-speed data output and string manipulation device 106 to through the data after the exchange, carry out n: 1 (n gets the integer value more than or equal to 1) also gone here and there and exported backboard (by the back board high-speed serial bus) in the Transform Sets.
Described high-speed data output and string manipulation device 106 use high speed LVDS technology as shown in Figure 7, mainly are made up of phase-locked loop 701, input lock part 702, characteristic test sequence signal generator 703 and the individual parallel-to-serial converter 704 of m (m gets the integer more than or equal to 1).Described characteristic test sequence signal generator 703 can send pseudo noise code, is used for sending test patterns under the chip testing pattern.701 pairs of outside input clocks of phase-locked loop carry out phase-locked and produce internal clocking offering parallel-to-serial converter 704 and importing sticking department 702 to carry out accurate sampled data, carry out again and go here and there conversion, reliably export receiving terminal with the characteristic test sequence signal of characteristic test sequence signal generator 703 generations is synthetic to high speed LVDS level equalization, realize the requirement of data centralization output.
Described high-speed data input string and processor 101 are opposite with high-speed data output and string manipulation device 106 processes, receive high speed LVDS signal (high speed low voltage differential transfer signal) and adopt deserializer to carry out the data dispersion treatment.As shown in Figure 8, mainly form by multipath reception device 801, the individual phase-locked loop 802 of m (m gets the integer more than or equal to 1), a m deserializer 803 and output register 810 etc.Each phase-locked loop is phase-locked to the clock that every road LVDS incoming line extracts, and produces clock and supplies with each road deserializer and output register 810, and wide by output register 810 output m groups is the low speed signal of n.
If the swap data of LVDS switching network uses PCM (the PULSE CODE Modulation of m group bit wide as n (n gets the integer value more than or equal to 1), pulse code modulation), and the words that do not adopt data centralization LVDS to export, the quantity that goes out lambda line so is 2*m*n, by high speed LVDS technology the PCM signal is concentrated output, the quantity that goes out lambda line so only is 2*m, can reduce the quantity that physics goes out lambda line greatly.
Be illustrated in figure 2 as the structural representation of the slow processor 102 of data input bullet, its main application is to adjust the time delay of extraneous input signal, satisfies the sequential requirement of switching network received signal when making it enter switching network.Mainly be to realize by a dual port data memory 204, dual port data memory 204 stores input signal according to two-port RAM write address generator 201, read address generator 203 according to two-port RAM then data are read, so the address that two-port RAM must strict control be read and write.Be the accuracy of assurance read-write two-port RAM data, the address that write address generator 201 and initial write address generator 206 are produced generates under the control of input data-interface extraction clock 205 (i.e. the reference clock that is extracted by high speed LVDS signaling interface); Reading address generator 203 generates under the control of plate internal clock 202 in 207 addresses that produced with initial write address generator.
If the 256K switching network still adopts the mode of " copy T ", then need 256 altogether according to the design of 16K exchange chip, it is unpractical wanting to plant 256 16 K exchange chips on a veneer, simultaneously also unacceptable aspect cost, therefore adopt scheme as shown in Figure 3, form one three grades exchanging array by 48 16 K exchange chips, each level has 16 16 K exchange chips (each sheet 16 K exchange chip provides 32 couples of 32M HW).Each sheet 16K exchange chip has 32 inputs and 32 output lines, and per two are connected to respectively on each chip of intergrade in 32 output lines of every 16K exchange chip of input stage switching network, have 16; Per two are connected to respectively on each chip of output stage in 32 output lines of every 16K exchange chip of intergrade switching network, have 16, and the physical connection method is as follows:
16K switching network (1) 301 the 1st, 2 output be connected to 16K switching network (17) 305 the 1st, 2 input;
16K switching network (1) 301 the 3rd, the 1st, 2 input that is connected to 16K switching network (18) 306 exported in 4 outputs successively;
And the like;
16K switching network (1) 301 the 29th, the 1st, 2 input that is connected to 16K switching network (31) 307 exported in 30 outputs successively;
16K switching network (1) 301 the 31st, the 1st, 2 input that is connected to 16K switching network (32) 308 exported in 32 outputs successively;
According to said method, 16K switching network (2) 302 all output lines are connected to the 3rd, 4 input of intergrade chip respectively; 16K switching network (15) 303 all output lines are connected to the 29th, 30 input of intergrade chip respectively; 16K switching network (16) 304 all output lines are connected to the 31st, 32 input of intergrade chip respectively; The physical connection method that each exchange chip of intergrade exports the output stage exchange chip to is consistent with the physical connection method that input stage exports intergrade to.As the connection of figure chip (305 to 308) to chip (309 to 312).
Can obtain according to mathematical method, above-mentioned exchanging array can be accomplished clog-free fully under the cooperation of software.
Blocking rate as the switch network architecture of Fig. 3 can be obtained by following formula:
Bi＝[1-(1-a)2]L*n
A is the occupancy of switching network, promptly Irish number;
L is the timeslot number that each the full crosspoint (a slice 16K exchange chip) in each grade links to each other with the single full crosspoint of other grades in three grades of switching networks, L=1024 in present networks;
N is the capacity of each full crosspoint, n=16384 in present networks;
N*L is the total number of paths that some input time slots may be walked to some output time solts;
The occupancy of supposing switching network is a=0.99, and this has been difficult to reach in switch system.The blocking rate that can calculate this moment is
Bi＝[1-(1-a)
2]
L*n＝[1-(1-0.99)
2]
1024*16384
＝2.18×10
-729＜＜10
-100
Therefore can think that this switching network is a choke free switching network.
Utilize the method for realization large capacity unblock time-division exchange network of the present invention may further comprise the steps:
Steps A, high-speed data input string and processor receive the backboard data, and carry out 1: n (n gets the integer value more than or equal to 1) tap is handled;
Step B, the slow processor of data inputs bullet receive string and handle after data, and carry out the automatic delay adjustment, can synchronous receiving data with the input that guarantees three grades of switching networks;
Step C, three grades of switching network input stage switching parts are responsible for Data Receiving, and carry out first order exchange, select the switching access of intergrade switching network simultaneously;
Step D, three grades of switching network intergrade switching parts are responsible for second level exchange, select the switching access of output stage switching network simultaneously;
Step e, three grades of switching network output stage switching parts are responsible for third level exchange, and dateout is sent into high-speed data output and string manipulation device;
Step F, high-speed data output and string manipulation device are n with the data of switching network output: 1 (n gets the integer value more than or equal to 1) multiple connection is given backboard after handling.
In three grades of switching networks, bridge joint effect in the middle of each sheet exchange chip in the intergrade switching network can be realized, can select different bridging chips so finish a switched connection, different connecting methods is arranged, but total principle at first is to make the bridge joint equalization of incidence of each chip of intergrade to continuing, and can improve the success rate of searching idle time slot in intergrade.Continue and interrupted before, the idle time slot formation of bridging chip in the middle of creating.
As Fig. 4, the handshaking procedure that large capacity unblock time-division exchange network of the present invention is once complete is as follows:
1) order (step 401) that continues;
2) judge whether output time solt has continued (step 402),, then remove original continue (step 403) earlier, as do not continue, then enter step 404 if continue;
3) determine middle bridging chip (step 404).The method of definite employing wheel continuous query of middle bridging chip, that is, the middle bridging chip of choosing specifically number for the last bridging chip of choosing number add 1,16 in the middle of the bridge joint chip number be 0～15, when the middle bridging chip that calculates number greater than 15 the time, just jump to 0.
4) whether idle time slot (step 405) is arranged all in the bridging chip I/O queue in the middle of the judgement,, then from I/O queue, take out idle time slot (step 407) if having; If no, judge whether the number of times of inquiry arrives 16 times (step 406), if do not reach 16 times, then change step 404 over to, choose next bridging chip; If reach 16 times, then return accordingly result and withdraw from (step 411).
5) from I/O queue, take out idle time slot (step 407).
6) determine three grades of switching time slots (step 408) that exchange is at different levels.
7) set up continue (steps 409) at different levels.
8) preserve subsequent data (step 410).
9) withdraw from (step 411), continue and finish.
As Fig. 5, once complete intermittent process is as follows:
1) road order (step 501) is torn in reception open;
2) judge output time solt whether intermittently (step 502),, then directly withdraw from (step 506) if interrupted.
3) according to the information acquisition that the continues subsequent data (step 503) at different levels of preserving.
4) remove continue (steps 504) at different levels.
5) the used input and output time slot of middle bridging chip, join in the idle time slot formation (step 505).
6) withdraw from (step 506), intermittently finish.
The internal structure of big capacity exchange chip as shown in Figure 6, the outside chip operation clock that provides is provided in clock processing section 605, offers chip core after treatment and uses.Input traffic is at first by depositing data storage 602 in after 601 samplings of data flow receiving unit, be called for short DM (DATA MEMORY), DM can deposit a frame input traffic, data cpu i/f 607 is accepted the outer CPU visit order, the data content of each receiving slot in can read access DM, cpu i/f 607 is put into the memory 604 that continues with the order request that continues that CPU assigns, be called for short CM (CONNECTION MEMORY), can deposit any one input time slot data in the input traffic of all output time solt correspondences of described output stream among the CM, CM is at DM like this, finish function of exchange under the cooperation of blender 606 and chip internal register 603, make any time slot input can exchange to any time slot output.Data flow output 608 receives the input signal of blender 606, output stream.The 16K exchange chip that this patent uses can be finished 16384 time gas exchange.It is the big capacity exchange chip of IDT72V73260 that one embodiment of the invention adopts model.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (12)
1. a single-board device of realizing large capacity unblock time-division exchange network is characterized in that, comprising:
High-speed data input string and processor are used to receive the high speed signal of input, and high speed signal made string and handle, and tap is the input signal of veneer switching network circuit identification;
Three grades of switching network input stage switching parts are used to receive the signal by described high-speed data input string and processor input, and according to the switched connection requirement, select output link to export three grades of switching network intergrade switching parts to;
Three grades of switching network intergrade switching parts are used to receive the dateout of described switching network input stage switching part, and according to the switched connection requirement, select output link to export three grades of switching network output stage switching parts to;
Three grades of switching network output stage switching parts are used to receive the dateout of described switching network intergrade switching part, and according to the switched connection requirement, select output link to export high-speed data output and string manipulation device to;
High-speed data output and string manipulation device are used to receive the dateout of described switching network output stage switching part, and with the data work and the string manipulation that receive, finish the multiple connection of dateout, and data are exported;
Further comprise the slow processor of data input bullet, be used for requiring the signal time delay of adjustment from described high-speed data input string and processor input according to the sequential of data link, make described input signal satisfy the sequential requirement of switching network received signal, and the adjusted signal of described time delay is input to described three grades of switching network input stage switching parts.
2. single-board device according to claim 1 is characterized in that, further comprises:
The CPU control section is used for realizing the control action of exchange process;
The clock processing section is used to provide described single-board device work needed clock;
The host communication interface is used for communicating by letter with outside exchange main control computer, the order and/or to described main control computer uploaded state of continuing that receives that described main control computer sends;
The serial test interface is used for the single-board device of on-line operation is tested.
3. single-board device according to claim 1 is characterized in that, described high-speed data input string and processor receive the high speed low voltage differential transfer signal of input, and it further comprises:
The multipath reception device is used to receive the high speed low voltage differential transfer signal of input;
One or more phase-locked loops, it is phase-locked to be used for clock that one or more incoming line is extracted, to produce required clock;
One or more deserializers are used for signal is gone here and there and changed;
Output register is used to export the low speed signal after going here and there and handling.
4. single-board device according to claim 3 is characterized in that, described high-speed data output and string manipulation device output high speed low voltage differential transfer signal, and it further comprises:
Phase-locked loop is used for outside input clock is carried out phase-locked, and produces internal clocking;
The input lock part is used to lock input signal;
Characteristic test sequence signal generator is used for sending test patterns under the chip testing pattern; And
One or more parallel-to-serial converters are used for signal is carried out and goes here and there conversion.
5. according to claim 1,3 or 4 described single-board devices, it is characterized in that the slow processor of described data input bullet further comprises: a dual port data memory, a dual port data memory are read an address generator and a dual port data memory write address generator; Described dual port data memory is read output signal according to the address storage input signal that described write address generator produces according to described address of reading the address generator generation.
6. single-board device according to claim 5 is characterized in that, the address of reading of described dual port data memory is generated by the control of plate internal clock, and write address is generated by the reference clock control that high speed low voltage differential transfer signaling interface extracts.
7. according to claim 1 or 6 described single-board devices, it is characterized in that described three grades of switching network input stage switching parts, intergrade switching part and output stage switching parts further comprise a plurality of exchange chips; Wherein, per one or more in the output line of every chip is connected to the corresponding incoming line of every chip in the described intergrade switching part chipset respectively in the described input stage switching part chipset; In the described intergrade switching part chipset in the output line of every chip per one or more is connected to the corresponding incoming line of every chip in the described output stage switching part chipset respectively.
8. a method that is applicable to the realization large capacity unblock time-division exchange network of the described single-board device of claim 1 is characterized in that, comprising:
Step 1, high-speed data input string and processor receive the high speed signal of input, and high speed signal work string and tap are handled;
Step 2, three grades of switching network input stage switching parts receive the signal of importing by described high-speed data input string and processor, carry out first order exchange, and select the switching access of three grades of switching network intergrade switching parts simultaneously;
Step 3, three grades of switching network intergrade switching parts receive the dateout of described switching network input stage switching part, carry out second level exchange, and select the switching access of three grades of switching network output stage switching parts simultaneously;
Step 4, three grades of switching network output stage switching parts receive the dateout of described switching network intergrade switching part, carry out third level exchange, and export data to high-speed data output and string manipulation device;
Step 5, high-speed data output and string manipulation device receive the dateout of described switching network output stage switching part, and described dateout is done and string manipulation, data are exported after finishing the multiple connection of dateout;
After described step 1, further comprise a steps A, the slow processor of data inputs bullet receive through described step a string and handle after data, described data are carried out the time delay adjustment, so that the input of described three grades of switching networks can receive described data synchronously, and further the adjusted data of described time delay are input to described three grades of switching network input stage switching parts.
9. method according to claim 8 is characterized in that, comprises following subsequent steps:
The middle bridging chip with time interval resource that step a, poll are identified for exchanging does not all have time interval resource as whole network, then returns accordingly result and end;
Step b determines three grades of switching time slots that exchange is at different levels;
Step c, the physics of setting up described three grades of switching network input stages, intergrade and output stages continues;
Steps d is preserved subsequent data, continues and finishes.
10. method according to claim 9 is characterized in that, comprises further before described step a one judges the step whether output time solt has continued, in this way, then removes original continuing earlier.
11. method according to claim 10 is characterized in that, comprises following interrupted step:
Step a1 obtains the subsequent data of preserving;
Step b1 removes at different levels continuing;
Step c1, the time interval resource that bridging chip in the middle of described is discharged joins in the idle time slot formation;
Steps d 1 withdraws from, and intermittently finishes.
12. method according to claim 11 is characterized in that, comprises further that before described step a1 one judges the step that output time solt is whether interrupted, in this way, then directly withdraws from.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2005100117957A CN1870833B (en) | 2005-05-26 | 2005-05-26 | Method of implement large capacity unblock time-division exchange network and its single-board device |
Applications Claiming Priority (1)
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|---|---|---|---|
| CN2005100117957A CN1870833B (en) | 2005-05-26 | 2005-05-26 | Method of implement large capacity unblock time-division exchange network and its single-board device |
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| Publication Number | Publication Date |
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| CN1870833A CN1870833A (en) | 2006-11-29 |
| CN1870833B true CN1870833B (en) | 2010-12-08 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1242659A (en) * | 1999-06-26 | 2000-01-26 | 深圳市中兴通讯股份有限公司 | Single chip and large capacity digital time division switching network |
| EP1073309A2 (en) * | 1999-07-28 | 2001-01-31 | Intellprop Limited | A non-blocking circuit switch |
| CN1466316A (en) * | 2002-06-07 | 2004-01-07 | 深圳市中兴通讯股份有限公司 | Compaction/decompaction method for realizing wire back panel large volume high speed exchange |
| CN1499893A (en) * | 2002-11-09 | 2004-05-26 | 深圳市中兴通讯股份有限公司 | Digital time division switching network |
| CN1529458A (en) * | 2003-09-26 | 2004-09-15 | 中兴通讯股份有限公司 | High-capacity hinder-free switching method in programme controlled switching network |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1242659A (en) * | 1999-06-26 | 2000-01-26 | 深圳市中兴通讯股份有限公司 | Single chip and large capacity digital time division switching network |
| EP1073309A2 (en) * | 1999-07-28 | 2001-01-31 | Intellprop Limited | A non-blocking circuit switch |
| CN1466316A (en) * | 2002-06-07 | 2004-01-07 | 深圳市中兴通讯股份有限公司 | Compaction/decompaction method for realizing wire back panel large volume high speed exchange |
| CN1499893A (en) * | 2002-11-09 | 2004-05-26 | 深圳市中兴通讯股份有限公司 | Digital time division switching network |
| CN1529458A (en) * | 2003-09-26 | 2004-09-15 | 中兴通讯股份有限公司 | High-capacity hinder-free switching method in programme controlled switching network |
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| Publication number | Publication date |
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| CN1870833A (en) | 2006-11-29 |
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