CN105740089B - A kind of network on three-dimensional chip fault tolerable circuit and its fault-tolerance approach based on data bit width recombination - Google Patents
A kind of network on three-dimensional chip fault tolerable circuit and its fault-tolerance approach based on data bit width recombination Download PDFInfo
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- CN105740089B CN105740089B CN201610048441.8A CN201610048441A CN105740089B CN 105740089 B CN105740089 B CN 105740089B CN 201610048441 A CN201610048441 A CN 201610048441A CN 105740089 B CN105740089 B CN 105740089B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
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Abstract
The invention discloses a kind of network on three-dimensional chip fault tolerable circuits and its fault-tolerance approach based on data bit width recombination, network on three-dimensional chip is made of n-layer chip, two layer wafer of arbitrary neighborhood is by more TSV vertical connections, characterized in that is provided with fault tolerable circuit on every layer wafer；Including interconnecting selecting module；The adaptive recombination module of data bit width；Sendaisle；Receiving channel；Data bit width is against recombination module.The present invention can improve the utilization rate of TSV, transmission delay be reduced, to ensure the correctness of data transmission.
Description
Technical field
The invention belongs to the fields of communication technology of integrated circuit network-on-chip (NoC), more particularly to one kind being based on bit wide weight
The weak optimization fault tolerable circuit and its fault-tolerance approach of group.
Background technology
Silicon hole (Through Silicon Via, TSV) technology is that the master of levels disparate modules is interconnected in three-dimensional chip
One of method is wanted, however due to the limitation of manufacturing technology level, some failures TSV is will appear after the completion of chip manufacturing, these
Failure TSV can lead to the failure of its even entire chip of Module Fail interconnected, and fault tolerable circuit can reduce failure TSV and bring
Influence, realize chip normally communicate.
《16th IEEE International On-Line Testing Symposium》2010 in 115-120 pages
‘Configurable serial fault-tolerant link for communication in 3d integrated
It proposes to remap mode using serial communication and signal in a systems ' texts, maps the data on fault-free channel and realize
It is fault-tolerant.Disadvantage is that：The scheme that this article is carried be first according to normally functioning TSV numbers in faulty channel to data into
Row grouping, then the data after grouping are mapped on fault-free channel and are transmitted.In view of the limitation of packet, for
Certain fault-tolerant target, the data width obtained after being grouped to data need not be equal to the number of normally functioning TSV, this
Cause to have TSV when data are mapped on fault-free channel and be in idle condition, i.e., can not utilize number simultaneously in the same time
According to all fault-free TSV in channel, and then lead to the increase of transmission delay.
Invention content
The present invention is in order to overcome the deficiencies of the prior art, it is proposed that a kind of network on three-dimensional chip appearance based on data bit width recombination
Wrong circuit and its fault-tolerance approach, it is intended to improve the utilization rate of TSV, and reduce transmission delay, to can ensure that data transmission just
True property.
Used technical solution is the present invention in order to achieve the above objectives：
The present invention it is a kind of based on data bit width recombination network on three-dimensional chip fault tolerable circuit, the network on three-dimensional chip be by
N-layer chip forms, and two layer wafer of arbitrary neighborhood is by more TSV vertical connections；Its main feature is that
Fault tolerable circuit is provided on the i-th layer wafer, i-th of fault tolerable circuit includes i-th layer of fault tolerable circuit transmitting terminal
With i-th of fault tolerable circuit receiving terminal；I-th of fault tolerable circuit transmitting terminal contains i-th of sendaisle, i-th of interconnection selection
Module, the adaptive recombination module of i-th of data bit width；I-th of fault tolerable circuit receiving terminal contains i-th of receiving channel and
I data bit width is against recombination module；I-th of sendaisle include：I-th of transmission control logic and i-th of transmission FIFO；
I-th of receiving channel include：I-th of reception control logic and i-th of reception FIFO；1≤i≤n；
Assuming that the i-th layer wafer needs to continuously transmit the initial data that bit wide is N to i+1 layer wafer；Then i-th layer crystal
Piece sends control logic by i-th and external initial data is stored in i-th of transmission FIFO；I-th of data bit width is certainly
The number M that recombination module obtains fault-free TSV between i-th layer wafer and i+1 layer wafer is adapted to, and at described i-th
It sends under the control of control logic after being successively read N initial data in i-th of sendaisle, by described N
Initial data is converted to M recombination datas and is sent to i-th of interconnection selecting module；I-th of interconnection selection mould
M of the recombination data is sent to i+1 layer wafer by block by M root fault-frees TSV；1≤M≤N；
The interconnection selecting module of the i+1 layer wafer receives M of the recombination data and passes to i+1 reception
Channel；The i+1 receiving channel receives control logic by i+1 and M of the recombination data is stored in i+1
Send FIFO；The i+1 data bit width recombination module constantly reads M recombination datas successively, and to the recombination data
Digit counted, when count value C is more than or equal to N, the i+1 data bit width recombination module is by C recombination numbers
According to the initial data and output for reverting to N；
Assuming that i+1 layer wafer needs to continuously transmit the initial data that bit wide is N to the i-th layer wafer；The then i+1 layer
Chip sends control logic by i+1 and external initial data is stored in i+1 transmission FIFO；The i+1 number
The number M of fault-free TSV between i-th layer wafer and i+1 layer wafer is obtained according to bit width self-adapting recombination module, and in institute
It states under the control of i+1 transmission control logic after being successively read N initial data in the i+1 sendaisle；
N of the initial data is converted into M recombination datas and is sent to the i+1 and interconnects selecting module；Described i-th
M of the recombination data is sent to the i-th layer wafer by+1 interconnection selecting module by M root fault-frees TSV；1≤M≤N；
The interconnection selecting module of i-th layer wafer, which receives M of the recombination data and passes to i-th of reception, leads to
Road；I-th of receiving channel receives control logic by i-th and M of the recombination data is stored in i-th of transmission
FIFO；I-th of data bit width constantly reads M recombination datas against recombination module successively, and to the recombination data
Digit is counted, and when count value C is more than or equal to N, i-th of data bit width is against recombination module by C recombination datas
Revert to N initial data and output；To realize the appearance of bidirectional data transfers between the i-th layer wafer and i+1 layer wafer
Wrong function.
The characteristics of network on three-dimensional chip fault tolerable circuit of the present invention, lies also in,
The adaptive recombination module of any one data bit width includes：Shift register Q, initialization controller, effectively
Data counter and shift controller；
The shift register Q obtains the number M of fault-free TSV；
The initialization controller carries out initialization process to the shift register Q, and 2 N initial data are deposited
Enter in the shift register Q；Meanwhile the valid data counter carries out the digit of data in the shift register Q
It counts, obtains count value C；
The shift register Q is removed high M-bit data by the shift controller, to form M recombination numbers
According to；
The shift controller is M mobile to a high position by remaining C-M data in the shift register Q；Meanwhile institute
It states valid data counter to count the digit of data in the shift register Q, obtains calculated value C '=C-M；
The shift controller judges whether C ' meets loading environment, when meeting loading environment, the shift controller
The next N initial data sent in FIFO are loaded into shift register Q, meanwhile, the valid data counter pair
The digit of data is counted in the shift register Q, obtains calculated value C "=C-M+N；To complete loading procedure；
Next high M-bit data is removed in the shift register Q；To complete shifting process；
The recombination data that N initial data are converted to M is realized with the shifting process and recycling for loading procedure.
Any one described data bit width includes against recombination module：Inverse recombination shift register QR, inverse recombination initialization control
Device, inverse recombination valid data counter and inverse recombination shift controller processed；
The inverse recombination shift controller obtains the bit wide N of data initial data；
The inverse recombination initialization controller is to the inverse recombination shift register QRInitialization process is carried out, by 2 M
The initial data deposit inverse recombination shift register QRIn；Meanwhile the inverse effective counter of recombination is to the inverse recombination
Shift register QRIn data bits counted, obtain count value CR；
The inverse recombination shift register is removed high N data by the inverse recombination shift controller, to form N
The initial data of position；
The inverse recombination shift controller is by described against recombination shift register QRIn remaining CR- N data are to high displacement
It is N dynamic；Meanwhile the inverse recombination valid data counter is to the inverse recombination shift register QRThe digit of middle data is counted
Number obtains calculated value C 'R=CR-N；
The inverse recombination shift controller judges C 'RWhether satisfaction shifts condition, when meeting displacement condition, the inverse weight
Group shift controller removes high N data in the inverse recombination shift register；To complete inverse recombination shifting process；
The next M recombination datas received in FIFO are loaded into inverse recombination displacement and posted by the inverse recombination shift controller
Storage QRIn；To complete inverse recombination loading procedure；
M recombination datas are reverted into N with the cycle realization of the inverse recombination shifting process and inverse recombination loading procedure
The initial data of position.
A kind of network on three-dimensional chip fault-tolerance approach based on data bit width recombination of the present invention, is applied to by n-layer chipset
At network on three-dimensional chip in, two layer wafer of arbitrary neighborhood is by more TSV vertical connections；Its main feature is that fault-tolerance approach is
It carries out as follows：
Step 1, defined variable x, and initialize x=1；1≤x≤X；Defined variable y, and initialize y=1；1≤y≤Y；
The initial data deposit that the bit wide that step 2, the i-th layer wafer send outside is N is sent in FIFO；1≤i≤n；
Step 3, the number M for obtaining fault-free TSV between the i-th layer wafer and i+1 layer wafer；
Step 4, the recombination data that the initial data that X bit wide is N is converted to Y M：
Step 4.1, delimiting period T, and initialize T=1；
Step 4.2, under the T period, read x-th of N initial data D from the transmission FIFOxAnd it is stored in
In shift register Q；Judge whether x=1 is true, if so, x+1 is then assigned to x, T+1 is assigned to T, and return to step
4.2；Otherwise, step 4.3 is executed；
Step 4.3, under the T period, the digit of initial data in the shift register Q is counted, obtain
Count value CT；
T+1 is assigned to T by step 4.4, under the T period, by high M-bit data H in the shift register QTIt moves
Go out；To form M recombination data Ry；
Step 4.5, under the T period, by remaining C in the shift register QTM-bit data moves M to a high position
Position；
Step 4.6, under the T period, the digit of initial data in the shift register Q is counted, obtain
Count value CT′；
Step 4.7, under the T+1 period, judge count value CT' whether meet loading environment, if satisfied, will then send
The initial data D of the positions N in FIFOx+2It is loaded into shift register Q, and to the position of initial data in the shift register Q
Number is counted, and count value C is obtainedT+1；If not satisfied, then directly executing step 4.8；
X+1 is assigned to x by step 4.8, judges whether x > X are true, if so, it indicates to complete X N initial data
Recombination；Otherwise, y+1 is assigned to y, and return to step 4.4 sequentially executes；
Step 5, initialization y=1；Initialize x=1；
M recombination datas are sent to i+1 layer wafer by step 6 by M root fault-frees TSV；
Step 7, the i+1 layer wafer receive the recombination data deposit of the positions the M received in FIFO；
The recombination data that Y bit wide is M is reverted to the initial data that X bit wide is N by step 8：
Step 8.1, initialization T=1, initialize y=1；
Step 8.2, under the T period, be successively read y-th of M recombination data R from the reception FIFOyAnd
The inverse recombination shift register Q of depositRIn；Judge whether y=1 is true, if so, y+1 is then assigned to y, T+1 is assigned to T, and
Return to step 8.2；Otherwise, step 8.3 is executed；
Step 8.3, under the T period, to the inverse recombination shift register QRThe digit of middle recombination data is counted
Number obtains count value CR_T；
T+1 is assigned to T by step 8.4, under the T period, judges CR_TWhether >=N is true, if so, it then will be described
Inverse recombination shift register QRMiddle high N data HR_TIt removes；To form N initial data Dx；And execute step 8.5；If
It is invalid, then follow the steps 8.7；
Step 8.5, under the T period, by the inverse recombination shift register QRIn remaining CR_T- N data are to height
Displacement is N dynamic；
Step 8.6, under the T period, to the inverse recombination shift register QRThe digit of middle recombination data is counted
Number obtains count value C 'R_T；And by C 'R_TIt is assigned to CR_T；
Y+1 is assigned to y by step 8.7, under the T period, will receive the recombination data R of the positions M in FIFOyLoad
To inverse recombination shift register QRIn, and to the inverse recombination shift register QRThe digit of middle recombination data is counted, and is obtained
Count value C "R_T, and by C "R_TIt is assigned to CR_T；
Step 8.8 judges whether y=Y is true, if so, it indicates to complete the recovery of Y M recombination datas；To real
The fault tolerance of existing data transmission between i-th layer wafer and i+1 layer wafer；Otherwise, x+1 is assigned to x, and return to step
8.4 sequences execute.
Compared with prior art, advantageous effects of the invention are embodied in：
1. the network on three-dimensional chip fault tolerable circuit proposed by the present invention based on data bit width recombination, for any one TSV
Fault condition, the data block that initial data can be split into bit wide equal to fault-free TSV numbers are transmitted, and are overcome existing
There is technology when turning serial transmission parallel, initial data, which is split into several groups, in the range of fault condition allows passes
It is defeated, the shortcomings that causing the data bit width of its single data transmission to be unable to reach maximum value.
2. the network on three-dimensional chip fault-tolerance approach proposed by the present invention based on data bit width recombination, can be according to fault-free
Initial data is split as multiple recombination data blocks, each recombination data by the number of TSV by the adaptive recombination module of data bit width
The width of block is equal to the number of fault-free TSV, so as to utilize all fault-free TSV simultaneously when transmitting each time, overcomes
When the prior art is due to transmitting grouping, the shortcomings that part TSV caused by the limitation of grouping number is in idle condition, carry
The high utilization rate of TSV.
3. the network on three-dimensional chip fault-tolerance approach proposed by the present invention based on data bit width recombination, can be according to TSV failures
Situation reuses all fault-free TSV.Compared with the prior art, the data bit width that the present invention is transmitted in primary transmission is more
Greatly, thus the delay smaller that generates, the shortcomings that overcoming the prior art transmission delay excessive since packet generates, reduces
Transmission delay.
Description of the drawings
Fig. 1 is the network on three-dimensional chip structure chart of the present invention；
Fig. 2 is chip overall structure figure of the present invention；
Fig. 3 is bit wide reformer core circuit figure of the present invention；
Fig. 4 is state machine state of the present invention transfer figure；
Fig. 5 is that bit wide reformer shift register of the present invention completes the state diagram after initialization；
Fig. 6 a are the operation diagram of bit wide reformer shift register of the present invention within a clock cycle；
Fig. 6 b are the state diagram of a clock cycle backward shift register of the invention；
Fig. 7 is the operation in the case where bit wide reformer shift register of the present invention needs load next clock cycle
Figure；
Fig. 8 a are operation diagram of the bit wide of the present invention against reformer shift register within a clock cycle；
Fig. 8 b are that bit wide of the present invention operates continuously figure against reformer shift register；
Fig. 9 is the transmission delay comparison diagram of the present invention and traditional fault-tolerance approach.
Specific implementation mode
As shown in Figure 1, network on three-dimensional chip is made of n-layer chip, between each two node of two layer wafer of arbitrary neighborhood
By more TSV vertical connections, in the present embodiment, it is assumed that network on three-dimensional chip is made of 3 layer wafers, is arranged on each layer
A kind of network on three-dimensional chip fault tolerable circuit based on data bit width recombination, each layer includes fault tolerable circuit transmitting terminal and fault tolerable circuit
Receiving terminal, wherein fault tolerable circuit transmitting terminal include sendaisle, interconnection selecting module, data bit width recombination module；Fault tolerable circuit
Receiving terminal includes receiving channel and data bit width against recombination module；
Wherein any one sendaisle includes sending control logic and transmission FIFO；Any one receiving channel includes connecing
It receives control logic and receives FIFO；
Wherein the adaptive recombination module of any one data bit width includes shift register Q, initialization controller, significant figure
According to counter and shift controller；Any one data bit width against recombination module include inverse recombination shift register QR, inverse recombination
Initialization controller, inverse recombination valid data counter and inverse recombination shift controller；
Assuming that the 1st layer wafer needs to continuously transmit the initial data that bit wide is N to the 2nd layer wafer；Then the 1st layer wafer
Control logic is sent by the 1st, and external initial data is stored in the 1st transmission FIFO；The 1st data bit width recombination
The shift register Q of module obtains the number M of fault-free TSV between the 1st layer wafer and the 2nd layer wafer,
The initialization controller of the adaptive recombination module of data bit width carries out initialization process to shift register Q, by 2
In N initial data deposit Q；Meanwhile valid data counter counts the digit of data in shift register Q, obtains
Obtain count value C；
Shift register Q is removed high M-bit data by shift controller, to form M recombination datas；
Shift controller is M mobile to a high position by remaining C-M data in shift register Q；Meanwhile valid data meter
Number device counts the digit of data in shift register Q, obtains calculated value C '=C-M；
Shift controller judges whether C ' meets loading environment, and when meeting loading environment, shift controller will be sent
Next N initial data in FIFO are loaded into shift register Q, meanwhile, valid data counter is to shift register Q
The digit of middle data is counted, and calculated value C "=C-M+N is obtained；To complete loading procedure；
Next high M-bit data is removed in shift register Q；To complete shifting process；
The recombination data that N initial data are converted to M is realized with above-mentioned shifting process and recycling for loading procedure.
Recombination data is sent to the 1st interconnection selecting module by the adaptive recombination module of data bit width；1st interconnection selection
M recombination datas are sent to the 2nd layer wafer by module by M root fault-frees TSV；1≤M≤N；
2nd data bit width against recombination module inverse recombination initialization controller to inverse recombination shift register QRIt carries out just
Beginningization processing, by the 2 M inverse recombination shift register Q of initial data depositRIn；Meanwhile the inverse effective counter of recombination is to inverse
Recombinate shift register QRIn data bits counted, obtain count value CR；
Inverse recombination shift register is removed high N data by inverse recombination shift controller, to form N original
Data；
Inverse recombination shift controller will inverse recombination shift register QRIn remaining CR- N data are N mobile to a high position；Together
When, inverse recombination valid data counter is to inverse recombination shift register QRThe digit of middle data is counted, and calculated value C ' is obtainedR
=CR-N；
Inverse recombination shift controller judges C 'RWhether satisfaction shifts condition, when meeting displacement condition, inverse recombination displacement control
Device processed removes high N data in inverse recombination shift register；To complete inverse recombination shifting process；
The next M recombination datas received in FIFO are loaded into inverse recombination shift register by inverse recombination shift controller
QRIn；To complete inverse recombination loading procedure；
M recombination datas are reverted into N with the cycle realization of above-mentioned inverse recombination shifting process and inverse recombination loading procedure
Position initial data and output.
Assuming that the 2nd layer wafer needs to continuously transmit the initial data that bit wide is N to the 1st layer wafer；Then the 2nd layer wafer
Control logic is sent by the 2nd, and external initial data is stored in the 2nd transmission FIFO；The 2nd data bit width recombination
The shift register Q of module obtains the number M of fault-free TSV between the 1st layer wafer and the 2nd layer wafer,
The initialization controller of the adaptive recombination module of data bit width carries out initialization process to shift register Q, by 2
In N initial data deposit Q；Meanwhile valid data counter counts the digit of data in shift register Q, obtains
Obtain count value C；
Shift register Q is removed high M-bit data by shift controller, to form M recombination datas；
Shift controller is M mobile to a high position by remaining C-M data in shift register Q；Meanwhile valid data meter
Number device counts the digit of data in shift register Q, obtains calculated value C '=C-M；
Shift controller judges whether C ' meets loading environment, and when meeting loading environment, shift controller will be sent
Next N initial data in FIFO are loaded into shift register Q, meanwhile, valid data counter is to shift register Q
The digit of middle data is counted, and calculated value C "=C-M+N is obtained；To complete loading procedure；
Next high M-bit data is removed in shift register Q；To complete shifting process；
The recombination data that N initial data are converted to M is realized with above-mentioned shifting process and recycling for loading procedure.
Recombination data is sent to the 2nd interconnection selecting module by the adaptive recombination module of data bit width；2nd interconnection selection
M recombination datas are sent to the 1st layer wafer by module by M root fault-frees TSV；1≤M≤N；
1st data bit width against recombination module inverse recombination initialization controller to inverse recombination shift register QRIt carries out just
Beginningization processing, by the 2 M inverse recombination shift register Q of initial data depositRIn；Meanwhile the inverse effective counter of recombination is to inverse
Recombinate shift register QRIn data bits counted, obtain count value CR；
Inverse recombination shift register is removed high N data by inverse recombination shift controller, to form N original
Data；
Inverse recombination shift controller will inverse recombination shift register QRIn remaining CR- N data are N mobile to a high position；Together
When, inverse recombination valid data counter is to inverse recombination shift register QRThe digit of middle data is counted, and calculated value C ' is obtainedR
=CR-N；
Inverse recombination shift controller judges C 'RWhether satisfaction shifts condition, when meeting displacement condition, inverse recombination displacement control
Device processed removes high N data in inverse recombination shift register；To complete inverse recombination shifting process；
The next M recombination datas received in FIFO are loaded into inverse recombination shift register by inverse recombination shift controller
QRIn；To complete inverse recombination loading procedure；
M recombination datas are reverted into N with the cycle realization of above-mentioned inverse recombination shifting process and inverse recombination loading procedure
Position initial data and output.
To realize the fault tolerance of bidirectional data transfers between the 1st layer wafer and the 2nd layer wafer.
In the present embodiment, a kind of network on three-dimensional chip fault-tolerance approach based on data bit width recombination, it is assumed that the 1st layer wafer needs
It then to be carried out as follows to the 2nd layer wafer transmission data：
Step 1, for ease of narration, it is assumed that current task have 500 bit wides be 64 initial data it is to be sent, i.e. N=64,
X=500；Fault-free TSV numbers are 50, i.e. M=50, then understand that the number of recombination data is Y=640；
Defined variable x, and initialize x=1；1≤x≤500；Defined variable y, and initialize y=1；1≤y≤640；
Step 2, as shown in Fig. 2, the 1st layer wafer is height in data valid signal Stb by the transmission control logic of this layer
When, external initial data deposit is sent into FIFO；
Step 3, the 1st layer wafer data bit width recombination module obtain fault-free between the 1st layer wafer and the 2nd layer wafer
The number M of TSV, it is assumed that M=50；
Step 4, the initial data for being 64 by bit wide are converted to the recombination data that bit wide is 50：
Step 4.1, delimiting period T, and initialize T=1；
Step 4.2, initialization data bit wide recombination module：
Shift register Q in data bit width recombination module, width are twice of data width, Q [q:P] it indicates in Q
The data of pth position to q；
The initialization of shift register Q is completed by the init state machine of such as Fig. 4, and process is as follows：It is not initialized
When, state machine is in idle condition, and is detected and is sent FIFO non-emptys, and state machine (draws high hair to FIFO transmissions load request is sent
FIFO is sent to read enabled), while state transition is to first loading cycle；Next period, initial data DxUnder the T period from
Send the high 64 i.e. Q [127 for reading and being loaded into shift register in FIFO:64], x+1 is assigned to x, T+1 is assigned to T,
State transition sends load request to second loading cycle, and to FIFO is sent；Next period, next initial data DxFrom
Send the low 64 i.e. Q [63 for reading and loading data into shift register Q in FIFO:0], while state machine jumps to the free time
State completes initialization, and the state of shift register Q is as shown in Figure 5 at this time；
Step 4.3, under the T period, valid data counter counts data bits in shift register Q,
Obtain count value CT=128；
T+1 is assigned to T by step 4.4, and under the T period, shift controller is by high 50 digit in shift register Q
According to HTIt removes, as shown in Figure 6 a；To form 50 recombination data Ry；
Step 4.5, under the T period, shift controller is by remaining C in shift register QT- 50 data are to height
Displacement is 50 dynamic, as shown in Figure 6 b, to complete shifting process；
Step 4.6, under the T period, valid data counter counts the data bits in shift register Q
Number obtains count value CT'=78；
Step 4.7, under the T+1 period, judge count value CT' whether meet loading environment, that is, judge at this time effectively
The value C of data counterTWhether ' < N are true, if so, it will then send the positions the N initial data D in FIFOx+2It is loaded into displacement
In register Q, and the data bits in Q is counted, obtains count value CT+1, CT+1=C 'T+ N, by CT+1It is assigned to CT, from
And loading procedure is completed, as shown in Figure 7；If not, then directly execute step 4.8；
X+1 is assigned to x by step 4.8, judges whether x > X are true, if so, it indicates to complete X N initial data
Recombination；Otherwise, y+1 is assigned to y, by CT' it is assigned to CT, and return to step 4.4 sequentially executes；
Step 5, initialization y=1；Initialize x=1；
50 recombination datas are sent to the 2nd layer wafer by step 6 by 50 fault-free TSV；
Step 7, the 2nd layer wafer receive receive 50 recombination data deposits in FIFO；
Step 8, the initial data that the recombination data that bit wide is 50 is reverted to bit wide 64：
Step 8.1, initialization T=1, initialize y=1；
Step 8.2, initialization data bit wide are against recombination module：
Data bit width is against the inverse recombination shift register Q in recombination moduleRInitialization by such as Fig. 4 init state machine
It completes, process is as follows：When not initialized, state machine is in idle condition, detect receive FIFO non-emptys, state machine to
It receives FIFO and sends load request (draw high receive FIFO read enabled), while state transition is to first loading cycle；Next week
Phase, recombination data RyIt reads and is loaded into against recombination shift register Q in FIFO from receiving under the T periodRHigh 50 i.e.
QR[127:78], y+1 is assigned to y, T+1 is assigned to T, state transition is sent to second loading cycle, and to FIFO is received
Load request；Next period, next recombination data RyIt is posted from receiving to read in FIFO and load data into inverse recombination displacement
Storage QRQ [77:28], while state machine jumps to idle state, completes initialization；
Step 8.3, under the T period, inverse recombination valid data counter is to inverse recombination shift register QRIn number
It is counted according to digit, obtains count value CR_T；
T+1 is assigned to T by step 8.4, under the T period, judges CR_TWhether >=64 is true, if so, it then will be inverse
Recombinate shift register QRMiddle high 64 data HR_TIt removes, as shown in Figure 8 a；To form 64 initial data Dx；And it executes
Step 8.5；If not, then follow the steps 8.7；
Step 8.5, under the T period, will inverse recombination shift register QRIn remaining CR_T- 64 data are to a high position
It is 64 mobile, as shown in Figure 8 b, complete the shifting process of inverse recombination；
Step 8.6, under the T period, inverse recombination valid data counter is to inverse recombination shift register QRMiddle data
Digit counted, obtain count value C 'R_T；And by C 'R_TIt is assigned to CR_T；
Y+1 is assigned to y by step 8.7, under the T period, will receive 50 recombination data R in FIFOyLoad
To inverse recombination shift register QRIn, complete the loading procedure of inverse recombination；And to inverse recombination shift register QRThe digit of middle data
It is counted, obtains count value C "R_T, and by C "R_TIt is assigned to CR_T；
Step 8.8 judges whether y=Y is true, if so, it indicates to complete the recovery of 640 50 recombination datas；From
And realize the fault tolerance of data transmission between the 1st layer wafer and the 2nd layer wafer；Otherwise, x+1 is assigned to x, and return to step
8.4 sequences execute.
The data that bit wide is exported against recombination module are the initial data that width is 64, and bit wide recombination and the inverse process recombinated do not have
There is change data information, therefore subsequent transmission and processing can be carried out.
A kind of network on three-dimensional chip fault-tolerance approach based on data bit width recombination, it is assumed that the 2nd layer wafer is needed to the 1st layer crystal
Piece transmission data is then executed still according to above step sequence, to realize two-way number between the 1st layer wafer and the 2nd layer wafer
According to the fault tolerance of transmission.
The delay comparison that the fault-tolerant networks of the present invention and the prior art transmit identical data is as shown in Figure 9.It can be seen that phase
Than in the prior art, the increase smaller of transmission delay of the present invention.
Claims (4)
1. a kind of network on three-dimensional chip fault tolerable circuit based on data bit width recombination, the network on three-dimensional chip is by n-layer chip
Composition, two layer wafer of arbitrary neighborhood is by more TSV vertical connections；It is characterized in that
Fault tolerable circuit is provided on the i-th layer wafer, i-th of fault tolerable circuit includes i-th of fault tolerable circuit transmitting terminal and i-th of appearance
Wrong circuit receiving terminal；I-th of fault tolerable circuit transmitting terminal contain i-th of sendaisle, i-th interconnection selecting module, i-th
The adaptive recombination module of data bit width；I-th of fault tolerable circuit receiving terminal contains i-th of receiving channel and i-th of data bit
Wide inverse recombination module；I-th of sendaisle include：I-th of transmission control logic and i-th of transmission FIFO；Described i-th
Receiving channel includes：I-th of reception control logic and i-th of reception FIFO；1≤i≤n；
Assuming that the i-th layer wafer needs to continuously transmit the initial data that bit wide is N to i+1 layer wafer；Then i-th layer wafer is logical
It crosses i-th and sends control logic by external i-th of transmission FIFO of initial data deposit；I-th of data bit width is adaptive
Recombination module obtains the number M of fault-free TSV between i-th layer wafer and i+1 layer wafer, and is sent at described i-th
It is original by described N under the control of control logic after being successively read N initial data in i-th of sendaisle
Data are converted to M recombination datas and are sent to i-th of interconnection selecting module；I-th of interconnection selecting module is by the M
The recombination data of position is sent to i+1 layer wafer by M root fault-frees TSV；1≤M≤N；
The interconnection selecting module of the i+1 layer wafer, which receives M of the recombination data and passes to i+1 and receive, leads to
Road；The i+1 receiving channel receives control logic by i+1 and M of the recombination data is stored in i+1 hair
Send FIFO；I+1 data bit width self-adapting recombination module constantly reads M recombination datas successively, and to the recombination data
Digit counted, when count value C is more than or equal to N, i+1 data bit width self-adapting recombination module is by C recombinations
Data revert to the initial data of N and output；
Assuming that i+1 layer wafer needs to continuously transmit the initial data that bit wide is N to the i-th layer wafer；The then i+1 layer wafer
Control logic is sent by i+1, and external initial data is stored in i+1 transmission FIFO；The i+1 data bit
Wide adaptive recombination module obtains the number M of fault-free TSV between i-th layer wafer and i+1 layer wafer, and described
Under the control of i+1 transmission control logic after being successively read N initial data in the i+1 sendaisle；By institute
N initial data are stated to be converted to M recombination datas and be sent to i+1 interconnection selecting module；The i+1 interconnection
M of the recombination data is sent to the i-th layer wafer by selecting module by M root fault-frees TSV；1≤M≤N；
The interconnection selecting module of i-th layer wafer receives M of the recombination data and passes to i-th of receiving channel；Institute
It states i-th of receiving channel and receives control logic by i-th of transmission FIFO of M of recombination data deposit by i-th；It is described
I-th of data bit width constantly reads M recombination datas against recombination module successively, and is counted to the digit of the recombination data
Number, when count value C is more than or equal to N, C recombination datas are reverted to N by i-th of data bit width against recombination module
Initial data simultaneously exports；To realize the fault tolerance of bidirectional data transfers between the i-th layer wafer and i+1 layer wafer.
2. network on three-dimensional chip fault tolerable circuit according to claim 1, characterized in that any one data bit width is adaptive
Recombination module includes：Shift register Q, initialization controller, valid data counter and shift controller；
The shift register Q obtains the number M of fault-free TSV；
The initialization controller carries out initialization process to the shift register Q, and 2 N initial data are stored in institute
It states in shift register Q；Meanwhile the valid data counter counts the digit of data in the shift register Q,
Obtain count value C；
The shift register Q is removed high M-bit data by the shift controller, to form M recombination datas；
The shift controller is M mobile to a high position by remaining C-M data in the shift register Q；Meanwhile described having
Effect data counter counts the digit of data in the shift register Q, obtains calculated value C '=C-M；
The shift controller judges whether C ' meets loading environment, and when meeting loading environment, the shift controller will be sent out
Next N initial data in FIFO are sent to be loaded into shift register Q, meanwhile, the valid data counter is to described
The digit of data is counted in shift register Q, obtains calculated value C "=C-M+N；To complete loading procedure；
Next high M-bit data is removed in the shift register Q；To complete shifting process；
The recombination data that N initial data are converted to M is realized with the shifting process and recycling for loading procedure.
3. network on three-dimensional chip fault tolerable circuit according to claim 1, characterized in that the inverse recombination of any one data bit width
Module includes：Inverse recombination shift register QR, inverse recombination initialization controller, inverse recombination valid data counter and inverse recombination move
Level controller；
The inverse recombination shift controller obtains the bit wide N of data initial data；
The inverse recombination initialization controller is to the inverse recombination shift register QRInitialization process is carried out, by 2 M originals
The beginning data deposit inverse recombination shift register QRIn；Meanwhile inverse recombination valid data counter is to the inverse recombination displacement
Register QRIn data bits counted, obtain count value CR；
The inverse recombination shift register is removed high N data by the inverse recombination shift controller, to form N
Initial data；
The inverse recombination shift controller is by described against recombination shift register QRIn remaining CR- N data move N to a high position
Position；Meanwhile the inverse recombination valid data counter is to the inverse recombination shift register QRThe digit of middle data is counted,
Obtain calculated value C 'R=CR-N；
The inverse recombination shift controller judges C 'RWhether satisfaction shifts condition, and when meeting displacement condition, the inverse recombination moves
Level controller removes high N data in the inverse recombination shift register；To complete inverse recombination shifting process；
The next M recombination datas received in FIFO are loaded into inverse recombination shift register by the inverse recombination shift controller
QRIn；To complete inverse recombination loading procedure；
M recombination datas are reverted to N with the cycle realization of the inverse recombination shifting process and inverse recombination loading procedure
Initial data.
4. a kind of network on three-dimensional chip fault-tolerance approach based on data bit width recombination is the three-dimensional for being applied to be made of n-layer chip
In network-on-chip, two layer wafer of arbitrary neighborhood is by more TSV vertical connections；It is characterized in that fault-tolerance approach is by following step
It is rapid to carry out：
Step 1, defined variable x, and initialize x=1；1≤x≤X；Defined variable y, and initialize y=1；1≤y≤Y；X is indicated
Fault-free TSV numbers, Y indicate to understand the number of recombination data；
The initial data deposit that the bit wide that step 2, the i-th layer wafer send outside is N is sent in FIFO；1≤i≤n；
Step 3, the number M for obtaining fault-free TSV between the i-th layer wafer and i+1 layer wafer, and XN=MY；
Step 4, the recombination data that the initial data that X bit wide is N is converted to Y M：
Step 4.1, delimiting period T, and initialize T=1；
Step 4.2, under the T period, read x-th of N initial data D from the transmission FIFOxAnd it is stored in displacement and posts
In storage Q；Judge whether x=1 is true, if so, x+1 is then assigned to x, T+1 is assigned to T, and return to step 4.2；Otherwise,
Execute step 4.3；
Step 4.3, under the T period, the digit of initial data in the shift register Q is counted, is counted
Value CT；
T+1 is assigned to T by step 4.4, under the T period, by high M-bit data H in the shift register QTIt removes；To
Form M recombination data Ry；
Step 4.5, under the T period, by remaining C in the shift register QTM-bit data is M mobile to a high position；
Step 4.6, under the T period, the digit of initial data in the shift register Q is counted, is counted
Value CT′；
Step 4.7, under the T+1 period, judge count value CT' whether meet loading environment, if satisfied, will then send FIFO
In the positions N initial data Dx+2Be loaded into shift register Q, and to the digit of initial data in the shift register Q into
Row counts, and obtains count value CT+1；If not satisfied, then directly executing step 4.8；
X+1 is assigned to x by step 4.8, judges whether x > X are true, if so, it indicates to complete the weight of X N initial data
Group；Otherwise, y+1 is assigned to y, and return to step 4.4 sequentially executes；
Step 5, initialization y=1；Initialize x=1；
M recombination datas are sent to i+1 layer wafer by step 6 by M root fault-frees TSV；
Step 7, the i+1 layer wafer receive the recombination data deposit of the positions the M received in FIFO；
The recombination data that Y bit wide is M is reverted to the initial data that X bit wide is N by step 8：
Step 8.1, initialization T=1, initialize y=1；
Step 8.2, under the T period, be successively read y-th of M recombination data R from the reception FIFOyAnd it is stored in inverse
Recombinate shift register QRIn；Judge whether y=1 is true, if so, y+1 is then assigned to y, T+1 is assigned to T, and return to step
Rapid 8.2；Otherwise, step 8.3 is executed；
Step 8.3, under the T period, to the inverse recombination shift register QRThe digit of middle recombination data is counted, and is obtained
Obtain count value CR_T；
T+1 is assigned to T by step 8.4, under the T period, judges CR_TWhether >=N is true, if so, then by the inverse weight
Group shift register QRMiddle high N data HR_TIt removes；To form N initial data Dx；And execute step 8.5；If not at
It is vertical, then follow the steps 8.7；
Step 8.5, under the T period, by the inverse recombination shift register QRIn remaining CR_T- N data are to high displacement
It is N dynamic；
Step 8.6, under the T period, to the inverse recombination shift register QRThe digit of middle recombination data is counted, and is obtained
Obtain count value C 'R_T；And by C 'R_TIt is assigned to CR_T；
Y+1 is assigned to y by step 8.7, under the T period, will receive the recombination data R of the positions M in FIFOyIt is loaded into inverse weight
Group shift register QRIn, and to the inverse recombination shift register QRThe digit of middle recombination data is counted, and count value is obtained
C″R_T, and by C "R_TIt is assigned to CR_T；
Step 8.8 judges whether y=Y is true, if so, it indicates to complete the recovery of Y M recombination datas；To realize the
The fault tolerance of data transmission between i layer wafers and i+1 layer wafer；Otherwise, x+1 is assigned to x, and return to step 8.4 is suitable
Sequence executes.
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