CN201594253U - Circuit design device adopting SRAM-imbedded FPGA to simulate TCAM - Google Patents

Abstract

The utility model relates to a circuit design device adopting SRAM-imbedded FPGA to simulate TCAM, which comprises a TCAM interface module, a TCAM configuration module and a plurality of SRAM search modules. The TCAM interface module includes a plurality of TCAM interface switch modules, a plurality of selector input modules and a plurality of selector output modules. The TCAM configuration module includes a search input operation unit and a search output unit. The SRAM search modules include a selector module, a plurality of decoder modules and a plurality of SRAM sub-modules. The circuit design device realizes TCAM function based on FPGA, is used for FPGA verification of ASIC, and finishes search acts of TCAM through the means of simulating TCAM and by embedding the SRAM in one FPGA, thereby not only simplifying FPGA verification of ASIC, saving cost, and realizing an interface verifying TCAM for ASIC when a TCAM chip is inaccessible.

Description

A kind of circuit design device that adopts FPGA embedded SRAM simulating TCAM

Technical field

The utility model relates to a kind of use large-scale gate array chip FPGA (Fieldprogrammable gate array able to programme, hereinafter to be referred as FPGA) in the process of proofing chip, relate in particular to and use the embedded SRAM of FPGA itself to realize ternary content addressable memory (Ternary ContentAddressable Memory, hereinafter to be referred as TCAM) function, come the communication between proofing chip and the plug-in TCAM and the device of application.

Background technology

Prior art can embed the TCAM model that can support, as shown in Figure 1 on the checking pcb board when using FPGA to verify high-end communication chip.TCAM interface module by comprehensive ASIC realizes being connected and the checking of application between checking ASIC and the different model TCAM at different FPGA.Like this, just brought following problem:

1) again FPGA is carried out comprehensive wiring once for TCAM interface of every checking with regard to needs.Reduced verification efficiency.

2) the TCAM model of supporting for ASIC is many more, and the plug-in TCAM of required checking is just many more.Cost is also just big more.

3) when TCAM that ASIC supported be that manufacturer is about to the new model released, the new model of perhaps just having issued, and also can't obtain checking ASIC the time TCAM just at chip.And has only the TCAM document of this model.The TCAM of this model can't be verified in the emulation testing of FPGA more fully so.

Therefore, also there is defective in existing technology, and awaits improving and development.

The utility model content

The purpose of this utility model is to provide a kind of and realizes the TCAM function based on FPGA, is used for the FPGA checking of ASIC, makes the mode by simulating TCAM, utilizes embedded SRAM in a FPGA, finishes the device of the behavior of searching of TCAM.

For achieving the above object, the utility model proposes a kind of circuit design device of the FPGA of employing embedded SRAM simulating TCAM, it is characterized in that this device comprises:

The TCAM interface module: it includes plural TCAM interface modular converter (TCAM0 interface, TCAM1 interface ... the TCAMN interface), MUX load module (MUXin) and MUX output module (MUXout);

TCAM configuration module: comprise and search the input operation unit and search output unit;

Plural number SRAM searches piece (Block0, Block1 ... BlockN): each this SRAM searches piece and includes selector module (MUX), plural decoder module (decode) and plural SRAM submodule.

Wherein, described TCAM interface module receives the TCAM instruction of ASIC output, the key word (key) or the configuration signal that become needs to search the TCAM instruction transformation according to its corresponding instruction agreement by described each TCAM interface modular converter, and select a set of keyword according to selected TCAM model or configuration signal is sent into described TCAM configuration module by described MUX load module.

Described TCAM interface module also will become the standard of the TCAM of each model to export from address (index) and coupling (hit) information translation that described TCAM configuration module feeds back, and select one group and send back to ASIC in described MUX output module (MUXout).

Described TCAM configuration module is used for that the information that spreads out of from described TCAM interface module is sent into described each SRAM and searches piece and search; And with lookup result address (index) and the coupling (hit) information send interface module to TCAM.

Described plural SRAM searches piece and searches the data (Data) that are complementary with key word and the register of mask (Mask) information at the SRAM submodule, and selects different decoder module loopback address (index) and coupling (hit) information to the TCAM configuration module by described MUX.

Described SRAM searches in each SRAM submodule of piece two clocks, and one is the low frequency simulation clock of ASIC, also is the instruction input and output synchronous clock of TCAM; Another is the clock of upper frequency among the SRAM, the clock of upper frequency can all read through in the address realm with SRAM in the cycle at a simulation clock, the value that reads out is compared with sending the key word that comes to, and comparative result is stored in the register of SRAM submodule.

Simultaneously, the utility model has also proposed a kind of supporting with said apparatus, adopts the circuit design method of FPGA embedded SRAM simulating TCAM, and it comprises the steps:

1) selection needs the TCAM model of use, and the TCAM interface module is sent in the TCAM instruction of ASIC output;

2) each TCAM interface modular converter (TCAM0 interface, the TCAM1 interface in the TCAM interface module ... the TCAMN interface) key word (key) or the configuration signal that becomes needs to search the TCAM instruction transformation according to its corresponding instruction agreement, and select a set of keyword according to selected TCAM model or configuration signal is sent into the TCAM configuration module by one group of MUX load module (MUXin);

3) the TCAM configuration module is sent this set of keyword and corresponding information into each SRAM again and is searched piece (Block0, Block1 ... BlockN) search in the SRAM submodule;

4) clock of upper frequency all reads through in the address realm with SRAM in a simulation clock in each SRAM submodule, the value that reads out is compared with sending the key word that comes to, and comparative result is stored in the register of SRAM submodule;

5) if calculating the back, data that read a certain address in the SRAM submodule (Data) and mask (Mask) information is complementary with key word, so corresponding bit will be set to " 1 ", and the value of this group register can be exported to decoder module (Decode) from the SRAM submodule;

6) decoder module is worth according to this, has judged whether that certain address and keyword matching arrive, and sends Hit information if any coupling, and will in this group register the position that " 1 " should be arranged be parsed the value that becomes the address;

7) each SRAM searches the address (index) of piece generation and mates (hit) information and passes TCAM configuration module and TCAM interface module back, in the TCAM interface module, each TCAM interface modular converter can become the standard of the TCAM of each model to export address (index) and coupling (hit) information translation of bringing, selects one group and send back to ASIC in MUX output module (MUXout).

Wherein, the quantity of searching piece of the SRAM in the described step 3) can be determined according to the size of the RAM of the TCAM of the resource of FPGA and required checking; After key word was sent into SRAM and searched in the piece, SRAM searched the size of piece according to key word, reconfigures key word, and sends in each SRAM submodule and search.

Described SRAM searches in each SRAM submodule of piece two clocks, and one is the low frequency simulation clock of ASIC, also is the instruction input synchronous clock of TCAM; Another is the clock of upper frequency among the SRAM.

If there are a plurality of addresses to be matched in the described step 6) in the register, when promptly having a plurality of " 1 " in this register, then with the lowest address position as coupling.

MUX module (MUX) is selected different decoder module output according to the size of carrying out search key.

The TCAM configuration module is according to address (index) and coupling (hit) information that attribute is selected corresponding SRAM to search piece to send back to of searching of key word in the described step 7), and this address (index) and coupling (hit) information are sent the interface module to TCAM.

When using the FPGA checking, often need to use simultaneously several FPGA, and adopt the mode that reduces frequency to come function and the interface of ASIC are verified for large-scale network A SIC chip.And the utility model is by the mode of simulating TCAM (eTCAM), in a FPGA, utilize embedded SRAM, finish the behavior of searching of TCAM, not only simplified the FPGA checking of ASIC, saved cost, and make in the time can't obtaining the TCAM chip, ASIC is verified the interface of TCAM provides feasibility.

Description of drawings

Fig. 1 is the principle module map of the FPGA checking of existing band TCAM;

Fig. 2 substitutes the principle module map of the FPGA checking of TCAM for the utility model;

Fig. 3 adopts the circuit design module figure of FPGA embedded SRAM simulating TCAM for the utility model.

Embodiment

The circuit design of the employing FPGA embedded SRAM simulating TCAM that the utility model disclosed is a kind of based on FPGA realization TCAM function, and the FPGA checking that is used for ASIC detects.As shown in Figure 2, the utility model adopts the mode of eTCAM (emulation TCAM, i.e. simulating TCAM), utilizes embedded SRAM in a FPGA, finishes the behavior of searching of TCAM.

Be illustrated in figure 3 as the construction module figure that the utility model adopts FPGA embedded SRAM simulating TCAM circuit, it includes the TCAM interface module, and TCAM configuration module and SRAM search piece module Block0, Block1 ... BlockN.Wherein, comprise in the TCAM interface module that example changed interface modular converter TCAM0 interface, the TCAM1 interface of various TCAM ... the TCAMN interface, MUX load module MUXin and MUX output module MAXout; The TCAM configuration module comprises to be searched the input operation unit and searches output unit.

Plural number SRAM searches piece Block0, Block1 ... BlockN, it includes MUX module MUX respectively, plural decoder module decode and SRAM submodule.Wherein also have one group of register and two clocks in each SRAM submodule, these two clocks are respectively the clock of upper frequency among the low frequency simulation clock (also being the instruction input and output synchronous clock of TCAM) of ASIC and the SRAM.

For the circuit design of above-mentioned simulating TCAM, the utility model is realized the behavior of searching of TCAM as follows:

The first, after the TCAM model that chooses required use, the TCAM interface module is sent in the TCAM instruction of ASIC output;

Second, each TCAM interface modular converter TCAM0 interface in the TCAM interface module, TCAM1 interface ... key word key or configuration signal that the TCAMN interface becomes need search with the TCAM instruction transformation according to its corresponding instruction agreement (these command protocols can obtain in corresponding TCAM document), and select a set of keyword key according to selected TCAM model or configuration signal is sent into the TCAM configuration module by one group of MUX load module MUXin.

The 3rd, the TCAM configuration module is sent this set of keyword key and corresponding information into each SRAM that searches again and is searched piece Block0, Block1 ... among the BlockN, SRAM searches the quantity of piece and can determine according to the size of the RAM of the TCAM of the resource of FPGA and required checking.

The 4th, send into SRAM at key word key and search piece Block0, Block1 ... after among the BlockN, SRAM searches the size of piece according to key word key, reconfigures key word key, and sends in each piece SRAM submodule and search.As, when the size of key is 80 bits, then the submodule of each SRAM will independently be searched the unit as one, the key that accepts 80 bits searches, when if key is 160 bits, then every adjacent two SRAM submodules are searched the unit as one group, accept high 80 bits respectively and low 80 bits are searched.When should key being 320 bits or 640 bits, 4 or 8 SRAM submodules need be formed one and search the unit, therefore, can select the number of SRAM submodule according to required size reasonable of carrying out the maximum key of emulation.

The 5th, two clocks are arranged in each SRAM submodule, one is the low frequency simulation clock of ASIC, also is the instruction input and output synchronous clock of TCAM; Another is the clock of upper frequency among the SRAM, it can all read through in the address realm with SRAM in a simulation clock, and the value that will read out compares with the key that sends to, in the SRAM submodule, also has one group of register, this group register is used for storing comparative result, and its data bit width is the degree of depth of SRAM.

The 6th, if Data that read a certain address and Mask calculate back and key word key coupling, so corresponding bit will be set to " 1 ", and the value of this group register can be exported to decoder module Decode from the SRAM submodule.

The 7th, decoder module Decode is worth according to this, judged whether that certain address and key match, send the Hit signal if any coupling, and will in this register the position that " 1 " should be arranged be parsed the value that becomes the address, if there are a plurality of addresses to be matched in this register, that is to say, when having a plurality of " 1 " in this register, then with the lowest address position as coupling, this also meets the TCAM search rule of most of model.MUX module MUX selects different Decode group output according to the size of the key that searches.

The 8th, after each SRAM searches address information index that piece produces and match information hit and passes the TCAM configuration module back, select corresponding SRAM to search address information index and match information hit that piece is sent back to TCAM configuration module Rigen according to the attribute of searching of key, and this address information index and match information hit sent the interface module to TCAM, in the TCAM interface module, each interface modular converter TCAM0 interface, the TCAM1 interface ... the standard output that the TCAMN interface can become each model TCAM with the index that brings and hit conversion of signals is selected one group and is sent back to ASIC in MUX output module MUXout.

Technology contents of the present utility model and technical characterictic have disclosed as above; yet those of ordinary skill in the art still may be based on teaching of the present utility model and announcements and are done all replacement and modifications that does not deviate from the utility model spirit; therefore; the utility model protection domain should be not limited to the content that embodiment discloses; and should comprise various do not deviate from replacement of the present utility model and modifications, and contained by the present patent application claim.

Claims (2)

1. circuit design device that adopts FPGA embedded SRAM simulating TCAM is characterized in that comprising:

The TCAM interface module: it includes plural TCAM interface modular converter, MUX load module and MUX output module;

TCAM configuration module: comprise and search the input operation unit and search output unit;

Plural number SRAM searches piece: each this SRAM searches piece and includes selector module, plural decoder module and plural SRAM submodule.

2. the circuit design device of employing FPGA embedded SRAM simulating TCAM as claimed in claim 1, it is characterized in that: described SRAM searches in each SRAM submodule of piece two clocks, one is the low frequency simulation clock of ASIC, also is the instruction input and output synchronous clock of TCAM; Another is the clock of upper frequency among the SRAM, is used for SRAM read data clock.

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