CN111175635B - Integrated circuit testing device - Google Patents
Integrated circuit testing device Download PDFInfo
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- CN111175635B CN111175635B CN201911425270.6A CN201911425270A CN111175635B CN 111175635 B CN111175635 B CN 111175635B CN 201911425270 A CN201911425270 A CN 201911425270A CN 111175635 B CN111175635 B CN 111175635B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The invention relates to an integrated circuit testing device which comprises a testing machine table, a programmable circuit and a signal conversion circuit, wherein the programmable circuit is respectively and electrically connected with a vector storage module and the signal conversion circuit of the testing machine table. The signal conversion circuit is used for electrically connecting the test chip. The vector storage module is used for storing the compressed test vectors and determining the test result of the test chip according to the compression response returned by the programmable circuit. The compression response is a response obtained by compressing the test response returned by the test chip by the programmable circuit. The programmable circuit is used for decompressing the compressed test vector and outputting the compressed test vector to the test chip and compressing the test response. The signal conversion circuit is used for aligning the decompressed test vectors, performing logic level conversion output, receiving the test response and transmitting the test response back to the programmable circuit. The decompression and compression work of the test vector is prepositioned to the programmable circuit, so that the storage and transmission pressure of the test vector of the test machine is reduced, and the test efficiency is greatly improved.
Description
Technical Field
The invention relates to the technical field of circuit testing, in particular to an integrated circuit testing device.
Background
With the increasing scale of integrated circuits, the wafer area of the integrated circuits is also increasing, and the integrated circuits inevitably have failed transistors during the manufacturing process, so that the efficient detection of failed units in the integrated circuits, such as the failed transistors, is of great significance in reducing the testing cost of the integrated circuits.
Taking a common sequential integrated circuit as an example, a common test method at present adopts a scan chain mode to replace a register with a scan register, so as to realize control over each register. The test vectors are input into the integrated circuit bit by bit in a serial manner, which may make the length of a single test vector longer, and the time consumption is longer in the process of applying the test vectors by an Automatic Test Equipment (ATE), so it is necessary to compress and optimize the test vectors. In a conventional integrated circuit testing method, test vectors are compressed on a testing machine or compressed on a testing chip (i.e., an integrated circuit to be tested). However, in the implementation process, the inventor finds that the traditional integrated circuit testing mode still has the problem of low testing efficiency.
Disclosure of Invention
In view of the above, it is necessary to provide an integrated circuit testing apparatus capable of greatly improving the testing efficiency in view of the above-mentioned problems of the conventional integrated circuit testing method.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:
the integrated circuit testing device comprises a testing machine table, a programmable circuit and a signal conversion circuit, wherein the programmable circuit is respectively and electrically connected with a vector storage module and the signal conversion circuit of the testing machine table, and the signal conversion circuit is used for electrically connecting a testing chip;
the vector storage module is used for storing the compressed test vectors and determining the test result of the test chip according to the compression response returned by the programmable circuit; the compression response is a response obtained by compressing the test response returned by the test chip by the programmable circuit;
the programmable circuit is used for decompressing the compressed test vector and outputting the compressed test vector to the test chip, and compressing the test response; the signal conversion circuit is used for aligning the decompressed test vectors, performing logic level conversion output, receiving the test response and transmitting the test response back to the programmable circuit.
In one embodiment, the programmable circuit comprises a decompression processing unit and a compression processing unit;
the input port of the decompression processing unit is electrically connected with the vector output port of the vector storage module, the output port of the decompression processing unit is electrically connected with the transmission input port of the signal conversion circuit, and the decompression processing unit is used for decompressing the compressed test vector and performing transmission processing according to the type of the test vector;
the output port of the compression processing unit is electrically connected with the response input port of the vector storage module, the input port of the compression processing unit is electrically connected with the return output port of the signal conversion circuit, and the compression processing unit is used for compressing and outputting the test response.
In one embodiment, the decompression processing unit comprises a decompression circuit, a protocol encoding circuit, a regular data generating circuit and an output gating circuit;
the input port of the decompression circuit is electrically connected with the vector output port of the vector storage module, and the output port of the decompression circuit is electrically connected with the input ports of the protocol coding circuit and the regular data generating circuit respectively;
the input port of the output gating circuit is respectively and electrically connected with the output ports of the protocol coding circuit and the regular data generating circuit, and the output port of the output gating circuit is electrically connected with the sending input port of the signal conversion circuit;
the decompression circuit is used for decompressing the compressed test vectors, the protocol coding circuit is used for packaging the test vectors of the protocol class, the rule data generation circuit is used for generating the test vectors of the rule class on line, and the output gating circuit is used for gating and sending the output data of the protocol coding circuit or the rule data generation circuit.
In one embodiment, the decompression processing unit further comprises an offset calculation circuit, an input end of the offset calculation circuit is electrically connected with an output port of the decompression circuit, and an output end of the offset calculation circuit is electrically connected with an input port of the output gating circuit;
the offset calculation circuit is used for generating a test vector of the initial value plus the offset mode, and the output gating circuit is also used for gating and transmitting output data of the offset calculation circuit.
In one embodiment, the decompression processing unit further comprises a data translation circuit, an input end of the data translation circuit is electrically connected with an output port of the decompression circuit, and an output end of the data translation circuit is electrically connected with an input port of the output gating circuit;
the data translation circuit is used for sending the translation test vectors in a set data period, and the output gating circuit is also used for gating and sending the output data of the data translation circuit.
In one embodiment, the compression processing unit comprises a compression circuit and a protocol decoding circuit;
the output port of the compression circuit is electrically connected with the response input port of the vector storage module, the input port of the compression circuit is electrically connected with the output port of the protocol decoding circuit, and the input port of the protocol decoding circuit is electrically connected with the return output port of the signal conversion circuit;
the protocol decoding circuit is used for carrying out protocol decoding output on the test response of the protocol class, and the compression circuit is used for carrying out compression output on the test response output by the protocol decoding circuit.
In one embodiment, the compression processing unit further comprises a data rearrangement circuit and an input strobe circuit;
the input port of the compression circuit is respectively and electrically connected with the output ports of the protocol decoding circuit and the data rearrangement circuit, the output port of the input gating circuit is respectively and electrically connected with the input ports of the protocol decoding circuit and the data rearrangement circuit, and the input port of the input gating circuit is electrically connected with the return output port of the signal conversion circuit;
the input gating circuit is used for gating the protocol decoding circuit or the data rearrangement circuit according to the type of the test response, and the data rearrangement circuit is used for carrying out data rearrangement on the test response of the non-protocol class and carrying out online verification on the test response of the storage rule class.
In one embodiment, the programmable circuit is an FPGA chip or a CPLD device.
In one embodiment, the integrated circuit testing apparatus further includes a controller, the controller is electrically connected to the vector storage module and the programmable circuit respectively;
the controller is used for sending a test control signal to the programmable circuit and sending the compressed test vector to the vector storage module for storage.
In one embodiment, the control engine is further configured to update the programmable logic and control algorithm in the programmable circuit based on the test protocol, the test rule data, and the vector offset data.
One of the above technical solutions has the following advantages and beneficial effects:
according to the integrated circuit testing device, the programmable circuit and the signal conversion circuit are arranged at the front end of the testing machine, so that the flexible configurable characteristic of the programmable circuit can be utilized, a test file is divided into two parts, namely a compressed test vector and a test operation part, the compressed test vector is stored in a vector storage module of the testing machine, and the functions of decompression processing of the compressed test vector, compression processing of a test response correspondingly returned after the test vector is applied to a test chip and the like are realized by the programmable circuit. Therefore, the work of decompressing and compressing the test vector is placed in the programmable circuit at the front end of the test machine, the storage and sending pressure of the test vector of the test machine is obviously reduced, the test delay caused by repeated loading of the vector due to overlarge test vector is reduced, and the aim of greatly improving the test efficiency is fulfilled.
Drawings
Fig. 1 is a diagram illustrating conventional huffman coding;
FIG. 2 is a schematic diagram of a first circuit configuration of an integrated circuit testing apparatus in one embodiment;
FIG. 3 is a schematic diagram of a second circuit configuration of the integrated circuit testing apparatus in one embodiment;
FIG. 4 is a schematic diagram of a third circuit configuration of the integrated circuit testing apparatus in one embodiment;
FIG. 5 is a diagram illustrating a fourth circuit configuration of the integrated circuit testing apparatus according to an embodiment;
FIG. 6 is a schematic diagram of a fifth circuit configuration of the integrated circuit testing apparatus in one embodiment;
FIG. 7 is a schematic diagram of a sixth circuit configuration of the integrated circuit testing apparatus in one embodiment;
FIG. 8 is a diagram illustrating the test structure of the integrated circuit testing apparatus according to one embodiment;
FIG. 9 is a logic diagram of the programmable circuit and data generation in the vector memory block in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element and integrated therewith or intervening elements may be present, i.e., indirectly connected to the other element.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In a conventional integrated circuit test method, compression of a test vector is mainly implemented based on test vector compatibility, and an Automatic Test Pattern Generator (ATPG) algorithm is usually used to generate the test vector. Because there are many xs (can be 0, also can be 1) in the test vector, through comparing, can fuse many test vectors to reduce the quantity of test vector. Taking one of the traditional test vector fusion modes as an example, four test vectors are provided, which are t respectively1＝01X，t2＝0X1，t30X0 and t4X01. Finding test vector t by comparison1And a test vector t3Can be fused to form t13010, test vector t2And a test vector t4Can be fused to form t24001, so that four test vectors are compressed into two testsAnd testing vectors to achieve the purpose of reducing the number of the test vectors. However, the test vector compression method adopts a static data fusion method, which can satisfy the preliminary data compression, and the inventor finds in practice that the number of generated test vectors is still large for a large-scale integrated circuit, the test vector compression method cannot be applied, the actual test efficiency is still low, and the required test cost is high.
In order to further reduce the number of test vectors, another conventional test vector compression method is a huffman coding-based test vector compression method, data compression is performed by using an information theory to obtain further compressed test vectors, and the compressed test vectors are sent from an ATE machine to a test chip. The test chip is internally provided with a test vector decompression circuit, and after decompression and reduction are carried out on the compressed test vectors, the compressed test vectors are applied to a test unit in the test chip, so that the test efficiency improvement effect of a certain degree is achieved. Fig. 1 shows a schematic view of huffman coding. The inventor finds in practice that in an actual test, the huffman coding-based test vector compression method has higher requirements on hardware of a test chip, a special hardware decompression circuit needs to be correspondingly designed, a coding rule needs to be designed in advance, and after a test vector is modified, the performance of the decompression circuit and the performance of a compression circuit are poor, the applicability is poor, and the test efficiency is obviously reduced. Based on the test efficiency defect existing in the conventional integrated circuit test mode, the embodiment of the present application provides the following technical solutions.
Referring to fig. 2, in one embodiment, an integrated circuit testing apparatus 100 is provided, which includes a testing machine, a programmable circuit 14, and a signal conversion circuit 16. The programmable circuit 14 is electrically connected to the vector storage module 12 and the signal conversion circuit 16 of the testing machine, respectively, and the signal conversion circuit 16 is electrically connected to the testing chip 101. The vector storage module 12 is used for storing the compressed test vectors and determining the test result of the test chip 101 according to the compressed response returned by the programmable circuit 14. The compressed response is a response obtained by compressing the test response returned by the test chip 101 by the programmable circuit 14. The programmable circuit 14 is used for decompressing the compressed test vectors and outputting them to the test chip 101, and compressing the test responses. Signal conversion circuit 16 is used to align the decompressed test vectors and perform logic level conversion output, and to receive the test response and then transmit it back to programmable circuit 14.
It can be understood that the specific type of the tester, that is, the automatic tester widely used in the art, may be selected according to the application cost and the needs of the application scenario in the actual application. The programmable circuit 14 refers to a device having a programmable logic function, and may be various types of independent (or embedded) field programmable logic devices, complex programmable logic devices, or other programmable logic devices in the art, and the specific type may be selected according to application needs, as long as it can be used to undertake the required decompression of test vectors, compression and feedback of test responses, and other required test flow control functions.
Based on the dynamically configurable characteristics of the programmable circuit 14, the operation programs (i.e., configurable operation data) such as the test vector decompression rule, the test response compression rule, the data calculation and the test flow control required by the test process, which are applied in the field, can be written into the programmable circuit 14 at the front end of the test machine in advance, so that the programmable circuit 14 can share the corresponding test functions during the test. Thus, in a new test scenario in which a test vector needs to be replaced, the configurable operation data in the programmable circuit 14 can be updated corresponding to the replaced test vector, so that adaptation of the new test scenario can be completed without additionally replacing a test machine to obtain other test circuit units arranged on the test chip 101. Signal translation circuitry 16 is electrical signal translation circuitry between programmable circuitry 14 and test chip 101 and may be any type of test interface unit commonly used in the art.
The test chip 101 is also the integrated circuit chip waiting for testing. The test vectors are various types of test vectors to be applied to the test chip 101 in the art. The compressed test vectors are compressed vectors obtained by vector compressing each test vector according to a conventional vector compression rule, so that the storage capacity of the test vectors in the vector storage module 12 is reduced. The compressed test vectors may be pre-loaded into the vector storage module 12 of the test machine for standby, or may be accessed to an external controller (or called test controller) or a test management server through the test machine, and the controller or the test management server is immediately loaded into the vector storage module 12 of the test machine before the test. The vector storage module 12 of the test machine may further store an expected response for performing a comparison analysis on the compressed response corresponding to the test response, so as to determine a test result of the test chip 101, for example, whether there are failure units, the number and the location of the failure units, the failure type, and the like in the test chip 101, where a specific expected response is determined by test contents required by the test chip 101 in the art, and is not specifically limited in this specification.
Specifically, in this embodiment, the test machine does not undertake compression and decompression of the test vectors, but directly stores the compressed test vectors. When the test chip 101 needs to be tested, the test chip 101 may be connected to the integrated circuit testing apparatus 100 through the signal conversion circuit 16 to form a test link. In the testing stage, the vector storage module 12 of the testing machine transmits the compressed testing vector to the programmable circuit 14 according to a preset testing time sequence, and the compressed testing vector is decompressed by the programmable circuit 14 and then restored to the original testing vector. The programmable circuit 14 further aligns and logic-level-converts the recovered test vector by the signal conversion circuit 16, and sends the test vector to the test chip 101. Test chip 101 receives the test vectors and generates corresponding test responses, which are passed through signal conversion circuit 16 to programmable circuit 14. The programmable circuit 14 compresses the returned test vector to form a corresponding compressed response, and transmits the compressed response to the vector storage module 12 of the test machine. The returned compression response is verified and analyzed by the vector storage module 12 to obtain the test result of the test chip 101.
The integrated circuit testing device 100 is configured with the programmable circuit 14 and the signal conversion circuit 16 at the front end of the testing machine, so that the flexible configurable characteristic of the programmable circuit 14 can be utilized to divide the testing file into two parts, namely, a compressed testing vector and a testing operation part, the compressed testing vector is stored in the vector storage module 12 of the testing machine, and the functions of decompression processing of the compressed testing vector, compression processing of a corresponding returned testing response after the testing vector is applied to the testing chip 101, and the like are realized by the programmable circuit 14. Therefore, the work of decompressing and compressing the test vector is placed in the programmable circuit 14 at the front end of the test machine, the storage and sending pressure of the test vector of the test machine is obviously reduced, the test delay caused by repeated loading of the vector due to overlarge test vector is reduced, and the aim of greatly improving the test efficiency is fulfilled.
Referring to fig. 3, in one embodiment, programmable circuit 14 includes a decompression processing unit 142 and a compression processing unit 144. The input port of the decompression processing unit 142 is electrically connected to the vector output port of the vector storage module 12, and the output port of the decompression processing unit 142 is electrically connected to the transmission input port of the signal conversion circuit 16. The decompression processing unit 142 is configured to decompress the compressed test vectors and perform transmission processing according to the types of the test vectors. An output port of the compression processing unit 144 is electrically connected to a response input port of the vector storage module 12. The input port of the compression processing unit 144 is electrically connected to the return output port of the signal conversion circuit 16. The compression processing unit 144 is used for performing compression output on the test response.
It is understood that, in the programmable circuit 14, two data processing and transmission links can be formed by pre-configuration based on the hardware environment provided by the variable circuit, one is the link where the decompression processing unit 142 is located, and the other is the link where the compression processing unit 144 is located. The programmable circuit 14 may be one, and thus, the decompression processing and compression processing unit 144 may be provided on one programmable circuit 14 at the same time. The programmable circuits 14 may also be two separate sub-circuit boards, so that the decompression processing unit 142 may be disposed on one programmable circuit 14, and the compression processing unit 144 may be disposed on the other programmable circuit 14, and the specific disposition may be determined according to the actual application needs.
Accordingly, the signal conversion circuit 16 is also provided with dual signal channels: a transmit channel and a backhaul channel. The transmission output port of the signal conversion circuit 16 is electrically connected to the vector input port of the test chip 101, and the return input port of the signal conversion circuit 16 is electrically connected to the response output port of the test chip 101, so as to provide a transmission channel required for transmitting the test vector and other logic level signals for testing to the test chip 101, and a return channel required for returning the test response to the compression processing unit 144.
Specifically, in the test phase, the vector storage module 12 transmits the compressed test vector to the decompression processing unit 142, and the compressed test vector is decompressed by the decompression processing unit 142 and then restored to the original test vector. The decompression processing unit 142 further aligns and logic-level-converts the recovered test vector by the signal conversion circuit 16, and then transmits the test vector to the test chip 101. The test chip 101 receives the test vector and generates a corresponding test response, and the test response enters the compression processing unit 144 through the return channel of the signal conversion circuit 16. The compression processing unit 144 compresses the returned test vector to form a corresponding compression response, and transmits the compression response to the vector storage module 12 of the test machine. The returned compression response is verified and analyzed by the vector storage module 12 to obtain the test result of the test chip 101.
By the arrangement of the decompression processing unit 142 and the compression processing unit 144, the prepositive effects of the functions of test vector compression and decompression, test response compression and feedback and the like at the front end of the test machine can be efficiently realized, and the design and the arrangement of an on-chip test circuit on the test chip 101 are not required. The scale of the test vector on the test machine is reduced, the scale of test data on the test machine is reduced, the time-consuming duration of the test machine in the test vector application process is shortened, and therefore the test efficiency is better high.
Referring to fig. 4, in one embodiment, the decompression processing unit 142 includes a decompression circuit 1422, a protocol encoding circuit 1424, a rule data generating circuit 1426, and an output gating circuit 1428. An input port of the decompression circuit 1422 is electrically connected to a vector output port of the vector storage module 12, and output ports of the decompression circuit 1422 are electrically connected to input ports of the protocol encoding circuit 1424 and the rule data generating circuit 1426, respectively. An input port of the output gating circuit 1428 is electrically connected to output ports of the protocol encoding circuit 1424 and the rule data generating circuit 1426, respectively, and an output port of the output gating circuit 1428 is electrically connected to a transmission input port of the signal converting circuit 16. The decompression circuit 1422 is used to decompress the compressed test vectors. Protocol encoding circuitry 1424 is used to encapsulate test vectors for protocol classes. The rule data generation circuit 1426 is used to generate the test vectors of the rule classes online. The output gating circuit 1428 is used to gate and transmit the output data of the protocol encoding circuit 1424 or the rule data generating circuit 1426.
It is understood that the functional circuits described above can be formed based on the circuit hardware basis provided by programmable circuit 14 through the configuration of programmable circuit 14, respectively, and are used for respectively assuming the basic test functions of vector decompression function, test rule generation and protocol coding, etc. required in the integrated circuit test in the field. For example, a test file required for testing the test chip 101 may be divided into two parts, one part is a test vector, and the other part is a configurable operation file, and the operation file is written into the programmable circuit 14 to form each unit circuit with a corresponding function. The data output by each functional circuit is finally output by the output gating circuit 1428, and the output gating circuit 1428 may turn on the corresponding processing circuit according to the type of the test vector that needs to be sent currently, so as to send the test vector of the corresponding type. In each test vector obtained after decompression and recovery of the compressed test vector, the vector type of each test vector is different according to different test contents, and can be specifically determined according to the type of the existing test vector in the field.
Specifically, after the compressed test vectors are transmitted from the vector output port of the vector storage module 12 to the decompression circuit 1422, the compressed test vectors are decompressed in the decompression circuit and restored to the original test vectors, and the test vectors of different types are processed and output by different circuits. After the decompression circuit decompresses and obtains the original vector data, the test vector of the protocol class is sent to the protocol encoding circuit 1424 for sending processing, so that the protocol encoding circuit 1424 correspondingly generates target (i.e. the protocol of the test vector pair) protocol data, and encapsulates the data to be sent. For rule-like test vectors, such as for vector storage rule-like test vectors of vector storage module 12, the decompression circuit sends the type of test vector to rule data generation circuit 1426 for on-line generation, such as generating test rule data or vector offset data corresponding to the aforementioned vector storage rule. The foregoing specific packaging processing and online generation flow, etc. can be understood by referring to the conventional transmission processing flow of the test vector, and are not described in detail in this specification. The data generated by the protocol encoding circuit 1424 and the rule data generating circuit 1426 is finally transmitted through the multiplexing output strobe circuit 1428.
By the arrangement of the unit circuits, the decompression of the test vector and the preposition of processing work before the test is applied are realized, the compression and the decompression at the test vector level are realized, and the test delay caused by multiple times of loading of the test vector is reduced. In addition, for the test chip 101, as the SoC (system on chip) chip is standardized, the interfaces inside and outside the test chip 101 are standardized interfaces; with the advent of serial buses, testing based on serial bus interfaces has become an important point of testing. For the test data with the protocol, the protocol related part needs to be packaged with the original test data to be loaded on the test chip 101 for testing, and the data amount of the packaged test vector is increased by a small amount compared with the data amount of the test vector before packaging. Therefore, by setting the unit circuits, the pressure of the test machine for processing the test vectors can be further reduced, and the multiplexing and the expansion of the output port of the whole programmable circuit 14 can be realized.
Referring to fig. 5, in one embodiment, the decompression processing unit 142 further includes an offset calculation circuit 1429. An input terminal of the offset calculation circuit 1429 is electrically connected to an output port of the decompression circuit 1422, and an output terminal of the offset calculation circuit 1429 is electrically connected to an input port of the output gate 1428. The offset calculation circuit 1429 is configured to generate a test vector of the initial value plus the offset pattern. The output gating circuit 1428 is also used to gate and transmit the output data of the offset calculation circuit 1429.
It will be appreciated that the offset calculation circuit 1429 is also configured by the programmable circuit 14 based on the circuit hardware basis provided by the programmable circuit 14 to share the sending processing work of the test machine for one type of test vector. Specifically, for a compressed test vector generated by using an initial value plus offset mode, after decompression, the decompression circuit sends the type of test vector to the offset calculation circuit 1429, and the offset calculation circuit 1429 performs generation processing on the type of vector data, where a specific generation processing flow may be understood by referring to a conventional transmission processing flow of a test vector, and details are not repeated in this specification.
Through the arrangement of the offset calculation circuit 1429, the partial vector with a small distance change of the test vector in the vector storage unit on the test machine can be stored in a form of adding an offset to an initial value, and corresponding decompression and transmission processing is completed in the programmable circuit 14. Therefore, the characteristic of less offset digit can be utilized to further reduce the test vector scale, thereby more effectively improving the test efficiency.
In an embodiment, for an application scenario where a random number generator is used to generate a compressed test vector, similarly, the offset calculation circuit 1429 may be set as a corresponding generation circuit on the decompression processing unit 142, so that the effect of sending the test vector of this type on the front end of the test machine can be achieved.
Referring to fig. 6, in one embodiment, the decompression processing unit 142 further includes a data translation circuit 1427. An input terminal of the data shifting circuit 1427 is electrically connected to an output port of the decompression circuit 1422, and an output terminal of the data shifting circuit 1427 is electrically connected to an input port of the output strobe circuit 1428. The data shift circuit 1427 is configured to transmit a shift-type test vector in a set data cycle. The output strobe circuit 1428 is also used to strobe and transmit the output data of the data shift circuit 1427.
It will be appreciated that the data translation circuit 1427 is also configured by the programmable circuit 14 based on the circuit hardware basis provided by the programmable circuit 14, thereby sharing the task of sending test vectors that are sent directly without processing after decompression. The set data period is a test vector transmission period preset according to the test requirement of the test chip 101, and is used for indicating the transmission period of the test vector which is not required to be processed after decompression. Specifically, the decompression circuit directly sends the test vectors that do not need to be processed after decompression to the data translation circuit 1427, and the data translation circuit 1427 sends the test vectors in a set data period after the set data period comes, so that the test vectors are sent to the signal conversion circuit 16 through the output gating circuit 1428 for conversion and output.
Through the setting of the data translation circuit 1427, the test vectors which do not need to be processed additionally after decompression can be sent in a set data period, the test vector sending pressure of the test machine is further shared, and the effect of further improving the test efficiency is achieved.
Referring to fig. 7, in one embodiment, the compression processing unit 144 includes a compression circuit 1442 and a protocol decoding circuit 1444. An output port of the compression circuit 1442 is electrically connected to a response input port of the vector storage block 12, and an input port of the compression circuit 1442 is electrically connected to an output port of the protocol decoding circuit 1444. The input port of the protocol decoding circuit 1444 is electrically connected to the feedback output port of the signal conversion circuit 16. The protocol decoding circuit 1444 is configured to perform protocol decoding on the test response of the protocol class and output the test response. The compression circuit 1442 is used for compressing and outputting the test response output by the protocol decoding circuit 1444.
It is understood that the compression circuit 1442 and the protocol decoding circuit 1444 may also be formed based on the circuit hardware foundation provided by the programmable circuit 14 by configuring the programmable circuit 14, for example, writing a file for implementing functions such as data compression and protocol decoding in an operation file required by a test into the compression processing unit 144, and respectively configured to undertake functions of protocol decoding and returning data compression required in an integrated circuit test in the field.
Specifically, the test responses generated by the test chip 101 correspond to the test vectors, and therefore, different types of test vectors may cause the test chip 101 to generate corresponding types of test responses. After the test vectors related to the protocol are applied to the test chip 101, the test chip 101 generates a test response corresponding to the protocol class. After the test response of this type enters the protocol decoding circuit 1444, the test response is subjected to protocol decoding by the protocol decoding circuit 1444 and then output to the compression circuit 1442. The compression circuit 1442 compresses the data according to a set compression rule (which may be determined by an expected response stored by the vector storage module 12 in the test machine using the compression rule), and outputs the compressed data to the vector storage module 12 for data comparison and analysis, so as to obtain a test result of the test chip 101.
Through the arrangement of the compression circuit 1442 and the protocol decoding circuit 1444, the protocol decoding and compression work of the returned data is preposed in the programmable circuit 14, the working pressure of a testing machine is reduced, and meanwhile, the on-chip circuit transformation of the testing chip 101 can be avoided, so that the purposes of improving the testing efficiency and reducing the testing cost are achieved.
In one embodiment, as shown in fig. 7, the compression processing unit 144 further includes a data reordering circuit 1446 and an input gating circuit 1448. The input ports of the compression circuit 1442 are electrically connected to the output ports of the protocol decoding circuit 1444 and the data rearranging circuit 1446, respectively. The output port of the input gating circuit 1448 is electrically connected to the input port of the protocol decoding circuit 1444 and the input port of the rearrangement circuit, and the input port of the input gating circuit 1448 is electrically connected to the return output port of the signal conversion circuit 16. The input gating circuit 1448 is used to gate the protocol decoding circuit 1444 or the data reordering circuit 1446 according to the type of test response. The data rearrangement circuit 1446 is used for performing data rearrangement on the test response of the non-protocol class and performing online verification on the test response of the storage rule class.
It can be understood that the arrangement of the data rearrangement circuit 1446 and the input strobe circuit 1448 can be understood by referring to the arrangement of the compression circuit 1442 and the protocol decoding circuit 1444, and the files for implementing the functions of data rearrangement, verification analysis, path selection, and the like in the operation files required by the test are written into the compression processing unit 144, so as to configure the corresponding unit circuits.
Specifically, as different types of test vectors are applied to the test chip 101 for testing, the types of test responses generated by the test chip 101 may also increase accordingly, for example, the planned test responses that do not relate to the protocol portion, such as the regularized test responses to the vector storage module 12 and the test responses to other regularized tests, may be specifically determined by the types of test vectors used in the actual test. In the case of returning a plurality of different types of test responses, the input gating circuit 1448 may gate the corresponding unit circuit according to the type of the test response, and send the test response to the unit circuit processing the corresponding type of test response for processing. For example, the returned test response is a non-protocol type test response, the input gating circuit 1448 gates the connection link with the data reordering circuit 1446, and sends the type of test response to the data reordering circuit 1446. The data rearrangement circuit 1446 rearranges data of the input non-protocol test response, performs online verification analysis on the test response of the storage rule class (i.e., the regularization test type of the vector stored in the vector memory), and preliminarily verifies the correctness of the test response. The test response processed by the data rearrangement circuit 1446 is compressed by the compression circuit 1442 and then transmitted to the vector storage module 12 for data comparison and analysis, so as to obtain a test result of the test chip 101.
Through the arrangement of the data rearrangement circuit 1446 and the input gating circuit 1448, the data rearrangement and analysis verification of other returned data are performed in advance, the working pressure of a testing machine is further reduced, the testing delay is reduced, and the purpose of further improving the testing efficiency is achieved.
In one embodiment, programmable circuit 14 is an FPGA chip or a CPLD device. It can be understood that the programmable circuit 14 can be implemented by using an FPGA chip or a CPLD device commonly used in the art, where the FPGA chip can be set independently of the test machine, or can be set in an embedded FPGA chip manner, such as being embedded in the test machine, so as to improve the integration level of the entire test apparatus. The FPGA chip or the CPLD device has the characteristics of low application cost, high operation processing efficiency and flexibility and configurability. Therefore, the setting of each unit circuit is realized by applying the FPGA chip or the CPLD device, when different test vectors need to be replaced facing different test chips 101, only the test file under the corresponding test scene needs to be written into the programmable circuit 14 for configuration, and no on-chip modification needs to be performed on the test chip 101, thereby reducing the test cost. The FPGA chip or the CPLD device can also realize the port multiplexing during the decompression sending processing of different types of test vectors and the port multiplexing during the return compression processing of different similar test responses, effectively realize the port expansion with the test chip 101, and have higher test efficiency and lower cost.
Referring to FIG. 8, in one embodiment, the integrated circuit testing apparatus 100 further includes a controller 18. The controller 18 is electrically connected to the vector storage module 12 and the programmable circuit 14, respectively. The controller 18 is used for sending test control signals to the programmable circuit 14 and sending the compressed test vectors to the vector storage module 12 for storage.
It can be understood that the controller 18 is a control device for providing the same control function of the whole chip test system, and may be an upper computer used for chip testing in the field, a main control device in a test machine, or a separately arranged test controller.
Specifically, based on the flexible configurability of the programmable circuit 14, such as an FPGA chip, the controller 18 may divide a test file (which may be loaded in advance by a tester or downloaded online with a test management server) used in a current test scenario into two parts before a test is started, where one part is a test vector of different types, and the other part is an operation file for completing data calculation, data decompression, data compression, protocol encoding and decoding, and other test operation functions required in the test. The controller 18 may compress the test vector according to a predetermined compression rule, such as but not limited to a huffman code based test vector compression method, and then send the compressed test vector to the vector storage module 12 of the testing machine. The controller 18 writes the operation file into the programmable circuit 14, for example, sends the operation file to the programmable circuit 14 in the form of a control signal, so that the programmable circuit 14 performs automatic configuration according to the operation file, so as to complete the required decompression and compression, protocol encoding and decoding, and the like when the test chip 101 is tested.
Through the setting of the controller 18, the field configuration of the programmable circuit 14 can be realized, so that the work of decompressing and compressing the test vector can be performed by being preposed to the front end of the test machine in a dynamic loading manner. The vector storage module 12 only needs to store the compressed test vectors, expected responses and other information related to the test configuration, so that the test machine does not need to undertake the decompression of the test vectors and the compression of the test responses, the storage and transmission pressure of the test vectors is reduced, and the test vectors of different types can be rapidly dynamically configured through the controller 18 when being changed, thereby further improving the test efficiency.
Referring to FIG. 9, in one embodiment, the control engine 18 is also configured to update the programmable logic and control algorithms in the programmable circuit 14 based on the test protocol, the test rule data, and the vector offset data.
It is understood that the test protocol, the test rule data, the vector offset data, and the like are data of a test file predetermined for the test chip 101 to be tested in the art. Logic for data generation in the programmable circuit 14 and the vector storage module 12 is shown in fig. 9, and the controller 18 may extract relevant vector data during a test vector generation stage, so as to divide a test vector into a plurality of portions according to test items and generate test data respectively. Therefore, when different types of test chips 101 need to be tested, the controller 18 can update the programmable circuit 14 according to the test file data of different test chips 101, so as to implement adaptation of the required test logic and the test flow control function when the test chip 101 is tested.
Through the configuration updating function provided by the controller 18 to the programmable circuit 14, the test deployment can be completed quickly without any on-chip modification of the test chip 101, and the test scenario adaptability of the integrated circuit test device 100 is improved.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. The integrated circuit testing device is characterized by comprising a testing machine table, a programmable circuit and a signal conversion circuit, wherein the programmable circuit is respectively and electrically connected with a vector storage module of the testing machine table and the signal conversion circuit, and the signal conversion circuit is used for being electrically connected with a testing chip;
the vector storage module is used for storing the compressed test vectors and determining the test result of the test chip according to the compression response returned by the programmable circuit; the compression response is obtained by compressing the test response returned by the test chip by the programmable circuit;
the programmable circuit is used for decompressing the compressed test vector, outputting the compressed test vector to the test chip and compressing the test response; the signal conversion circuit is used for aligning the decompressed test vectors, performing logic level conversion output, receiving the test response and transmitting the test response back to the programmable circuit;
the programmable circuit comprises a decompression processing unit and a compression processing unit;
the input port of the decompression processing unit is electrically connected with the vector output port of the vector storage module, the output port of the decompression processing unit is electrically connected with the transmission input port of the signal conversion circuit, and the decompression processing unit is used for decompressing the compressed test vector and performing transmission processing according to the type of the test vector;
the output port of the compression processing unit is electrically connected with the response input port of the vector storage module, the input port of the compression processing unit is electrically connected with the feedback output port of the signal conversion circuit, and the compression processing unit is used for compressing and outputting the test response.
2. The integrated circuit test apparatus of claim 1, wherein the programmable circuit comprises two separate sub-circuit boards; the decompression processing unit and the compression processing unit are respectively arranged on the two sub circuit boards.
3. The integrated circuit test device of claim 1, wherein the decompression processing unit comprises a decompression circuit, a protocol encoding circuit, a regular data generation circuit, and an output strobe circuit;
the input port of the decompression circuit is electrically connected with the vector output port of the vector storage module, and the output port of the decompression circuit is electrically connected with the input ports of the protocol coding circuit and the rule data generating circuit respectively;
the input port of the output gating circuit is electrically connected with the output ports of the protocol coding circuit and the regular data generating circuit respectively, and the output port of the output gating circuit is electrically connected with the sending input port of the signal conversion circuit;
the decompression circuit is used for decompressing the compressed test vectors, the protocol coding circuit is used for packaging the test vectors of the protocol class, the rule data generation circuit is used for generating the test vectors of the rule class on line, and the output gating circuit is used for gating and sending the output data of the protocol coding circuit or the rule data generation circuit.
4. The integrated circuit testing device of claim 3, wherein the decompression processing unit further comprises an offset calculation circuit, an input terminal of the offset calculation circuit is electrically connected to the output port of the decompression circuit, and an output terminal of the offset calculation circuit is electrically connected to the input port of the output gating circuit;
the offset calculation circuit is used for generating the test vector of an initial value plus an offset mode, and the output gating circuit is also used for gating and sending the output data of the offset calculation circuit.
5. The integrated circuit testing device according to claim 3 or 4, wherein the decompression processing unit further comprises a data shifting circuit, an input terminal of the data shifting circuit is electrically connected to the output port of the decompression circuit, and an output terminal of the data shifting circuit is electrically connected to the input port of the output gating circuit;
the data translation circuit is used for sending the translation-type test vectors in a set data period, and the output gating circuit is also used for gating and sending the output data of the data translation circuit.
6. The integrated circuit test apparatus of claim 1, wherein the compression processing unit comprises a compression circuit and a protocol decoding circuit;
the output port of the compression circuit is electrically connected with the response input port of the vector storage module, the input port of the compression circuit is electrically connected with the output port of the protocol decoding circuit, and the input port of the protocol decoding circuit is electrically connected with the feedback output port of the signal conversion circuit;
the protocol decoding circuit is used for carrying out protocol decoding output on the test response of the protocol class, and the compression circuit is used for carrying out compression output on the test response output by the protocol decoding circuit.
7. The integrated circuit test apparatus of claim 6, wherein the compression processing unit further comprises a data reordering circuit and an input strobe circuit;
the input port of the compression circuit is electrically connected with the output ports of the protocol decoding circuit and the data rearrangement circuit respectively, the output port of the input gating circuit is electrically connected with the input ports of the protocol decoding circuit and the data rearrangement circuit respectively, and the input port of the input gating circuit is electrically connected with the return output port of the signal conversion circuit;
the input gating circuit is used for gating the protocol decoding circuit or the data rearrangement circuit according to the type of the test response, and the data rearrangement circuit is used for carrying out data rearrangement on the test response of a non-protocol class and carrying out online verification on the test response of a storage rule class.
8. The device for testing an integrated circuit according to claim 1, wherein the programmable circuit is an FPGA chip or a CPLD device.
9. The integrated circuit testing device of claim 1, further comprising a controller, wherein the controller is electrically connected to the vector storage module and the programmable circuit, respectively;
the control machine is used for sending a test control signal to the programmable circuit and sending the compressed test vector to the vector storage module for storage.
10. The integrated circuit testing device of claim 9, wherein the controller is further configured to update the programmable logic and control algorithm in the programmable circuit based on the test protocol, the test rule data, and the vector offset data.
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| CN116157694A (en) * | 2020-11-26 | 2023-05-23 | 华为技术有限公司 | Control circuit, control method thereof and integrated circuit chip |
| CN113009317B (en) * | 2021-02-20 | 2024-03-29 | 上海燧原科技股份有限公司 | Interface conversion circuit, chip test system and method |
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